US 8587076

Here's a concise summary of US Patent 8587076:

US Patent 8587076

• Title: Semiconductor device
• Current Assignee: Advanced Integrated Circuit Process LLC
• Inventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
• Filing Date: 2012-07-12
• Issue Date: 2013-11-19
• Abstract: A semiconductor device includes a high dielectric constant gate insulating film formed on an active region in a substrate, a gate electrode formed on this insulating film, and an insulating sidewall on each side of the gate electrode. The high dielectric constant gate insulating film continuously extends from under the gate electrode to under the insulating sidewall. At least the part of the insulating film under the sidewall has a smaller thickness than the part under the gate electrode.

Plain-Language Overview of Independent Claims (inferred from the "Summary of the Invention" section due to the absence of explicit claim text in the provided document):

• Independent Device Claim 1 Overview: This claim describes a semiconductor device featuring a high dielectric constant gate insulating film on a substrate's active region, with a gate electrode on top of it. Crucially, an insulating sidewall is on each side of the gate electrode. The high dielectric constant gate insulating film is continuous, extending from directly under the gate electrode to under the insulating sidewall, and the portion of this film under the sidewall is thinner than the portion under the gate electrode.

• Independent Device Claim 2 Overview (describing a device with multiple sidewalls): This claim details a semiconductor device where the insulating sidewall comprises a first insulating sidewall and a second insulating sidewall, with the first sidewall positioned between the gate electrode and the second sidewall. The high dielectric constant gate insulating film extends continuously from under the gate electrode to under the first insulating sidewall, and the part of this film under the first insulating sidewall is thinner than the part under the gate electrode. (Note: The patent summary presents several variations of this multi-sidewall configuration, which would typically be dependent claims or separate independent claims, each specifying different thickness relationships for the high dielectric constant gate insulating film under the various sidewalls).

• Independent Method Claim 1 Overview: This claim outlines a method for fabricating a semiconductor device, involving the steps of:
  a) Forming a high dielectric constant gate insulating film on an active region of a substrate.
  b) Forming a gate electrode on the high dielectric constant gate insulating film.
  c) Etching the part of the high dielectric constant gate insulating film located outside the gate electrode to reduce its thickness. This etching occurs after the gate electrode is formed.
  d) Forming an insulating sidewall on a side surface of the gate electrode, after the etching step.

CAFC 2026 Dockets:
As of April 26, 2026, a direct search of the CAFC 2026 dockets for patent number US8587076 was not possible with the provided tools, as the search results for CAFC dockets only offer general information and links to PDF schedules for specific months (e.g., April, May, June 2026). Without direct access to searchable docket content for patent numbers, it cannot be authoritatively confirmed whether US8587076 is involved in any CAFC litigation in 2026. The Google Patents information for US8587076 indicates "Family has litigation" and mentions "PTAB case IPR2025-01093 filed (Not Instituted - Procedural)", "PTAB case IPR2025-00831 filed (Not Instituted - Procedural)", and "US case filed in Texas Eastern District Court" for 2024, but this does not confirm active CAFC dockets for 2026.