US 5784584

I'll search for the specific patent and any current litigation status.

Search scope and method

I searched for the literal identifiers 5784584 / 5,784,584 across general web results, USPTO-derived bibliographic pages (Google Patents, PatentCenter listings), PTAB/reexamination records surfaced in secondary sources, and Federal Circuit dockets/opinions for 2026. No 2026 CAFC docket or 2026 decision asserting, invalidating, or otherwise addressing U.S. Patent No. 5,784,584 was located. The most recent Federal Circuit activity I could verify involving this patent is a 2008 Rule 36 summary affirmance (details below). I am flagging that as a negative finding, not proof of absence — a PACER/CM-ECF or USPTO PatentCenter query would be needed to be definitive.

Two cautionary notes on identifier collisions (consistent with your instruction not to auto-correct or conflate):

• The 2026 Federal Circuit decision in medmix / Xiniial (No. 2024‑1516, June 15, 2026) construes "at least two ramps" in a "'578 patent." That is a different patent — a fluid-mixing/dosing device — not US 5,784,584. I am excluding it.
• JP5784584B2 ("Click chemistry with heterogeneous catalysts") is an unrelated Japanese patent. Excluded.

1. Bibliographic data — US 5,784,584

Term note: Because the priority application predates the June 8, 1995 URAA effective date, the term ran to the greater of 17 years from issue or 20 years from earliest filing. 17 years from 1998-07-21 = 2015-07-21, matching the listed expiration. The patent has therefore been expired for more than a decade and cannot be asserted now.

2. Abstract (verbatim)

"A high-performance microprocessor system using instruction that access operands and instructions located relative to the current instruction group rather than located relative to the current instructions, as is the convention, is disclosed herein. The microprocessor system includes a central processing unit, memory, and a bus connecting the central processing unit and memory. An instruction fetching unit, connected to the bus, is provided for fetching instruction groups from the memory for use by the central processing unit and for storage within an instruction register. An instruction supplying unit operates to supply, in succession from the instruction register to the central processing unit, one or more instructions from each of the instruction groups. The system further includes an instruction decoder for configuring the instruction supplying unit to select, from the instruction register, operands associated with instructions from particular instruction groups."

The commercial significance attributed to this patent in the "Moore Microprocessor Patent" (MMP) portfolio was multiple instruction fetch — fetching four 8-bit instructions per memory cycle into a 32-bit instruction register, and positioning operands relative to instruction-group boundaries rather than relative to individual instructions.

3. Independent claims — plain-language overview

⚠️ Uncertainty disclosure: the authoritative text I retrieved for this patent was truncated before the claims section, so I cannot reproduce the full claim set verbatim. The following is based on (a) the Summary of the Invention, which recites three parallel aspects matching three independent claims, and (b) the verified text of claim 29 as quoted in the district court's claim construction opinion in Technology Properties Ltd. v. Matsushita Electric Industrial Co. Treat claim numbering below claim 29 as inferred, not confirmed.

(A) System/apparatus claim (independent — likely claim 1).
A microprocessor system with a CPU, memory, and a bus. An instruction-fetch unit pulls instruction groups from memory over the bus into an instruction register. Each group contains at least one instruction that accesses operands and/or instructions, and — the key limitation — those operands/instructions are located relative to the instruction group, not relative to the individual instruction. An instruction-supply unit feeds the sequential instructions of the group to the CPU one at a time, and a decoder configures that supply unit to select the right operand out of the same instruction register.

(B) Microprocessor claim (independent).
The same core idea framed device-level: a CPU plus an instruction register, where the fetch unit delivers groups that may contain operands and/or sequential instructions, the supply unit successively couples those instructions to the CPU, and the decoder lets the supply unit pick operands for particular instructions out of the register.

(C) Method claim — claim 29 (confirmed text).
"In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and operands from said memory to said central processing unit comprising the steps of:

• providing instruction groups to said instruction register from said memory wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an operand or an instruction or both, said operand or instruction being located at a predetermined position from a boundary of said instruction groups;
• decoding said at least one instruction to determine said predetermined position;
• locating said predetermined position; and
• supplying, from said instruction groups, using the predetermined location, said operand or instruction or both to said central processing unit."

Claim constructions applied to the '584 (from the Matsushita Markman opinion):

• "Instruction" = "a command to a processor that tells the processor what operation to perform."
• "Boundary of said instruction groups" = "beginning or end of an instruction group."
• "Supplying, from said instruction groups, using the predetermined location, said operand or instruction or both to said central processing unit" = "using the results of the locating step in the step of transferring the bits from the accessed operand or instruction to the central processing unit."
• "Instruction register" = "a hardware element that receives and holds an instruction group as it is extracted from memory; the register either contains or is connected to circuits that interpret the instructions in the group."

The separate E.D. Tex. Markman ruling that broke the litigation turned on the term "instruction groups."

4. Prosecution, reexamination, and ownership history

• Reexamination 90/008,225, filed 2006-11-15, Art Unit 3992 (Examiner Banankhah). A Notice of Intent to Issue a Reexamination Certificate was mailed 2009-04-21, i.e., the '584 survived reexamination, with the certificate issuing thereafter. Contemporary reports indicate the PTO had earlier issued an office action rejecting the asserted claim over prior art, and that the asserted claim was amended during reexamination. I could not retrieve the certificate itself, so the exact final wording of the surviving claim remains unverified.
• Assignment chain (per the Google Patents assignment record): Patriot Scientific Corp. (original) → Technology Properties Limited (recorded 2003-12-08, from Charles H. Moore) → Moore, Charles H., TTE UTD 03/21/2006 The Equinox Trust (recorded 2009-03-24), with Patriot Scientific Corp. and Technology Properties Ltd. also appearing as listed assignees. Various security interests (Swartz Private Equity, Lincoln Ventures, Knobbe Martens) were recorded 2001–2003 and released 2005–2012.

5. Litigation history (historical; nothing pending in 2026 that I could verify)

• John Doe / declaratory-judgment actions (pre-2005): Patriot Scientific sued TPL, Daniel Leckrone, and Charles Moore over ownership of the MMP patents, including the '584.
• USDC E.D. Tex. (Marshall), filed Oct. 2005 — Technology Properties Ltd., Inc. v. Fujitsu, et al., asserting US 5,809,336, 5,784,584, and 6,598,148 against Fujitsu, Matsushita/Panasonic, JVC, NEC, and Toshiba entities. ARM Holdings intervened in September 2006 and became a defendant; the allegation was that certain ARM cores infringed a single claim of the '584.
• Claim construction (June 15/18, 2007) on "instruction groups" went against TPL. TPL stipulated to a partial judgment of non-infringement as to the '584 to obtain immediate appellate review, removing ARM and its core families (ARM7, ARM9, ARM9E, ARM10E, ARM11, Cortex) from the Texas trial.
• Federal Circuit, May 9, 2008: summarily affirmed (Fed. Cir. R. 36) that ARM products do not infringe US 5,784,584. ARM characterized this as the first final court ruling on any MMP patent. Concurrently, the PTO reexamination had rejected the asserted '584 claim over 11 prior-art references.
• N.D. Cal., 5:08-cv-00882 — HTC Corporation et al. v. Technology Properties Limited et al. Named the '336, '584, '749, and '148 patents. The '584 was dismissed from that case by stipulation on 2010-03-25.
• German counterpart litigation also produced claim-construction analysis of the '584 (reflected in the Technology Properties Ltd. v. Matsushita Electric Industrial Co. opinion).
• Federal Circuit No. 14-1317 appears in the Google Patents/Unified Patents litigation listing for this family. I could not retrieve its subject matter, parties, or outcome, and I will not speculate — treat as unresolved.

2026 CAFC check: nothing found. Given the patent expired July 21, 2015, and given that every '584 campaign concluded years ago, the absence of 2026 appellate activity is entirely consistent with the record.

6. Explicit uncertainty list

1. Full claim set not verified. My authoritative source was truncated before the claims; only claim 29's text (via a court opinion) is confirmed verbatim, and the number of independent claims and their exact numbering below that are inferences from the specification's Summary section.
2. Post-reexamination claim text not retrieved. The certificate issued after April 2009, but I could not obtain its amended claim wording.
3. CAFC 14-1317 — referenced but not substantiated.
4. "Assignee" is ambiguous in the databases, which list three entities (Equinox Trust, Patriot Scientific, Technology Properties Ltd.) without a clear current sole owner.
5. Truncated specification text limited my review to roughly the first half of the patent's Description.

I'll research the litigation history for US patent 5784584. Let me start with the known litigation links from the patent record and then verify current status.

Let me dig deeper into the specific cases associated with the Moore Microprocessor Portfolio (MMP), of which the '584 patent is part.

Let me verify the specific case numbers and parties from the patent record.

Litigation Involving U.S. Patent No. 5,784,584

Important caveats up front. I was not able to pull live results from the Unified Patents caselist or PACER directly in this session — I hit tool limits. The following is compiled from (a) the litigation metadata embedded in the Google Patents record for US 5,784,584, (b) federal court opinions/orders (Justia, Studicata, Supreme Court docket appendix), (c) the ITC complaint in Technology Properties v. Samsung et al., and (d) contemporaneous press releases. Where I could not independently confirm a party mapping or case number, I say so explicitly. Note also that Google Patents' litigation tab is aggregated at the patent family level, so some entries below involve sibling patents in the Moore Microprocessor Patent (MMP) portfolio rather than the '584 patent itself. I distinguish those.

The patent itself

• US 5,784,584 — "High performance microprocessor using instructions that operate within instruction groups" (also described commercially as "Multiple Instruction Fetch").
• Inventors: Charles H. Moore and Russell H. Fish, III.
• Division of Ser. No. 07/389,334 (filed Aug. 3, 1989, now US 5,440,749); filed June 7, 1995; issued July 21, 1998.
• Part of the Moore Microprocessor Patent (MMP) Portfolio, jointly held by Technology Properties Ltd. (TPL, "TPL Group") and Patriot Scientific Corp., licensed through Alliacense (a TPL Group enterprise). Current assignees of record include Patriot Scientific Corp., Technology Properties Ltd., and the Charles H. Moore Trust (Equinox Trust).
• Expired – Lifetime; anticipated expiration July 21, 2015.

A. Cases in which the '584 patent itself was asserted or put at issue

B. Related portfolio/enforcement actions (family-level; '584 not the patent at issue)

• TPL & Patriot v. HTC — E.D. Tex. Nos. 2:08-cv-00172 (filed Apr. 25, 2008), and also 2:08-cv-00173, -00174, -00176 per the Google Patents record; these asserted the '336 (among others) and were dismissed without prejudice Feb. 13–23, 2009 after the N.D. Cal. court denied TPL's motion to dismiss/transfer.
• ITC Investigation No. 337-TA-853 — Technology Properties Ltd. LLC, Phoenix Digital Solutions LLC & Patriot Scientific Corp. v. Samsung Electronics et al., filed July 24, 2012. Respondents included Acer, Amazon, Barnes & Noble, Garmin, HTC, Huawei, Kyocera, LG, Nintendo, Novatel, Samsung, Sierra Wireless, and ZTE. The asserted patent was the '336 (dual-clock), not the '584.
• N.D. Cal. Nos. 3:12-cv-03865, -03876, -03877, -03880, -03881 (Judge Chhabria) — parallel district-court suits against Huawei/Futurewei, ZTE, Samsung, LG, and Nintendo asserting the '336; summary judgment of non-infringement entered Dec. 13, 2017; affirmed by the Federal Circuit (Nos. 2016-1306/-1307/-1309/-1310/-1311). Supreme Court petition No. 19-324 followed. Not '584.
• N.D. Cal. No. 3:10-cv-00816 — the "Sirius XM Action," listed among the resolved related cases in the Acer/HTC litigation. Whether the '584 was among the asserted patents is not confirmed.
• S.D.N.Y. No. 1:09-cv-04083 and Federal Circuit No. 14-1317 — both appear in the '584 patent's litigation metadata, but I could not confirm the parties or subject matter; they may involve sibling MMP patents. Flagging rather than guessing.
• N.D. Cal. Nos. 3:05-cv-04837, -04844, -04845, and two entries labeled Cal. E.D. (3:05-cv-04838, -04847) — 2005 filings in the patent's metadata. I could not confirm the parties. These may correspond to early Patriot Scientific enforcement/declaratory filings from the 2004–2005 period (Patriot publicly announced suits against Intel, Sony, Fujitsu, Toshiba, NEC and Matsushita in this timeframe), but I could not verify that mapping. (Note the Google Patents "court" labels for these numbers appear to be unreliable.)

C. Ownership and contract disputes touching the '584 patent (not infringement suits)

• Patriot Scientific Corp. v. Technology Properties Ltd., Daniel Leckrone & Charles H. Moore — N.D. Cal., No. C 04-0618 JF. A Stipulated Final Judgment (June 2005) held that "TPL is at least a co-owner of" the '584 patent and six other patents ('336, '148, '749, '890, '703, '915), which unified Patriot's and TPL's interests in the MMP portfolio and gave rise to the Alliacense licensing program.
• Charles H. Moore v. TPL Group & Alliacense LLC (and officers Daniel E. Leckrone, Daniel M. Leckrone, and Michael Davis) — Superior Court of Santa Clara County, No. 110CV183613 (filed ~Oct. 2010), alleging fraud, breach of fiduciary duty and breach of contract; not specifically about the '584.
• Patriot Scientific Corp. v. TPL — San Diego Superior Court (filed ~April 2010), contractual breach over a $1M note; not specifically about the '584.

D. USPTO proceedings (adjacent, worth noting)

The '584 was the subject of ex parte reexaminations filed by NEC and Toshiba. The USPTO issued a Reexamination Certificate for the '584 in July 2009, affirming the claims — a point TPL publicized as validating the portfolio.

Bottom line

Yes, litigation is known. The '584 patent was asserted by the patentee in the 2005 Eastern District of Texas action against Fujitsu, Matsushita, NEC and Toshiba (settled/dismissed in 2007), and it was challenged in declaratory-judgment actions brought by HTC, Acer/Gateway, ASUSTeK and Barco in the Northern District of California (2008–2009), from which the '584 was dismissed by stipulation in the HTC case in 2010 and settled in the ASUSTeK case in 2008. It was also the subject of USPTO reexaminations by NEC and Toshiba (certificate issued July 2009). The patent expired July 21, 2015, so no active infringement litigation on the '584 itself is possible today.

If you need me to lock down the unconfirmed items — the exact E.D. Tex. 2005 case number, the parties for the 2005 N.D. Cal. filings, S.D.N.Y. 1:09-cv-04083, and Fed. Cir. 14-1317 — I'd recommend a targeted PACER/RECAP or Unified Patents caselist lookup, which I was unable to reach in this session.

I'll start by verifying PTAB activity via web search, since the structured ODP block reports none.

Let me dig deeper into PTAB-specific proceedings and the reexamination history.

Let me search specifically for any AIA trial records and the CAFC docket referenced in the ODP data.

PTAB / AIA Trial Analysis — US 5,784,584

"High performance microprocessor using instructions that operate within instruction groups"
Charles H. Moore; Russell H. Fish, III — Priority 1989-08-03; filed 1995-06-07 (div. of Ser. No. 07/389,334, now US 5,440,749); issued 1998-07-21; anticipated expiration 2015-07-21

Proceedings overview

There are zero AIA trial proceedings (IPR, PGR, or CBM) on file against US 5,784,584 — 0 active, 0 claims invalidated by the Board, 0 claims sustained by the Board, 0 settled, 0 institution denials. Bottom line for a defendant: this is not a "hardened by surviving IPRs" patent and it is not a "claims 1–5 canceled by the Board" patent either — the PTAB never touched it. Your defensive posture instead rests on three non-PTAB facts that are collectively stronger than any IPR outcome: (1) the patent expired 2015-07-21, so the § 286 six-year damages lookback closed on (or before) 2021-07-21 and a demand letter in 2026 supports no recoverable damages; (2) the one claim TPL actually asserted in litigation, claim 29, was amended and narrowed in ex parte reexamination — not an AIA trial — with a certificate issuing 2009-07-21; and (3) the asserted claim was held non-infringed by the Federal Circuit as to all ARM core families (Rule 36 summary affirmance, 2008-05-09).

⚠️ Sourcing note / caveat on my own work. The canonical list in your prompt (USPTO ODP) states there are no AIA trial proceedings. I ran targeted web searches to test that and found none either — every PTAB hit for a "584 patent" in my results belonged to a different patent (e.g., 6,066,584, the CeraMedic/Fraunhofer ceramics patent in IPR2015-00398 and IPR2015-00424). I hit my search-step limit before I could run exhaustive PTAB E2E / PTAB-API queries and before I could verify one CAFC docket the ODP record lists (14-1317). Treat the "0 AIA proceedings" conclusion as high confidence but re-verifiable, not as my own independent database pull. Verification URLs are in "Recommended next steps."

AIA proceedings on US 5,784,584

None. No IPR, PGR, or CBM petition has ever been identified against this patent. Consequently there is no proceeding number, no petitioner, no institution decision, no FWD, no settlement, no appeal, no judge panel, and no § 315(e)(2) / § 325(e)(2) estoppel to report. I will not manufacture a proceeding number to fill these fields.

Why no AIA trials? (context, not speculation about intent)

The AIA trial regime began 2012-09-16. By then, the '584 patent's assertion campaign had already been litigated through E.D. Tex. 2:05-cv-494 (Markman 2007-06-18; Fed. Cir. appeal 2008-05-09), N.D. Cal. 5:08-cv-00877 (Acer), 5:08-cv-00882 (HTC), 5:08-cv-05398 (Barco), 3:10-cv-00816, and the patent had already been narrowed in reexamination (certificate 2009-07-21). Per the parties' own N.D. Cal. case-management statement, the five MMP patents-in-suit drew sixteen separate ex parte reexamination requests between September 2006 and early 2010 — the challengers' energy went to reexam, not to the Board.

Nearest-equivalent proceedings (NOT AIA trials — do not cite these as PTAB decisions)

Because a defense team will ask "has anything administrative happened to this patent?", here is the non-AIA record, clearly labeled.

EX PARTE REEXAMINATION of 5,784,584 — third-party requester (identity not established) v. Technology Properties Ltd. / Patriot Scientific Corp.

• Type: Ex parte reexamination under 35 U.S.C. §§ 301–307 (not an AIA trial)
• Filed: reexamination request(s) filed on or before 2008; the '584 patent was among five MMP patents hit by 16 requests commencing September 2006
• Status: Certificate issued 2009-07-21; a further request filed 2009-10-02 was denied 2009-11-04
• Reexamined claims: public filings indicate the asserted claim was claim 29 and that the proceeding involved claims 29–54. Claims 29–54 were finally rejected by the examiner on 2008-12-05 over (per contemporaneous reporting) approximately 11 prior-art references; the patent owner then substantively amended claim 29, which was allowed as patentable, and the '584 patent emerged on 2009-07-21 with amended claim 29.
• Confidence / gaps: The 2009-07-21 certificate and the amended claim 29 are confirmed by the N.D. Cal. Barco order (Judge Jeremy Fogel) and by contemporaneous reporting. ⚠️ I could not verify from a primary source the final certificate disposition of claims 30–54 (whether they were carried as rejected/cancelled or separately confirmed). The assertion that "30–54 remain rejected" comes from a party's case-management filing quoted on an investor message board (low-reliability secondary source) — treat as unconfirmed. Do not tell a court that claims 30–54 are cancelled without pulling the reexam certificate (US 5,784,584 C1) from Patent Center/Global Dossier.
• Defensive value: An amended independent claim means § 252 intervening rights arguments and prosecution history estoppel are live, and the pre-2009 claim-29 scope is off the table. Amendment also means the claim carries a narrowed construction with the amendment's own record supporting it.
• Estoppel note: Ex parte reexamination creates no statutory estoppel. A third-party requester that lost in reexam may still raise the same art in district court. So no administrative estoppel shields this patent.

CAFC APPEAL — Technology Properties Ltd. v. ARM, Ltd. / ARM, Inc.

• Type: Appeal from E.D. Tex. 2:05-cv-494 (Judge T. John Ward); not a PTAB appeal
• Disposition: Rule 36 summary affirmance, 2008-05-09, per curiam (Dyk and Prost, Circuit Judges, with Judge Hochberg, D.N.J., sitting by designation)
• What it decided: TPL/Patriot stipulated to non-infringement of the '584 patent under the district court's construction of "instruction groups" (from the 2007-06-18 Markman ruling) to accelerate the appeal; the Federal Circuit affirmed. The judgment of non-infringement is binding as to the ARM7, ARM9, ARM9E, ARM10E, ARM11 and Cortex core families.
• Link: https://www.courtlistener.com/opinion/[209905](/patent/209905)/tech-properties-limited-v-arm-ltd/ · Markman opinion: https://law.counselstack.com/opinion/technology-properties-ltd-v-matsushita-electric-industrial-co-txed-2007
• Defensive value: If a demand letter today targets a product using an ARM7/9/9E/10E/11/Cortex core, there is a binding Federal Circuit non-infringement judgment on the only claim-in-suit. That is the single most useful citation in this file.

N.D. CAL. — Barco N.V. v. Technology Properties Ltd., Patriot Scientific Corp., Alliacense Ltd., No. 08-5398-JF

• Filed: 2008-12-01 (DJ action on the '584, '749, '890 patents)
• Disposition: 2009-07-21 reexam certificate issued (amended claim 29) → defendants proffered a covenant not to sue on the '584 patent → 2010-02-19 order dismissing the '584 declaratory-judgment count for lack of Article III jurisdiction; attorneys' fees denied without prejudice.
• Defensive value: Confirms the patent owner's practice of issuing covenants not to sue to moot DJ claims when claim 29's scope is unfavorable — a tactical read on how they behave when pressed.

Family-level signals from the ODP litigation record (context only)

• Three 2008 N.D. Cal. DJ actions (Acer/HTC/Barco) and E.D. Tex. cases (2:05-cv-00173/00174/00176, 2:05-cv-00494) — these are district-court matters, not PTAB matters.
• ODP lists a Federal Circuit case 14-1317 under "family has litigation." ⚠️ I could not verify its subject matter with the tools available. It may relate to a sibling MMP patent ('336 / '749 / '148 / '890) rather than the '584. Do not represent it as an appeal of an AIA trial or of the '584. Docket: https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/14-1317
• No defensive aggregator appears in the chain. The Unified Patents links on the Google Patents page are data attribution for the district-court litigation dataset, not evidence that Unified filed a validity challenge. No IPR filed by Unified Patents, RPX, or any similar entity is on record for this patent.

Strategic summary

Claim status: CANCELED vs. SUSTAINED vs. UNTESTED. No claim of US 5,784,584 has ever been cancelled, confirmed, or held unpatentable by the PTAB — the entire patent is UNTESTED at the Board. What exists is an ex parte reexamination outcome: the asserted claim, claim 29, was amended (narrowed) and carried forward in the 2009-07-21 certificate; the fate of claims 30–54 is not verified on my end and must be pulled from the certificate. Practically, for assertion purposes the "live" claim is amended claim 29, and its pre-2009 scope is lost. Claims 1–28 were never the subject of the MMP assertion campaign and are effectively untested backwater — a plaintiff citing them today would be citing claims the portfolio owner never relied on, and the whole patent is expired, which makes their assertion economically inert.

Estoppel landscape. There is essentially no administrative estoppel wall: (a) no IPR/PGR/CBM means § 315(e)(2) and § 325(e)(2) do not apply at all — no petitioner or privy is barred from raising anything; and (b) ex parte reexamination carries no statutory estoppel, so a third-party requester that lost (or prevailed) in reexam can re-run the same § 102/§ 103 art in district court. The flip side: a defendant today faces no § 315(b) one-year clock problem (there is no IPR to file, and filing one on an expired patent yields nothing of value), and no estoppel-based limitation on which prior-art grounds remain available — everything in the § 102/§ 103 universe, plus § 112 defenses (which no IPR could have addressed anyway), remains open. The real constraints on a defendant are non-estoppel ones: claim 29's amended scope, § 252 intervening rights, and the now-expired term.

Pattern signals. This patent was enforced as part of the Moore Microprocessor Patent (MMP) portfolio jointly owned by TPL and Patriot Scientific, licensed through Alliacense, in a broad campaign (2005 E.D. Tex. suits against Fujitsu/Matsushita/NEC/Toshiba; 2008 N.D. Cal. DJ suits; 2012 N.D. Cal. suits against Huawei/ZTE/Samsung/LG/Nintendo). The challenger community's response was reexamination-heavy, not PTAB-heavy — because the assertions predate the AIA and because claim 29's scope was the pressure point. The patent owner did aggressively pursue appeals (2007 Markman appeal; the '336 line went up twice, CAFC 16-1306 et al. and 18-1439 et al., affirmed 2019-02-06). No same-party multi-petition pattern exists. The absence of any IPR is itself the story: a patent asserted this widely for a decade and never drawn to the Board, then expired — the market priced it out rather than invalidated it.

Recommended next steps

1. Do not respond to a 2026 demand letter as if it is enforceable. The patent's anticipated expiration was 2015-07-21. Under 35 U.S.C. § 286, damages reach back only six years from filing — the last date on which suit could have captured any infringing sales was on or about 2021-07-21. A new assertion in 2026 is time-barred as to damages and cannot support injunctive relief on an expired patent. Make that the first paragraph of any response.
2. Pull the reexamination certificate, not a PTAB record. Search US 5,784,584 C1 (issued 2009-07-21) in USPTO Patent Center / Global Dossier (https://patents.google.com/patent/[US5784584C1](/patent/US5784584C1)/en may or may not be populated) and the reexam file wrapper. You need: the exact text of amended claim 29, and the certificate's disposition of claims 30–54. Until you have that, do not assert claim-level cancellation to a court — I deliberately declined to do so above.
3. Weaponize the ARM judgment. If the accused product uses an ARM7/ARM9/ARM9E/ARM10E/ARM11/Cortex core, cite Technology Properties Ltd. v. ARM, Ltd. (Fed. Cir. 2008-05-09, Rule 36 affirmance; E.D. Tex. 2:05-cv-494) — https://www.courtlistener.com/opinion/209905/tech-properties-limited-v-arm-ltd/. Also cite the 2007-06-18 "instruction groups" construction (514 F. Supp. 2d 916) as the construction that defeated the claim.
4. If you must run an AIA-style challenge, know it is a formality play. On an expired patent the Board construes under Phillips and the proceeding's only value is a judicial cancellation finding supporting a § 285 / defense posture. Before filing, re-verify there is truly nothing on file at PTAB E2E (https://ptabtrials.uspto.gov/) and via the USPTO PTAB API (https://developer.uspto.gov/api-catalog/ptab-api) — the ODP ingest your prompt relies on can lag. Also check whether § 315(a)(1) bars your client if it already filed a DJ action on this patent's invalidity (the 2008–2010 N.D. Cal. cases show this portfolio draws DJ suits).
5. Verify CAFC 14-1317 before citing it. It appears only as a family-level litigation link in ODP. Confirm on PACER/CourtListener whether it involves the '584 and what it held. Do not characterize it as an AIA appeal.
6. Flag the low-reliability source. One of the more granular claim-level data points I found (claims 29–54 finally rejected 2008-12-05; amended claim 29 allowed 2009-04-21) comes from a party's CMC filing reproduced on an investor message board — cite it only as a lead to the primary reexam record, never as authority.

I'll research this patent's assignment chain. Let me start with targeted searches.

Good context on the MMP portfolio. Now let me dig for the recorded assignment metadata (reel/frame, correspondents) and the litigation history.

Let me try to pin down recorded reel/frame data and the Alliacense/TPL commercialization structure.

US 5,784,584 — Assignment & Ownership Analysis

Source note (read first). The authoritative record for this patent is the USPTO Assignment Center (https://assignmentcenter.uspto.gov/) and the legacy Assignment Search (https://assignment.uspto.gov/patent/index.html). In this session I was able to retrieve the Google Patents legal-events table, which mirrors the USPTO assignment index (https://patents.google.com/patent/US5784584/en), showing conveyance type, assignor, assignee and event date — but not the reel/frame numbers or the correspondent of record. I was unable to open the Assignment Center directly. Accordingly, every reel/frame field below is marked NOT RETRIEVED, and I have not guessed at any reel number, correspondent name, or execution date. The dates shown are the event dates as recorded by Google Patents/USPTO; where execution differs from recordation, that difference is not visible in the data I have.

Inventors

Unusual patterns worth flagging:

1. Inventor interests were split from each other almost immediately and stayed split for ~15 years. Moore's interest was conveyed to Technology Properties Limited on 2003-12-08; Patriot held Fish's interest via the Fish Family Trust/Nanotronics chain. The result was divided co-ownership of a single patent family, which produced Patriot Scientific v. TPL, Leckrone and Moore (title/inventorship litigation pending through 2004–2005).
2. The patent face names an assignee (Patriot Scientific Corp) even though a named inventor separately conveyed his interest to a different entity 14 years post-issuance. That is the fingerprint of an unresolved or incomplete original assignment, not a clean corporate chain.
3. Moore's interest moved again on 2009-03-24 into his own revocable trust (Equinox Trust, UTD 03/21/2006), i.e. an estate-planning transfer that fractured title further rather than consolidating it.

Original assignee

Patriot Scientific Corporation (San Diego / Carlsbad, California; OTC Bulletin Board: PTSC), per the "Original Assignee" field on the issued patent.

• Line of business at the time. A fabless microprocessor developer. Patriot designed and marketed the PSC1000 / "ShBoom"/IGNITE family of 32-bit stack-based RISC microprocessors, licensed the core (General Dynamics licensed the IGNITE microprocessor in 2003; Sun Microsystems was named a silicon partner), and supplied development tools. Its IGNITE/INFLAME core technology is the natural commercial embodiment of the invention described in this patent.
• Did they ship a product embodying the claims? Moderate confidence: yes, in core/licence form, on a small scale — the patent's specification (44-pin package, on-chip RAS/CAS DRAM control, 4-instruction fetch) describes the PSC1000-class part Patriot was promoting. I cannot confirm from the sources retrieved whether high-volume production silicon embodying issued claim 29 (as amended in reexamination) was ever sold by Patriot. By 2003 Patriot had repositioned itself as an intellectual-property licensing company rather than a silicon vendor.
• Current status. Unclear. Patriot Scientific remained a small publicly traded IP-holding company and remains a named plaintiff/co-owner in litigation as late as the 2019 Supreme Court petition in TPL v. Huawei (No. 19-324), where it is described as "publicly held." Investor-board evidence suggests the PTSC ticker/board was later associated with a differently named registrant, but I could not verify a merger, name change, or dissolution with confidence. Treat the current corporate status as unverified.
• The patent is jointly owned in practice: the Federal Circuit and N.D. Cal. pleadings repeatedly state the patents "are owned jointly by Defendants Technology Properties Ltd. (TPL) and Patriot Scientific Corp." (see Barco N.V. v. Technology Properties Ltd., N.D. Cal. 5:08-cv-05398).

Assignment timeline

The USPTO assignment index (as mirrored by Google Patents legal events) shows ten recorded events. All reel/frame numbers and correspondents were not retrievable in this session and are so marked.

• 2001-11-20 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Security Interest (secured party interest)
  • Assignor: Patriot Scientific Corporation
  • Assignee: Swartz Private Equity, LLC
  • Correspondent: NOT RETRIEVED
  • Context: Securitization — collateral for Patriot's equity line of credit with Swartz (the $30M facility that went effective 2000-07-06).

• 2002-05-23 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Convertible Debenture (note Article IV)
  • Assignor: Patriot Scientific Corporation
  • Assignee: Lincoln Ventures, LLC
  • Correspondent: NOT RETRIEVED
  • Context: Securitization — distressed-issuer convertible financing; patent pledged as collateral.

• 2002-08-05 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Convertible Debenture
  • Assignor: Patriot Scientific Corporation
  • Assignee: Lincoln Ventures, LLC
  • Correspondent: NOT RETRIEVED
  • Context: Securitization — second debenture recording against the same collateral pool in under three months.

• 2002-09-03 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Amended Secured Promissory Note and Addendum
  • Assignor: Patriot Scientific Corporation
  • Assignee: Swartz Private Equity, LLC
  • Correspondent: NOT RETRIEVED
  • Context: Securitization — restructured/amended note, again pledging patent collateral.

• 2003-02-14 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Security Interest
  • Assignor: Patriot Scientific Corporation
  • Assignee: Knobbe, Martens, Olson & Bear, LLP (law firm)
  • Correspondent: NOT RETRIEVED
  • Context: Fee lien — outside counsel took a security interest in the patent, consistent with a cash-constrained client funding enforcement litigation.

• 2003-12-08 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Moore, Charles H. (named inventor)
  • Assignee: Technology Properties Limited (TPL Group, Cupertino/Sunnyvale, CA)
  • Correspondent: NOT RETRIEVED
  • Context: Transfer-to-asserter / consolidation of inventor interest. This is the pivotal link: the inventor's undivided interest moves into a licensing-only entity. Patriot filed infringement suits against Intel, Sony, Fujitsu, Toshiba, NEC and Matsushita on 2003-12-23/24 — 15–16 days later.

• 2005-08-08 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Termination of Security Interest
  • Assignor: Knobbe, Marten, Olson & Bear, LLP
  • Assignee: Patriot Scientific Corporation
  • Correspondent: NOT RETRIEVED
  • Context: Release — lien discharged, clearing title for the June 2005 portfolio unification.

• 2009-03-24 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Moore, Charles H.
  • Assignee: Moore, Charles H., Trustee UTD 03/21/2006, The Equinox Trust
  • Correspondent: NOT RETRIEVED
  • Context: Estate planning / internal transfer only. No change in beneficial control; title moves into Moore's revocable trust. Recorded while the '584 reexamination was pending (USPTO notice of intent to reexamine issued 2009-04-21).

• 2012-02-10 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Release by Secured Party
  • Assignor: Lincoln Ventures, LLC
  • Assignee: Patriot Scientific Corporation
  • Correspondent: NOT RETRIEVED
  • Context: Release — decade-old convertible-debenture collateral interest finally cleared.

• 2012-02-10 (recorded) / execution date not shown — Reel NOT RETRIEVED

  • Conveyance: Release by Secured Party
  • Assignor: Swartz Private Equity, LLC
  • Assignee: Patriot Scientific Corporation
  • Correspondent: NOT RETRIEVED
  • Context: Release — paired with the Lincoln release above; title cleanup in the same year the TPL/Phoenix Digital N.D. Cal. campaign (3:12-cv-03865 et al.) was launched.

Not in the recorded-assignment chain but material to ownership (surfaced from SEC-filed contracts, not assignment records): the Master Agreement dated 2005-06-07 among Patriot Scientific, Technology Properties Limited Inc. and Charles H. Moore, and the Commercialization Agreement among P-Newco, TPL and Patriot, by which TPL was granted full responsibility and authority for commercialization and licensing of the unified ten-patent portfolio, and the "MSD Patents" were moved to a new joint entity (P-Newco) via Newco Licenses. These are contract/licence instruments (Patriot Scientific 10-K exhibits), not recorded assignments, but they are the operative enforcement structure for this patent.

Timeline diagram

timeline
    title Ownership of US 5784584
    1989 : Priority application filed by Moore and Fish
    1998 : Patent issued naming Patriot Scientific
    2001 : Security interest to Swartz Private Equity
    2002 : Debentures recorded to Lincoln Ventures
         : Amended note recorded to Swartz
    2003 : Fee lien recorded by Knobbe Martens
         : Moore assigns interest to Technology Properties
         : Patriot sues Intel Sony Fujitsu Toshiba NEC Matsushita
    2005 : Knobbe lien terminated
         : Patriot and TPL unify the portfolio
    2009 : Moore interest moved into Equinox Trust
         : Reexam amends claim 29
    2012 : Lender releases recorded
    2015 : Patent reaches full term

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT (qualified).
The inventor's undivided interest was conveyed to Technology Properties Limited on 2003-12-08 — a licensing-only entity with no product line. The portfolio was then administered through purpose-built vehicles: Alliacense (TPL's licensing arm, "responsible for managing the patents on behalf of the TPL Group and its partner Patriot Scientific"), and Phoenix Digital Solutions LLC, a joint entity in which "more than 10% of the membership interest… is held by Patriot Scientific Corporation" (Corporate Disclosure Statement, TPL LLC v. Huawei, No. 19-324, 2019-09-06). Qualification: the name suffix is "Limited"/"LLC" rather than the "IP/Patents/Licensing/Holdings/Ventures" pattern, and I did not verify a registered-agent address or single-membership structure. The finding rests on the function (no products, licensing-only, purpose-built assertion vehicles), not the naming.

2. Known asserter in the chain — PRESENT.
TPL/Alliacense does not appear on the enumerated lists (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Spangenberg), but it squarely fits the catch-all criterion of an entity "surfaced by Unified Patents or RPX as a high-frequency plaintiff." Evidence: Google Patents' own litigation block for this patent lists 11+ US cases across N.D. Cal., E.D. Cal., E.D. Tex., S.D.N.Y. and the Federal Circuit (No. 14-1317); Technology Properties Ltd. v. Matsushita, E.D. Tex. 4:05-cv-00494 (claim construction 2007-06-15); the five consolidated N.D. Cal. actions 3:12-cv-03865/03876/03877/03880/03881; and contemporaneous reporting that "more than 150" companies were put on notice of likely infringement.

3. Repeat correspondent across the chain — UNCLEAR.
The correspondent of record field is not exposed in the data I could retrieve, so I cannot test recurrence. I will not infer it. The adjacent, verifiable counsel data (which is litigation counsel, not assignment correspondent, and therefore not a substitute) is: Townsend, Townsend and Crew LLP identified contemporaneously as "PTSC/TPL's lead patent litigator," and Bunsow De Mory LLP (Denise M. De Mory) as counsel of record for TPL/Phoenix Digital/Patriot in the Federal Circuit appeals and the 2019 cert petition. Flagging these as leads to check against the Assignment Center correspondent field, not as a finding.

4. Cascading transfers — NOT PRESENT (for the defined pattern).
There is no chain of consecutive LLC-to-LLC assignments inside 24 months. What exists instead is a dense cluster of five secured-party recordings against Patriot in 27 months (2001-11-20 Swartz; 2002-05-23 and 2002-08-05 Lincoln; 2002-09-03 Swartz; 2003-02-14 Knobbe), followed by inventor→TPC in 2003 and Moore→his own trust in 2009. These are liens and an estate-planning transfer, not a shell cascade. Different signal, different label.

5. Pre-litigation transfer — PRESENT.
Moore's assignment to Technology Properties Limited was recorded 2003-12-08; Patriot's first infringement suit wave (Intel, Sony, Fujitsu, Toshiba, NEC, Matsushita) was filed 2003-12-23/24 — roughly two weeks. The pattern repeats at the portfolio level: the 2005-06-07 Master Agreement unifying title preceded the E.D. Tex. Matsushita action (4:05-cv-00494). This is the cleanest signal in the chain.

6. Bankruptcy fire-sale — NOT PRESENT.
Patriot exhibited severe financial distress (Swartz equity line, two Lincoln convertible debentures, a law-firm fee lien, warrants renegotiated in 2003) but I found no Chapter 7 or Chapter 11 filing and no §363 patent sale involving this patent. Distress financing ≠ bankruptcy fire-sale.

7. Privateering — NOT PRESENT (for the defined pattern).
The classic fact pattern requires an operating company with products funding an NPE to assert against its competitors. Here the two owners are both IP-holding entities: Patriot (an IP company from ~2003) and TPL (a licensing firm and Moore's CTO employer). The 2005 Master/Commercialization Agreements pooled rights and gave TPL enforcement authority with revenue sharing — a joint enforcement arrangement between two non-practicing owners, not an operating company using a proxy. I found no SEC, EFF or Patent Progress coverage alleging privateering by a product-making manufacturer here.

8. Defensive aggregator — NOT PRESENT.
The chain never terminates at RPX, AST, LOT, Unified Patents or OIN. The inverse finding is real, though, and worth recording: the '584 specifically was neutralized after reexamination. USPTO gave notice of intent to reexamine on 2009-04-21; the patent emerged on 2009-07-21 with an amended claim 29; a further reexam request was denied 2009-11-04; TPL then proffered covenants not to sue and dismissed the '584 from the Barco (N.D. Cal. 5:08-cv-05398, dismissed 2010-02-19) and HTC (5:08-cv-00882, stipulated 2010-03-15) actions. The '584 was dropped from the enforcement campaign thereafter — the 2012 campaign and the Fed. Cir. appeals ran on the '336 patent.

Verdict

NPE — high confidence.

Two or more strong signals are documented, not inferred: (a) shell/licensing-only transfer — named inventor Charles H. Moore conveyed his undivided interest to Technology Properties Limited, a licensing-only entity, recorded 2003-12-08, with the portfolio thereafter administered by Alliacense and asserted through purpose-built vehicles including Phoenix Digital Solutions LLC; and (b) pre-litigation transfer — Patriot's first infringement wave against Intel, Sony, Fujitsu, Toshiba, NEC and Matsushita followed that recording by roughly two weeks (2003-12-23/24), with the same sequence at portfolio level in 2005. Corroborating: the known-asserter status of TPL/Alliacense (E.D. Tex. 4:05-cv-00494; five consolidated N.D. Cal. actions 3:12-cv-03865 et seq.; Federal Circuit 14-1317, 16-1306, 18-1439; cert petition No. 19-324) and the distinct fact that the '584 was separately neutralized in 2009–2010 by reexamination plus covenants not to sue.

Caveat on confidence: no reel/frame or correspondent data was retrievable in this session, so signals 3 (repeat correspondent) and the reel-level citations are unresolved rather than negative. Verify the chain and pull the correspondent fields at https://assignmentcenter.uspto.gov/ (search patent number 5784584) — a single recurring recording attorney across the 2003–2012 entries would raise this from high-confidence to documented beyond dispute.

I'll start by searching for the specific patent US5784584 and its citation records.

Let me retrieve the detailed citation records for US5784584, including its "References Cited" and related family members.

Let me access the full patent document and citation records directly.

I hit the tool-step ceiling while trying to pull the complete "References Cited" list off the face of the patent, so I'll report exactly what the search surfaced and clearly flag what I could not verify rather than filling gaps from memory.

US 5,784,584 — Citation and Prior-Art Analysis

1. Patent identification (confirmed against retrieved records)

Sources: Google Patents US5784584A; US5784584 PDF; EveryPatent US5784584.

Note: I searched literally for 5784584 and did not substitute similar numbers. A parallel family member frequently appearing in results — US 5,809,336 — is a different patent and is not treated here.

2. Frequency-of-citation note before the analysis

US 5,784,584 is the "multiple instruction fetch" member of the portfolio the industry press calls the Moore Microprocessor Portfolio (MMP). Multiple licens and litigation sources describe it as covering "fetching multiple instructions":

• InformationWeek / Nokia license release — "U.S. Patent 5,784,584, which covers fetching multiple instructions."
• Design-Reuse, HP license release — same characterization.
• Docket Alarm, N.D. Cal. 5:08-cv-00882 — the '584 patent was one of four MMP patents challenged; it was voluntarily dismissed from that case on March 25, 2010.
• Design-Reuse, TPL Texas streamlining release — the dispositive disputed term was "instruction groups" as construed in the E.D. Tex. Markman ruling; a partial judgment of non-infringement was entered so TPL could appeal the construction (Matsushita/Fujitsu/NEC/Toshiba/ARM defendants).

3. References cited — what I could confirm, and the limit of my confirmation

Important candor statement: The retrieved copy of the front-page citation block for US 5,784,584 was truncated in the search results I obtained. I could only positively confirm the following two U.S. patent references from the patent's own "[56] References Cited" material. I could not verify the complete list (there may be additional U.S. references, foreign references, or non-patent literature). I am not going to invent the remainder.

3.1 Confirmed cited U.S. patent references

(a) U.S. Patent No. 4,967,326

• Citation form (as it appears): "4,967,326 — 10/1990 — May"
• Issue/publication date: October 1990
• Field classification slot in the '584 front page: 395/376–384 area (instruction processing / program control)
• Brief description: I could not verify this document's title or disclosure text in this session. I can only confirm it was cited on the face of the '584 patent with inventor/date as above. I am explicitly not supplying a description from memory, per the no-fabrication rule.
• Potential § 102 exposure: Unknown/unverified. Cannot responsibly assign claim numbers.

(b) U.S. Patent No. 5,127,091

• Citation form (as it appears): "5,127,091 — 6/1992 — Bonfaval et al."
• Issue/publication date: June 1992
• Brief description: Again unverified in this session; confirmed only as a face citation with inventor/date as above.
• Potential § 102 exposure: Unknown/unverified. Cannot responsibly assign claim numbers.

Caveat on both: These are examiner citations, i.e., they were of record during prosecution and the claims as issued (and later reexamined) were allowed over them. That is a strong signal neither reference alone anticipates the independent claims — but I cannot confirm that conclusively without the actual reference texts, and I will not assert it as fact.

3.2 Prior art discussed in the specification itself (non-citation, background art)

The '584 specification names, without front-page citation, the following as representative of the prior art:

• Motorola 68000 and Intel 80X86 families — characterized as the "brute force / complex instruction set" approach.
• Sun SPARC and Intel 8960 — characterized as RISC microprocessors. (I am reproducing "Intel 8960" exactly as the patent text states it; I am not correcting that identifier.)

These are background characterizations, not anticipation references, and none is assigned a claim under § 102.

3.3 Related-family / prosecution context (not "prior art" in the § 102 sense, but relevant to citation scope)

• U.S. 5,440,749 — parent application Ser. No. 07/389,334, the division source.
• U.S. 5,809,336 — separate MMP patent, sometimes confused with the '584 number; distinct document.
• U.S. 6,598,148 — separate MMP patent (decoder/instruction-group related), cited in the HTC declaratory-judgment suit.

4. § 102 bottom line

Because I could retrieve only two face citations and could not open their full texts, I cannot in good conscience map specific references to specific claims of US 5,784,584 under 35 U.S.C. § 102. Doing so would require the actual disclosures of U.S. 4,967,326 and U.S. 5,127,091 set against each independent claim (and the reexam certificate claim set, which per the EveryPatent listing includes claims numbered into the 20s — i.e., claims added/amended during the 2006 ex parte reexamination).

What I can state with confidence:

1. US 5,784,584's confirmed face citations are U.S. 4,967,326 (May, Oct. 1990) and U.S. 5,127,091 (Bonfaval et al., Jun. 1992), plus the prior art families recited in the background (Motorola 68000, Intel 80X86, Sun SPARC, "Intel 8960").
2. Both confirmed citations are examiner cites of record from a case that proceeded to issuance and survived two ex parte reexaminations (certificate US 5,784,584 C1), which makes single-reference § 102 anticipation by either one unlikely — a judgment about outcome, not a claim-by-claim holding.
3. The single most litigated limitation is the term "instruction groups," not any particular prior-art reference; the E.D. Tex. construction of that term drove the partial non-infringement judgment and the TPL appeal.

What I recommend to close the gap: run the USPTO Patent Center / PatFT "References Cited" and the reexamination file-wrapper (90/008,299 and 90/008,225) for the '584 patent, which will produce the complete, authoritative citation list — including any non-U.S. references and non-patent literature my search did not surface. I'll gladly complete the reference-by-reference § 102 table once those texts are in hand.

Did the search results contradict anything I previously understood? No — the licensor characterization ("multiple instruction fetch") and the litigation history are consistent with the patent's own disclosure, and I have preferred the retrieved records throughout.

I'll start by pulling the actual prior-art citations of record for US5784584, since the patent text itself names several prior-art systems but the "Prior Art" citation list is what an examiner would have considered.

Let me pull the complete "[56] References Cited" list from the patent's front page and the related family.

Obviousness Analysis — U.S. Patent 5,784,584 (35 U.S.C. § 103)

0. Evidentiary basis (what the "Prior Art section of this page" actually gives me)

Before analyzing, I must be precise about what the supplied page contains and what it does not, because it materially limits the confidence of the conclusions.

What the page provides (authoritative):

• Full description, abstract, classifications, and bibliographic data for US 5,784,584 (https://patents.google.com/patent/US5784584/en).
• The applicant's own "Description of the Prior Art" (Background §2) and the body discussion of other machines.
• A machine-extracted "Definitions" block (Google's keyword summary — not the claims) and "Prior art keywords: instruction, microprocessor, groups, register, operand."

What the page text does not contain: a complete [56] References Cited list and the full claim set. I recovered only a partial front-page OCR showing two U.S. patents of record:

• 4,967,326 (10/1990, May, class 395/800)
• 5,127,091 (6/1992, Bonfaval et al.)

Identifiers reproduced literally; I could not verify the content of either reference, and the OCR string "Bonfaval" may or may not be the correct spelling in the printed patent. Treat the mapping of those two references to specific claim elements as unverified.

Admitted prior art on the face of the patent (usable as §103 evidence per MPEP 2129):

• CISC: Motorola 68000, Intel 80X86 families.
• RISC: Sun SPARC (expressly stated to use a five-cycle instruction pipeline) and the "Intel 8960" RISC microprocessor (printed literally; likely the i960/80960, but I do not auto-correct it).
• Skip-on-condition machines: "Other machines (such as the PDP-8 and Data General NOVA) provide the ability to skip a single instruction."
• Stack/implied-operand calculation: Hewlett-Packard RPN calculators (expressly contrasted with TI calculators).
• Multiprocessing/column-latch context: INMOS transputer.
• Family fact: the patent is a division of Ser. No. 07/389,334, filed 1989-08-03, now U.S. 5,440,749 — so the effective filing date is 3 August 1989 (pre-AIA §103(a) governs).
• Litigation is extensive (N.D. Cal., E.D. Cal., E.D. Tex., S.D.N.Y., Fed. Cir. 14-1317); a forum post reports an ex parte reexamination 90/008,225 (filed 2006-11-15) with the '584 "IN" (certificate to issue). That reexam item is anecdotal (https://www.ariva.de/forum/patriot-scientific-der-highflyer-2006-[261359](/patent/261359)) and I could not confirm the certificate's scope. Note that a reexamination can only use patents and printed publications — a real limitation for a challenger.

1. Person of ordinary skill in the art (PHOSITA), August 1989

B.S. in electrical engineering or computer science plus 2–3 years of microprocessor/computer-architecture experience, or an M.S. plus ~1 year — with working knowledge of instruction decode, instruction buffers/queues, stack machines, DSP engines, and DRAM memory controllers. Microprocessor design is a predictable art, which matters under KSR Int'l v. Teleflex, 550 U.S. 398 (2007).

2. The invention, element by element

From the Summary and Abstract, independent claim 1 is directed to:

1. CPU + memory + bus;
2. instruction fetching means fetching instruction groups from memory over the bus;
3. each group containing ≥1 instruction that accesses operands or instructions, with operands and instructions located relative to the instruction groups;
4. an instruction register receiving a first group containing sequential instructions;
5. instruction supplying means supplying, in succession, the sequential instructions of that group to the CPU; and
6. instruction decoding means configuring the supplying means to select from the instruction register an operand associated with one of the instructions of that group.

From the claims text I did recover (claims 20–29, http://www.everypatent.com/comp/pat5784584.html), the dependent/subcombination claims add:

• a counter selecting a predetermined position in the group, with the decoder supplying counter-control and operand-control signals (cl. 20);
• SKIP: fetch the next group, reset the counter to zero, supply the first instruction (cl. 21);
• a loop counter and MICROLOOP: decrement the loop counter, reset the position counter to zero, re-supply preceding instructions in the same register (cl. 23), optionally conditioned on a predefined condition (cl. 24);
• branch-type instruction handling conditioned on a flag, and supplying a subsequent group as an operand (cl. 27–28);
• a method claim (cl. 29).

Dependent claims also recite 8/16/24-bit right-justified operands and a four-instruction, single-memory-cycle fetch.

The point of novelty is narrow: it is not multiple-instruction fetching, not an instruction register/queue, not skips, and not hardware loops per se. It is locating the operand relative to the instruction group (right-justified in the fetch word) rather than relative to the individual instruction, plus the counter/decoder combination that selects that operand, and the group-atomic SKIP/MICROLOOP behaviors.

3. Prior-art landscape and proposed §103 combinations

Ground 1 — Group-buffered fetch + group-atomic skip + loop-back re-execution

Primary: IBM S/360 Model 85 instruction buffer with "loop mode" (IBM Systems Journal, Vol. 8, No. 1, 1969; IBM 360/85 Functional Characteristics GA22-6919) and CDC 6600/7600 instruction stack (instruction parcels held in a stack and re-executed from the stack in tight loops without refetch); comparable implementations in the IBM 3033 and Amdahl 470V/6 instruction buffers.
Secondary (admitted): PDP-8 and Data General NOVA skip-on-condition instructions; RISC art — Patterson & Ditzel, "The Case for the Reduced Instruction Set Computer," Computer Architecture News 8(6), Oct. 15, 1980; Patterson, "Microprogramming," Scientific American, Mar. 1983 (both surfaced in my searches).

Mapping: Group fetch into a buffer = cl. 1 elements 2–4; a byte-select pointer in a fixed-width buffer = cl. 20 counter; "flush the buffer and refetch" = cl. 21 SKIP; loop mode re-executing buffered instructions under a count = cl. 23 MICROLOOP.
Motivation (KSR): The '584 itself identifies the problem — "the bottleneck in most computer systems is the memory bus… the ability to fetch four instructions in a single memory bus cycle significantly increases the bus availability to handle data." The 360/85 and 6600 attack the identical problem by the identical mechanism (buffer a group, recycle it). Once fetch and decode are group-atomic, making SKIP group-atomic (discard the remainder, latch the next group, reset the pointer) is the natural and predictable consequence of the group being the unit of operation — a textbook "predictable variation" and "design choice" under MPEP 2144.02/.03. The applicant concedes PDP-8/NOVA single-instruction skip, so the only delta for cl. 21 is "skip up to three," which is dictated by the chosen group size (4 bytes). Reasonable expectation of success: high; loop mode was demonstrated hardware a decade earlier.

Ground 2 — Operand located relative to the fetch word (right-justified multi-byte operand)

Primary: byte-oriented variable-length instruction machines in which the operand follows the opcode and extends across subsequent bytes of the same fetched word — IBM 1130, HP 2116/2100, Data General NOVA, PDP-11 extension words, and the 8080/8086 immediate-operand formats.
Secondary: IBM 801 (Cocke & Markstein, 1980) and the RISC literature for single-cycle, register/stack-oriented execution.
Mapping: cl. 1 element 3 ("operands… located relative to the instruction groups") and the right-justified 8/16/24-bit operand claims.
Motivation: The applicant's own design premise — "most operations can be specified with 8-bit instructions," to shrink code and fit four instructions in one 32-bit fetch — creates the problem that operand bits have nowhere to live. The known answer in the byte-machine art is to let the operand occupy following bytes of the same fetch unit and to fix the least-significant bit position (right-justification) so that one shift aligns the operand for the datapath. That is a routine encoding choice with a predictable result, and it is the only place in the spec where operands are described as group-relative. KSR: "a known technique used to improve a similar device in the same way."

Ground 3 — Hardware MICROLOOP with a loop counter

Primary: single-chip processors with a hardware repeat/loop counter and no instruction refetch during the loop: TI TMS32010 (1982–83) "RPT" (repeat next instruction); TMS320C25 (1986) block repeat with a dedicated repeat counter (BRC) and repeat-end pointer; NEC μPD7720 DSP "repeat" instructions; Motorola DSP56000 (1986–87) REP/REPEAT with a loop counter; AT&T DSP16 (1988) do-loops.
Secondary: IBM 360/85 loop mode (Ground 1); the admitted NOVA/IBM-1130 "ISZ" counter-index-skip construct.
Mapping: cl. 23–24 (loop counter, decrement, clear the position counter, re-execute preceding buffered instructions).
Motivation: DSP designers added hardware repeat counters for exactly the reason the '584 states — the inner loop of a filter should not pay instruction refetch. Same field (single-chip processors), same problem (fetch bandwidth), same structure (counter + pointer to the buffer). The '584's own claim that "Microloops are a unique feature" is contradicted by five years of DSP practice; the MICROLOOP claim is the most vulnerable.

Ground 4 — Prefetch-ahead, opcode predecode, and single-cycle branches

Primary: instruction prefetch/branch handling in the IBM 360/91 and in the RISC machines the applicant admits (SPARC's overlapping pipeline phases; the i960's instruction prefetch); the generic practice of predecoding opcode bits to determine whether a memory reference is required.
Mapping: the prefetch-on-nonzero-MSB scheme and claims 25–28 (branch-type handling conditioned on a flag; supplying a subsequent group as an operand).
Motivation: Prefetch and predecode are time-honored, low-risk optimizations. Using the most significant bits of all four buffered bytes to trigger the next group fetch is a routine microarchitectural choice; single-cycle branch execution is achieved by the admitted "increment/decrement to the next/previous page" trick rather than by any structural difference. The patent's asserted benefit ("debugging is… easier because the user doesn't have to visualize five instructions simultaneously in the pipe") is a result, not a patentable difference.

Ground 5 — Stack/implied-operand architecture (relevant if unrecited stack elements appear in the '584's broader claims; squarely pertinent to parent U.S. 5,440,749)

Primary: the applicant's own admitted HP RPN stack calculators; Forth/stack-engine prior art — Novix NC4000 (1985) and the published Forth-chip/RTX-2000 literature (1985–88); the INMOS transputer (admitted).
Mapping: the push-down stack supplying implied top-of-stack/next-of-stack operands, which is what makes the 8-bit opcode possible.

4. Claim-by-claim vulnerability (assessment)

5. What the patentee will argue, and the counter

• Teaching away: Patterson & Ditzel's RISC paper disparages variable-length, memory-operand instructions. Counter: the '584's stated goals are code density and low cost, which is the CISC/byte-machine motivation (Nova, 1130, 8086) — so the natural primary references are the byte machines, not RISC. RISC is used only for the single-cycle/stack execution teachings.
• Non-analogous art: weak — every reference is computer architecture, and all reasonably pertain to instruction fetch and decode.
• Secondary considerations: a challenger must address the nexus to the claimed group-relative operand selection. Evidence of industry adoption (licensing of the "Moore Microprocessor Patent" portfolio, suits against numerous chip makers) can be offered, but mere licensing/litigation volume without claim nexus is weak. Alleged "failure of others" is undercut by the 360/85, 6600, and DSP repeat-counter art.
• Presumption of validity: as an issued patent that apparently survived ex parte reexamination, the claims carry a §282 presumption; a challenger must prove invalidity by clear and convincing evidence, and for a reexamined claim must contend with §307(b)'s estoppel/intervening-rights rules.
• Dependency on claim text: the strongest obviousness case is against the group-relative operand + right-justification and SKIP/MICROLOOP limitations. Until I can read the complete claim set (particularly the unnumbered independent claims), conclusions on claims other than those quoted above are provisional.

6. Bottom line and what must still be verified

1. On the record I can see, claims 20, 21, 23, 24, and 29 are the most likely to be held obvious, over: (a) IBM S/360-85 loop-mode instruction buffer and CDC 6600 instruction stack, in view of the applicant-admitted PDP-8/NOVA skip art and the byte-machine operand-after-opcode art; and (b) TMS32010/C25 or DSP56000 hardware repeat/loop counters, in view of a buffered group fetch.
2. Claim 1's "operand located relative to the instruction group" is the crux and turns on whether the byte-machine references (1130, Nova, PDP-11, 8086) are found to disclose/teach right-justified, fixed-position operands within a group-atomic fetch word.
3. To complete a defensible §103 opinion I still need: (i) the complete [56] list (to confirm what US 4,967,326 "May" and US 5,127,091 "Bonfaval et al." actually teach and whether they are §102(e) art predating 1989-08-03); (ii) the full claim set; (iii) the reexam file 90/008,225 and any Fed. Cir. 14-1317 record; and (iv) pre-1989 printed evidence for the ShBoom/NC4000 system art, since system prior art can only be relied upon if it was published.

I have flagged every statement above that is my reconstruction rather than a verified record citation; the two cited U.S. patent numbers, the "Intel 8960" and "Bonfaval" strings, and the reexamination number are reproduced literally as found and are not corrected.