US 5659703

I'll search for authoritative information on this patent, including any 2026 CAFC docket activity.

Let me search for the patent's claims and any litigation history.

Let me look for the actual claim text of this patent.

US 5,659,703 — Search Report and Summary

Scope and confidence note

Before the substance: two caveats you should weigh.

1. Date discrepancy. Your prompt states the current date is April 26, 2026. My operating environment date is September 30, 2026. I flag this rather than silently normalizing it, and I have searched for 2026 activity covering both windows.
2. Claim text not independently verified. The authoritative full text supplied to me (Google Patents, https://patents.google.com/patent/US5659703/en, fetched 2026-09-30) contains the bibliographic data, abstract, and full specification but the numbered claims themselves were not in the retrieved text. My independent web searches did not surface the verbatim claim set either. The "independent claim" overview below is therefore reconstructed from the abstract and the "Summary of the Invention" section, which in this patent are near-paraphrases of the claim structure — but I cannot certify the claim numbers or exact claim language. Treat that portion as high-confidence-but-unverified.

Bibliographic data (from the USPTO/Google Patents record)

Assignment chain of note (per the record): 1996-10-28 assignment to Patriot Scientific Corporation from Nanotronics Corporation; subsequent security interests held by Swartz Private Equity LLC, Lincoln Ventures LLC, and Knobbe, Martens, Olson & Bear LLP (all later released); 2009-03-24 assignment to the Charles H. Moore Equinox Trust. The record carries a "Family has litigation" flag with a Darts-IP family link (family=23537828).

Family members (per the EPO citation in EP 0 992 881 A1): US 5440749 A; AU 6067290 A; EP 0497772 A; EP 0786730 A; JP 5502125 T; WO 9102311 A; US 5530890 A; US 5809336 A; US 5784584 A; US 5604915 A.

Abstract (verbatim)

"A microprocessor including a central processing unit connected to a push-down stack is disclosed herein. The push-down stack includes a first plurality of latches corresponding to a like first plurality of stack elements, and a second plurality of locations of random access memory corresponding to a like second plurality of stack elements. The first and second plurality of stack elements are provided in a single integrated circuit with the microprocessor. The push-down stack further includes a third plurality of memory locations in a system random access memory, with the third plurality of memory locations corresponding to a like third plurality of stack elements. In operation, up to a first plurality of items initially stored in the first plurality of stack elements are transferred therefrom without accessing the second plurality of stack elements. When the first plurality of stack elements are empty, up to a second plurality of items may be transferred thereto from the second plurality of stack elements. Similarly, up to the second plurality of items may be transferred from the second plurality of stack elements without accessing the third plurality of stack elements. In addition, up to a third plurality of items may be transferred from the third plurality of stack elements to the second plurality of stack elements when the second plurality of stack elements become empty."

Plain-language overview of the independent claims

Reconstructed from the abstract and Summary of the Invention. Claim numbers are NOT verified.

Apparatus claim (a microprocessor with a three-tier stack). The claim is directed to a microprocessor built on one integrated circuit, having a CPU wired to a push-down (LIFO) stack that is deliberately split into three tiers:

• Tier 1 — latches on-chip. A set of latch-based stack elements, the fastest tier. Operations touching only these top elements complete without ever reading the RAM tiers below them.
• Tier 2 — on-chip RAM. A set of RAM locations on the same IC as the CPU, forming the middle tier. When Tier 1 empties, items are refilled into it from here — and again, consuming the Tier 2 items does not require going off-chip.
• Tier 3 — off-chip system RAM. Memory locations in the system DRAM, forming the bottom tier. When Tier 2 empties, items are pulled up from here.

The inventive point, in plain terms: the hardware automatically spills and refills the stack across three levels of storage of increasing latency and decreasing cost, so the programmer sees one ordinary stack while most pushes/pops never leave the fastest tier. The specification describes this as giving "the appearance of a large stack memory operating at the speed of on-chip latches," with tier sizes given illustratively as four latches, sixteen on-chip RAM locations, and off-chip RAM beyond that (FIG. 21, elements 450/452/454/456/458).

Method claim (method of operation — "and method of operation" in the title). The title and the "Summary" language ("During operation, up to a first plurality items... are transferred therefrom...") indicate at least one independent claim in method form, covering the operating steps just described: transferring items out of the top latch tier without accessing the RAM tier; refilling the latch tier from the on-chip RAM tier upon emptiness; and refilling the on-chip RAM tier from off-chip system RAM upon its emptiness.

Pointer limitation (present in the preferred implementation, not necessarily in every independent claim). Where claimed, a first pointer is coupled to the latch tier, a second to the on-chip RAM tier, and a third to the off-chip tier, with the first pointer coupled to the second and the second coupled to the third specifically so that the refill transfers are triggered by the lower tier becoming empty as a consequence of CPU-directed transfers.

CAFC / litigation status relevant to 2026

I found no CAFC 2026 docket activity for US 5,659,703, and I do not believe any exists. Supporting reasoning and what I did find:

• The patent is expired. The record shows "Expired – Lifetime," with anticipated expiration 2014-08-19; a Patriot Scientific SEC Form 10-K states the portfolio's patents "all expired between August 2009 and October 4, 2016." Enforcement of an expired patent is limited to retrospective damages for the statutory look-back window and has long since been foreclosed in practice.
• The relevant historical litigation was the Moore Microprocessor Patent (MMP) Portfolio campaign, in which '703 was one of the seven U.S. patents jointly owned by Patriot Scientific Corporation and The TPL Group and managed by Alliacense. Key events: suits filed in the E.D. Texas and N.D. California against Matsushita/Panasonic, JVC, Toshiba, NEC, and Fujitsu; a June 18, 2007 Markman ruling; December 18, 2007 settlements with Toshiba, Matsushita (Panasonic), and JVC; and a May 2008 CAFC affirmance of non-infringement in favor of ARM (concerning the 'instruction groups' construction, principally US 5,784,584, not '703).
• The last litigation touching the inventors' ownership was the January 29, 2013 settlement between Charles H. Moore and The TPL Group, announced by Patriot Scientific.

Uncertainty statement: I did not have access to a live CAFC docket system in this session. My searches of public sources returned no 2026 appellate proceeding naming patent 5,659,703. If you need a definitive docket negative, that should be confirmed against PACER/CM-ECF and the CAFC's own docket search directly.

What I could not confirm

• Verbatim claim language, claim count, and independent-claim numbering for US 5,659,703. My overview is derived from the abstract and Summary and should not be quoted as claim text.
• Whether a post-2013 reexamination, IPR, or PGR involving '703 exists. I found none, but I did not query PTAB dockets directly.

I'll research litigation involving US patent 5659703. Let me search multiple sources.

Let me search for more specific litigation details.

Let me search more specific sources on the MMP portfolio litigation.

Litigation Report — U.S. Patent No. 5,659,703

1. Patent identification (as verified)

Per the authoritative full text supplied, US 5,659,703 is titled "Microprocessor system with hierarchical stack and method of operation"; inventors Charles H. Moore and Russell H. Fish, III; original assignee Patriot Scientific Corp.; a division of Ser. No. 07/389,334 (filed Aug. 3, 1989; now US 5,440,749); filed June 7, 1995; granted Aug. 19, 1997. Google Patents flags it "Family has litigation" and links a Darts‑IP first‑worldwide‑family‑litigation record (family 23537828).

The '703 patent is one of the seven patents in the MMP (Moore Microprocessor Patent) Portfolio, which for most of its life was jointly owned by Patriot Scientific Corp., Technology Properties Ltd. (TPL), and Charles H. Moore, and managed/enforced by Alliacense (a TPL Group enterprise) and later Phoenix Digital Solutions (PDS).

2. Litigation known to involve the '703 patent / its portfolio

Important limitation up front: My searches did not surface any docket in which US 5,659,703 is expressly identified by number as an asserted patent. It is named by number in the ownership/inventorship dispute (see Case B) and is part of the portfolio asserted across the campaign below, where the patents most commonly identified by number are the '336, '749, '890, '584 and '148 patents. I have flagged where the '703 connection is by portfolio rather than by express number.

Case A — Patriot Scientific's 2004 enforcement suits (dominant relation: portfolio/ownership)

• Plaintiffs: Patriot Scientific Corp.
• Defendants: Sony Electronics Inc., Matsushita Electric Corp. of America, Fujitsu Computer Systems Corp., Toshiba America Inc., NEC Solutions (America) Inc.
• Jurisdiction: U.S. District Court, Northern District of California (Oakland Division)
• Filing date: January 2004
• Outcome/status: Patriot dismissed these actions in 2005 after granting TPL the exclusive enforcement/licensing right, so TPL could sue in Texas. Sources: CNET, eWeek, Patriot PR (Dec. 20, 2005)
• '703 connection: portfolio-level. These suits were reported as asserting "Patriot's patents," with the '336 patent named publicly; the '703 was among the seven patents in the same ownership fight (Case B).

Case B — Patriot Scientific v. TPL / Leckrone / Moore ( '703 expressly named )

• Plaintiff: Patriot Scientific Corp.
• Defendants: Technology Properties Ltd., Daniel Leckrone, Charles H. Moore
• Jurisdiction: N.D. Cal. (per contemporaneous reporting)
• Filing/announcement: November 2004 (litigation publicly confirmed Nov. 13, 2004)
• Subject patents expressly listed by number: US 5,809,336; 6,598,148; 5,440,749; 5,604,915; 5,530,890; 5,784,584; and 5,659,703.
• Outcome: Settled June 2005 — the parties entered a joint venture (50/50 net licensing/enforcement revenue), giving TPL the exclusive enforcement right. Sources: EE Times (Nov. 11, 2004), EE Times (Nov. 23, 2004), Patriot PR (Dec. 2005)
• This is the one case where the '703 is confirmed by number.

Case C — Intel Corp. v. Patriot Scientific Corp. (declaratory judgment)

• Plaintiff: Intel Corp.; Defendant: Patriot Scientific Corp.
• Jurisdiction: U.S. District Court, N.D. Cal.
• Filing date: February 2004
• Outcome: Resolved via the 2005 MMP portfolio licenses to Intel and AMD (Patriot/TPL licensed the portfolio). Source: Semiconductor Digest (Feb. 6, 2004)
• '703 connection: portfolio-level.

Case D — Technology Properties Ltd. v. Japanese manufacturers (Texas infringement action)

• Plaintiff: Technology Properties Ltd. (on behalf of Patriot, TPL and Moore)
• Defendants: Japanese electronics vendors (all but Sony, per press)
• Jurisdiction: U.S. District Court, Eastern District of Texas
• Filing date: ~October/November 2005
• Outcome/status: Patriot publicly characterized this as the vehicle to obtain a faster infringement determination. Source: The Register (Dec. 21, 2005)
• '703 connection: portfolio-level (reported as three jointly owned Moore microprocessor patents; '703 not named).

Case E — 20 Japanese manufacturers v. Patriot / TPL / Moore (five declaratory-judgment suits)

• Plaintiffs: A group of ~20 Japanese electronics manufacturers
• Defendants: Patriot Scientific Corp., Technology Properties Ltd., Charles H. Moore
• Jurisdiction: U.S. District Court, N.D. Cal. (Oakland)
• Filing date: December 2005
• Relief sought: Declaration of non-infringement and invalidity of three jointly owned MMP patents
• Outcome/status: Consolidated/litigated through 2008–2010 in N.D. Cal. before Judge Fogel (the "Moore microprocessor patents" declaratory actions). Source: Patriot PR (Dec. 20, 2005), SEC 10-Q excerpt
• '703 connection: portfolio-level (three of the seven patents; the '703 is not identified as one of the three litigated).

Case F — Alliacense / TPL 2012 enforcement campaign (ITC + district court)

• Plaintiff: Alliacense (TPL Group)
• Jurisdiction: U.S. International Trade Commission (Section 337 investigation 337-TA-853) and U.S. District Court (parallel actions filed July 24, 2012)
• Outcome/status: Multiple defendants; portfolio (MMP) licensing/enforcement ongoing into 2013–2014. Source: Patriot Scientific 10-Q
• '703 connection: portfolio-level; not identified by number in the source.

Case G — Acer et al. v. TPL/Alliacense (declaratory judgment)

• Plaintiff: Acer Inc. et al.; Defendants: Technology Properties Ltd. / Alliacense / (Patriot as applicable)
• Jurisdiction: N.D. Cal. (before Judge Fogel)
• Status: Filed 2008; part of the N.D. Cal. DJ group concerning the '336, '749, '148 and '890 patents. Source: SEC 10-Q
• '703 connection: none identified by number.

3. Cases I expressly excluded (similar-number / non-matching hits)

To comply with your instruction not to return results for similar numbers or unrelated identifiers, I discarded the following search hits:

• JP Patent No. 5659703 B2 (Japanese Patent Office, IHI/弾塑性プレース防震構造 — an elastoplastic brace seismic structure) — a wholly different patent sharing the digits "5659703."
• Renesas Electronics v. Alliacense / HSM Portfolio / TPL, N.D. Cal. 3:2011cv06662 (Dec. 28, 2011) — this concerned Thunderbird Technologies inverter/memory patents licensed to TPL, not the '703 patent. (RPX)
• An unrelated COVID-19 vaccine article URL containing the string "5659703."

4. Bottom line

• The '703 patent is confirmed to have been involved in litigation only as one of the seven patents named in the 2004–2005 Patriot Scientific v. TPL/Leckrone/Moore ownership/inventorship dispute (Case B).
• For the major infringement campaigns (2004 Japanese-vendor suits, the 2005 E.D. Tex. action, the 2012 ITC/district-court actions), the '703 was part of the asserted MMP Portfolio, but the reporting I retrieved identifies the asserted patents by number only as the '336, '749, '890, '584 and/or '148 — not the '703.
• I could not verify specific docket/case numbers (e.g., the N.D. Cal. and E.D. Tex. case numbers) from the sources retrieved in this session. I have deliberately not supplied case numbers I could not confirm. To obtain them, the authoritative next steps are:
  • PACER (N.D. Cal. and E.D. Tex. dockets),
  • Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation/caselist),
  • RPX Empower litigation database,
  • the Darts-IP family record linked from the '703 Google Patents page (family 23537828).

5. Don't-know items (stated explicitly)

• Exact case numbers for Cases A, B, C, D, E and G: not verified.
• Whether the '703 was ever expressly asserted in an infringement complaint (as opposed to being held in the jointly owned portfolio): not established by the sources I retrieved.
• Outcome of the 2012 ITC investigation 337-TA-853 as to the '703: not established.

Recommend primary-source verification in PACER/Unified Patents before relying on any of the above in a filing.

I'll start from the canonical structured list (empty per ODP) and verify against the web.

Proceedings overview

Total AIA trial proceedings on file: 0. The USPTO Open Data Portal structured block returns no IPR, PGR, or CBM proceeding for US 5,659,703, and my independent web search (2026-09-30) surfaced none either — every challenge to this patent family that I could document was filed as an ex parte or inter partes reexamination (pre-AIA), not an AIA trial. The defensive posture this gives a defendant is not "the patent is hardened by having survived IPRs"; it is something stronger and more mundanely fatal to any 2026 demand letter: the patent is expired (anticipated expiration 2014-08-19, status "Expired – Lifetime" on Google Patents), and no AIA trial proceeding exists to fight about. There is no claims-invalidated IPR to cite, but there is also no live patent to license.

No proceeding found — and here is what the record actually shows

I will not invent a proceeding number. The honest output of this task is the negative finding plus the surrounding enforcement history, which is where the defensive value lies.

• Type: N/A — no IPR / PGR / CBM identified.
• Filed: N/A.
• Status: No AIA trial activity on file (ODP structured data); corroborated by web search (2026-09-30).
• Judge panel: N/A.
• Petition grounds: N/A.
• Institution decision: N/A.
• Final Written Decision: N/A.
• Settlement / termination: N/A.
• Appeal: No PTAB-to-Federal Circuit appeal exists, because there is no FWD. Separately, the '703 is a member of the Moore Microprocessor Patent ("MMP") Portfolio, which had a litigation and ownership dispute track running through district court, the ITC, and California state court — see below.
• Defensive value: Do not build a defense around an IPR that does not exist. Build it around (a) expiration, and (b) chain-of-title.

What did happen to this family instead of IPRs (all pre-AIA reexamination, so no § 315(e)(2) trial estoppel attaches):

• Alliacense/TPL publicly claimed the MMP Portfolio "survived 17 re-examination challenges before the USPTO," and specifically that the USPTO affirmed US 5,809,336 after reexaminations filed by NEC, Toshiba, and the Public Patent Foundation and rejected a further attack by HTC, with a reexamination certificate issuing for US 5,784,584 in July 2009 (EE Times, 2009-09-16; Alliacense release; Patriot Scientific quarterly report, 2013-10-15). Those releases name the '336 and '584 patents specifically — I did not find a source confirming a reexamination certificate for US 5,659,703 itself, so I am not asserting one. Note also that a reexam win for the patent owner is a patentability event, not a validity judgment, and carries no IPR-style estoppel against you.
• On the litigation side, the '703 was identified as part of the disputed portfolio in the Patriot Scientific / TPL Group title fight (EE Times, 2004-11-23, listing US 5,809,336; 6,598,148; 5,440,749; 5,604,915; 5,530,890; 5,784,584; 5,659,703). The asserted patents in the main infringement campaigns skewed to the '336, '584, '148, '749, and '890 patents; in HTC Corp. v. Technology Properties Ltd., No. 5:08-cv-00882-PSG (N.D. Cal.), only the '336 patent reached the jury, and the court denied HTC's JMOL of non-infringement (order, Docket No. 707). A related ITC investigation concerning the '336 patent was initiated on 2012-08-24 (per that same order). Ownership was further complicated by Charles Moore's 2010 suit against TPL/Alliacense and by the Patriot/TPL June 2005 unification agreement.

Strategic summary

Claim status. I cannot give you a claim-by-claim canceled / sustained / untested ledger, because no AIA tribunal ever ruled on the claims of US 5,659,703. What I can tell you definitively from the face of the record: the patent's anticipated expiration is 2014-08-19 and it is marked "Expired – Lifetime" (Google Patents US5659703A). That date is consistent with a pre-URAA 17-years-from-issue term running from the 1997-08-19 grant (priority 1989-08-03, divisional of Ser. No. 07/389,334, which issued as US 5,440,749). So the entire claim set — the hierarchical-stack subject matter described in the abstract (a first plurality of on-chip latches, a second plurality of on-chip RAM stack elements, and a third plurality of stack elements in system RAM) — is expired and untestable in any prospective sense. Any reexamination-confirmed or amended claims in this family matter only for the six-year damages lookback under § 286, which for a 2014-expiring patent has long since closed.

Estoppel landscape. There is no § 315(e)(2) estoppel in this family, because no petitioner ever obtained an IPR institution on the '703. That cuts in the defendant's favor in one narrow sense — you are not barred from raising any prior-art ground — but it is largely academic, because you also have no PTAB record to leverage. The prosecution-history record that does exist (reexaminations filed by NEC, Toshiba, the Public Patent Foundation, and HTC across the portfolio, plus the 2007 Eastern District of Texas Markman rulings) is usable for admissions and claim-construction purposes, not as estoppel. Note the asymmetry a licensing plaintiff would exploit: reexam survival is often marketed as "validation," but reexam claims carry § 252 intervening rights if amended, and the reexam record is where a good invalidity case gets rehabilitated, not where it dies.

Pattern signals. No petitioner filed multiple IPRs against this patent; no defensive aggregator (Unified Patents, RPX, etc.) appears in the record I found. The relevant pattern is instead: (1) this is a pre-1995 patent, so most of its enforcement life predated the IPR regime (IPR only became available 2012-09-16, roughly two years before the '703 expired) — that timing, not patent strength, is the most likely reason no IPR was ever filed; (2) the patent owner/co-owners did pursue challenges and appeals in district court and in Europe, and the ownership story is fractured (Patriot Scientific, TPL Group/Alliacense, Phoenix Digital Solutions, and the Moore Equinox Trust all appear in the chain, with the current-assignee field listing the Equinox Trust and Patriot Scientific). Title is a genuine defense here, not a formality.

Recommended next steps

1. Do not commission an IPR. It would be money burned on an expired patent, and the patent bar (§ 311(c)) and estoppel consequences are beside the point — there is no live claim to invalidate and no ability to enjoin or recover for post-2014 conduct. If someone proposes an IPR here, that proposal is defective on its face.
2. Treat an infringement demand on the '703 as facially deficient. Demand a (i) certified copy of the reexamination certificate(s) affecting the '703 specifically, (ii) a claim chart against unexpired conduct, and (iii) proof of the current owner's standing. The pres releases I located confirm reexam certificates for the '336 and '584 patents, not the '703; if a licensor claims the '703 was reexamined-and-confirmed, make them produce the certificate. § 315 estoppel would not have saved them, but a missing certificate is an immediate credibility hit.
3. Run a § 286 damages-timeline wipe. Even on the plaintiff's best case, expired-patent damages reach only infringement within six years before complaint. With the patent expiring 2014-08-19, no 2026-filed complaint recovers anything for post-expiration conduct, and pre-expiration recovery is time-barred.
4. Attack standing and ownership first. The record shows a documented title dispute over these patents (Patriot Scientific vs. TPL Group/Alliacense, resolved by the June 2005 unification agreement; Moore's 2010 fraud/fiduciary suit; the 2014 Alliacense–Phoenix Digital Solutions services/novation agreement). Confirm who actually holds the '703 today before negotiating anything.
5. If a plaintiff points to the MMP reexamination history as "validation," separate the patents. The published reexam wins are for the '336 and '584. Do not let '336/'584 history be imported to the '703, and do not accept "17 reexaminations survived" as a substitute for a claim-level record on the patent you are actually accused of infringing.

Caveat on completeness: I could not query PTAB E2E or Docket Alarm's PTAB index directly in this session, and the ODP ingest underlying the structured block may lag. My search did not surface any AIA trial on this patent, and the absence is well explained by the patent's 2014 expiration. If you have a specific IPR/PGR/CBM number in hand that I did not find, send it and I will pull the institution decision, FWD, and any CAFC docket.

I'll research the assignment record before writing anything. Let me run several searches in parallel.

Good context. Now let me dig for reel/frame specifics and the later chain events.

Now let me chase the later chain events, the 2009 Equinox Trust transfer, and any 2016+ sale.

Assignment Record Analysis — US 5,659,703

Source limitation (read first)

I could not retrieve reel/frame numbers or correspondent-of-record names for this patent. The USPTO Assignment Center (https://assignmentcenter.uspto.gov/) and the legacy assignment.uspto.gov index are JavaScript-driven search applications; my searches returned the Google Patents legal-events mirror of the assignment data (which carries dates, conveyance types, assignors and assignees) but not the reel/frame identifiers or the recording-attorney fields. I have therefore transcribed every assignment event I could verify and marked [NOT RETRIEVED] wherever the brief asks for reel/frame or correspondent. I have not invented those values.

Consequence: NPE signal #3 (repeat correspondent) cannot be assessed at all in this session — which is unfortunate, because it is the single most probative signal in this chain. That gap should be closed by a manual Assignment Center lookup.

Inventors

Unusual patterns worth flagging:

1. Both inventors' interests left the inventors' hands early. Moore's individual interest was ultimately assigned to a trust he controlled — the Charles H. Moore Equinox Trust (UTD 03/21/2006), recorded 2009-03-24. Fish's interest travelled Fish → Fish Family Trust → Nanotronics Corporation → Patriot Scientific (the 1996-10-28 record names Nanotronics as assignor). So by 1997 neither inventor held record title.
2. The two inventors ended up on opposite sides of a title fight. Patriot's November 2004 press statements assert discovery showed Fish was the sole inventor of US 5,809,336, implying improper co-inventorship by Moore on the shared family. This is not a "fire-sale" pattern — it is an inventorship/ownership cloud pattern, and it is material because the same cloud covered '703.
3. Residual inventor-side interest survived 26 years. The Equinox Trust assignment recorded in 2009 shows Moore-side title interests being formalized long after the original filings.

Original assignee

Entity named on the issued patent: Patriot Scientific Corporation (San Diego, CA), per the Google Patents record.

Important discrepancy to flag: the Google Patents "Original Assignee" field reflects the assignee at issuance (1997-08-19), not at filing. The application was filed 1995-06-07 as a division of Ser. No. 07/389,334 (filed 1989-08-03, now US 5,440,749). The first recorded transfer is Nanotronics Corporation → Patriot Scientific Corporation, recorded 1996-10-28 — i.e., after filing but before issuance. On the face of the record, the applicant-of-record on 1995-06-07 was likely Nanotronics Corporation, not Patriot. I state this as an inference from the assignment dates, not verified against the filing papers.

• Primary line of business: Patriot began as a microprocessor developer. It marketed the PSC1000 / "ShBoom" line (licensing Moore's stack-machine designs) and later the IGNITE™ and INFLAME™ array microprocessor brands. By ~2004 it had repositioned itself as an intellectual-property licensing company, describing itself in its own releases as "an intellectual property company."
• Did it ship a product embodying the claims? Ambiguous. The specification itself describes a concrete 44-pin PLCC part, a 2-MB one-card system, and a CPU-on-DRAM die — and Moore's architecture was commercialized. But by the time this patent was asserted (2003–2015), Patriot's revenue was licensing, not product sales. The product-embodiment question is therefore largely moot for the enforcement period.
• Current status: Patriot Scientific continued as a public OTC entity (PTSC) and ultimately a licensing shell; the '703 patent expired 2014-08-19 ("Expired – Lifetime"). I found no Chapter 7/11 filing for Patriot in this session.

Assignment timeline

Dates are as listed in the Google Patents legal-events table. I cannot distinguish execution date from recording date in that data, and that table does not expose reel/frame or correspondent. Conveyance labels are quoted verbatim from the record.

• Recorded 1996-10-28 — Reel [NOT RETRIEVED]

  • Conveyance: Assignment of assignors' interest ("SEE DOCUMENT FOR DETAILS")
  • Assignor: Nanotronics Corporation
  • Assignee: Patriot Scientific Corporation
  • Correspondent: [NOT RETRIEVED]
  • Context: Rights consolidation — Fish-side interests funnelled through Nanotronics into the eventual patent holder.

• Recorded 2001-11-20 — Reel [NOT RETRIEVED]

  • Conveyance: Security Interest (not a transfer of title)
  • Assignor: Patriot Scientific Corporation
  • Assignee: Swartz Private Equity, LLC
  • Correspondent: [NOT RETRIEVED]
  • Context: Securitization — Patriot encumbering the portfolio to raise capital.

• Recorded 2002-05-23 — Reel [NOT RETRIEVED]

  • Conveyance: Convertible Debenture (Note Article IV)
  • Assignor: Patriot Scientific Corporation
  • Assignee: Lincoln Ventures, LLC
  • Correspondent: [NOT RETRIEVED]
  • Context: Securitization / financing — convertible debt collateralized against the patents.

• Recorded 2002-08-05 — Reel [NOT RETRIEVED]

  • Conveyance: Convertible Debenture
  • Assignor: Patriot Scientific Corporation
  • Assignee: Lincoln Ventures, LLC
  • Correspondent: [NOT RETRIEVED]
  • Context: Securitization — second Lincoln Ventures debenture, ~10 weeks after the first.

• Recorded 2002-09-03 — Reel [NOT RETRIEVED]

  • Conveyance: Amended Secured Promissory Note and Addendum
  • Assignor: Patriot Scientific Corporation
  • Assignee: Swartz Private Equity, LLC
  • Correspondent: [NOT RETRIEVED]
  • Context: Securitization — amendment/up-sizing of the Swartz facility. Three lien recordings in ten months indicates acute capital need.

• Recorded 2003-02-14 — Reel [NOT RETRIEVED]

  • Conveyance: Security Interest
  • Assignor: Patriot Scientific Corporation
  • Assignee: Knobbe, Martens, Olson & Bear, LLP
  • Correspondent: [NOT RETRIEVED]
  • Context: Securitization — the patent litigation firm took a lien for unpaid fees. This is a strong financial-distress tell: Patriot was pledging its core patent as collateral to its own lawyers five months before it began suing Intel and others.

• Recorded 2005-08-08 — Reel [NOT RETRIEVED]

  • Conveyance: Termination of Security Interest
  • Assignor: Knobbe, Martens, Olson & Bear, LLP
  • Assignee: Patriot Scientific Corporation
  • Correspondent: [NOT RETRIEVED]
  • Context: Lien release — fees paid off, coincident with the June 7, 2005 TPL unification and first license revenues (AMD, Intel).

• Recorded 2009-03-24 — Reel [NOT RETRIEVED]

  • Conveyance: Assignment of assignors' interest
  • Assignor: Moore, Charles H.
  • Assignee: Moore, Charles H., Trustee, UTD 03/21/2006, The Equinox Trust
  • Correspondent: [NOT RETRIEVED]
  • Context: Estate/asset-planning transfer inside inventor control — not an arm's-length or third-party acquisition. The trust's stated date of 03/21/2006 predates the 2009 recording by three years, so the transfer was executed (or the trust created) well before it was recorded.

• Recorded 2012-02-10 — Reel [NOT RETRIEVED]

  • Conveyance: Release by Secured Party
  • Assignor: Swartz Private Equity, LLC
  • Assignee: Patriot Scientific Corporation
  • Correspondent: [NOT RETRIEVED]
  • Context: Lien release — ten years after the 2002 lien was recorded. A decade-long unresolved encumbrance is itself notable for anyone doing title work.

• Recorded 2012-02-10 — Reel [NOT RETRIEVED]

  • Conveyance: Release by Secured Party
  • Assignor: Lincoln Ventures, LLC
  • Assignee: Patriot Scientific Corporation
  • Correspondent: [NOT RETRIEVED]
  • Context: Lien release — same date as the Swartz release; both legacy debenture encumbrances cleared simultaneously.

Critical omission from the recorded chain: there is no recorded assignment reflecting The TPL Group's co-ownership, even though a June 2005 stipulated final judgment (N.D. Cal., Case No. C 04-0618 JF) stated that "TPL is at least a co-owner of" the '336, '148, '749, '890, '915, '703, and '584 patents, and the June 7, 2005 Patriot/TPL agreement unified the portfolio. The assignment record is therefore incomplete as a title record for this patent. Anyone relying solely on Assignment Center data would miss TPL entirely.

Timeline diagram

timeline
    title Ownership of US 5659703
    1989 : Parent application filed by Moore and Fish
    1995 : Division application filed
    1996 : Assigned to Patriot from Nanotronics
    1997 : Patent issued
    2001 : Security interest to Swartz Private Equity
    2002 : Security interests to Lincoln Ventures
    2003 : Security interest to Knobbe Martens
    2005 : Knobbe lien released
         : TPL ruled at least a co-owner
         : Patriot and TPL unify the portfolio
    2009 : Moore interest assigned to Equinox Trust
    2012 : Swartz and Lincoln releases recorded
    2014 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT.
No entity bearing an "IP / Patents / Licensing / Holdings / Ventures" suffix ever received title. The two "Ventures/Equity" names in the record — Swartz Private Equity, LLC (2001-11-20; 2002-09-03) and Lincoln Ventures, LLC (2002-05-23; 2002-08-05) — are secured lenders, expressly recorded as Security Interest and Convertible Debenture, each followed by a Release by Secured Party on 2012-02-10. Taking title never occurred. Per the brief's own rule, a suggestive name alone is not a finding — and here the conveyance types positively rebut it.

2. Known asserter in the chain — PRESENT (strong).
The portfolio was exclusively commercialized by Alliacense, a TPL Group enterprise dedicated to running "IP Licensing Programs" — per the June 7, 2005 unification release and TPL/Patriot's own licensing announcements. The associated campaign was large-scale and adversarial: Patriot announced suits against Intel, Sony, Fujitsu, Toshiba, NEC and Matsushita (Nov. 2004); TPL filed broad-based infringement claims against Fujitsu, Matsushita, NEC and Toshiba in the E.D. Tex. in October 2005; Patriot had earlier "informed more than 150 other companies they may also be infringing." The 2005–2008 docket included declaratory-judgment actions by HTC, Acer/Gateway and Asustek/Asus against TPL, Patriot, MCM and Alliacense. A TPL ITC complaint against Samsung et al. (naming TPL at 20883 Stevens Creek, with proposed respondents including Amazon, Barnes & Noble, Garmin, HTC, Huawei, Kyocera, LG, Nintendo and Novatel) reflects continued assertion activity into the 2012 era.
Caveat: I was not able to verify in this session that Alliacense appears on a specific RPX or Unified Patents high-frequency-plaintiff list. The "present" call rests on the documented assertion record above, not on a directory match. Also note that Alliacense/TPL is a licensing agent and co-owner, never an assignee of record for '703.

3. Repeat correspondent across the chain — UNCLEAR (data gap).
[NOT RETRIEVED] for all ten events. The assignment data available to me does not expose the correspondent field. I can note one adjacent fact: Knobbe, Martens, Olson & Bear, LLP appears in the chain as a secured party (2003-02-14) — appearing as lienholder rather than correspondent — which itself tells you the firm was Patriot's patent counsel of record in that era. But I cannot state who filed the recordings, and I will not infer an NPE-pattern attorney from this data.

4. Cascading transfers — NOT PRESENT.
There is no chain of back-to-back LLC acquisitions. The five pre-2009 events are three security interests and two notations, not title transfers. The only two title transfers are 1996 (Nanotronics → Patriot) and 2009 (Moore → Equinox Trust), thirteen years apart, with entirely different purposes.

5. Pre-litigation transfer — NOT PRESENT as to recorded assignments; timing pattern present as to the unrecorded unification.
The operative transfer to Patriot (1996-10-28) predates the first named suits by seven years. However, there is a suggestive sequencing: the June 7, 2005 Patriot/TPL unification agreement was followed four months later by TPL's October 2005 E.D. Tex. infringement filings — consistent with the ownership structure being finalized to enable assertion. Because the unification was never recorded as an assignment, this point rests on press releases and a court judgment, not on Assignment Center data.

6. Bankruptcy fire-sale — NOT PRESENT.
No bankruptcy proceeding involving Patriot Scientific or Nanotronics was found. The February 6, 1990 Dun & Bradstreet Receivable Recovery letter to PT Acquisitions shows pre-petition distress at the original commercialization vehicle, and the 2001–2003 lien cluster shows later distress at Patriot — but distress is not bankruptcy, and no sale-in-proceedings occurred.

7. Privateering — PARTIAL.
This is not classic privateering (a market-leading operating company funding an NPE against competitors). It is the inverse-ish pattern: an operating company that converted itself into a licensing entity and then granted exclusive commercialization authority to a third-party licensing agent (TPL/Alliacense) that asserted against the industry. I mark this partially present — the economic effect is the same, the corporate mechanics differ.

8. Defensive aggregator — NOT PRESENT.
The chain terminates at Patriot Scientific Corporation and the Charles H. Moore Equinox Trust (UTD 03/21/2006). No RPX, AST, LOT Network, Unified Patents, or Open Invention Network involvement appears anywhere. The patent was not neutralized by a defensive aggregator.

Verdict

NPE — high confidence.

Justification: the patent's record owner throughout its entire enforcement life (roughly 2003–2014) was Patriot Scientific Corporation, which had converted from a product company into a self-described "intellectual property company," and the portfolio — including '703 — was placed under the exclusive commercialization authority of Alliacense, a TPL Group licensing enterprise, which ran a mass assertion campaign (suits against Intel, Sony, Fujitsu, Toshiba, NEC and Matsushita; a 2005 E.D. Tex. filing; declaratory-judgment actions by HTC, Acer/Gateway and Asustek; an ITC action; and "more than 150" demand letters). The 2003-02-14 Knobbe, Martens security interest — the patent pledged as collateral to Patriot's own litigation counsel — corroborates that the asset was being run as a monetization instrument, not a product line.

Two honest qualifications: (a) the classic troll mechanics are absent — there are no shell LLCs, no cascading transfers, no bankruptcy sale, and no defensive-aggregator endpoint (signals 1, 4, 6, 8 all not present), so this is a well-documented licensing-campaign NPE, not a chain of anonymous shells; and (b) signal #3, the repeat-correspondent test, could not be run at all because reel/frame and correspondent data were not retrievable in this session. If you need the brief's full evidentiary standard met, the single next step is a manual Assignment Center lookup to capture reel/frame and correspondent for the ten events above.

Verification links:

• USPTO Assignment Center — https://assignmentcenter.uspto.gov/
• Legacy Assignment Search — https://assignment.uspto.gov/patent/index.html
• Google Patents legal events for this patent — https://patents.google.com/patent/[US5659703A](/patent/US5659703A)/en (source of all dates and conveyance labels above; carries no reel/frame or correspondent data)

Contradictions and open items relative to the earlier section

1. The earlier summary's "current assignee" field is incomplete as a title statement. It correctly lists Equinox Trust and Patriot Scientific, but the June 2005 stipulated final judgment held TPL "at least a co-owner" of '703, and the June 7, 2005 agreement unified Patriot's and TPL's interests with TPL holding exclusive licensing authority. No assignment recording reflects TPL's interest. The Assignment Center chain and actual equitable title diverge here — flag this if any downstream analysis relies on the recorded chain as complete.
2. "Original assignee: Patriot Scientific Corp" is an issuance-date artifact. On the record, Nanotronics Corporation held the interest at the 1995-06-07 division filing and assigned to Patriot on 1996-10-28, before the 1997-08-19 issuance.
3. The earlier section's note that the patent expired 2014-08-19 is consistent with everything found here, as is the absence of 2026 CAFC activity.
4. Unverified lead: the name "MCM" appears alongside TPL, Patriot and Alliacense in 2008 declaratory-judgment complaints about the MMP patents. I could not confirm whether any MCM-affiliated entity (or any later TPL-affiliated vehicle) ever held an interest in '703 specifically. Treat as a lead requiring a separate assignment-name search, not as a finding.

I'll research the prior art cited against US 5,659,703, starting with the patent's own citation record.

Let me pull the citation record directly from the patent's front page and related databases.

The citation list isn't surfacing in search snippets. Let me pull the patent's front page and the Google Patents "Cited By / Citations" data directly.

I hit the step limit before I could retrieve the patent's front-page citation list. Rather than guess, here is what I verified, what I could not, and the exact route to close the gap — because for this specific patent the gap matters.

Direct answer: I could not retrieve the "References Cited" list for US 5,659,703

The task asks me to walk through "each patent citation for 5659703." The honest result is that I did not obtain that list, and I will not reconstruct it from memory. Two independent reasons:

1. The authoritative full text you supplied does not contain it. The Google Patents text provided to me (fetched 2026-09-30) runs from the bibliographic block through the Abstract, Description, and "Landscapes" classification tree. It omits the "Patent Citations (References Cited)" and "Cited By" table sections that a Google Patents page normally carries below the description. So the citation list was never in my source.
2. My web searches did not surface it. Searches targeting the "References Cited" U.S. Patent Documents block for '703 returned the patent page but only the metadata/landscape fragments — no numbered prior-art list. This is consistent across several queries (Google Patents US5659703A).

Under your strict no-auto-correction, no-fabrication rule, the correct output here is the negative finding plus the verifiable artifacts I did collect.

What I did verify

A. The patent's own identity (unaffected by the missing citations)

• US 5,659,703 A, "Microprocessor system with hierarchical stack and method of operation," inventors Charles H. Moore; Russell H. Fish, III; app. 08/482,185; filed 1995-06-07; granted 1997-08-19; priority 1989-08-03; division of Ser. No. 07/389,334 (now US 5,440,749); "Expired – Lifetime," anticipated expiration 2014-08-19.

Consequence for the prior-art question: because '703 is a division of the '749 application, the prior-art citations of record in the parent (Ser. No. 07/389,334) are the most likely pool from which the '703 front page draws, and the '749 patent's front page is the single best proxy for the '703 citation list. That is a concrete, checkable starting point — I just was not able to pull either front page in this session.

B. One verifiable citation relationship — but it runs the wrong direction

The one citation hit my searches returned with a date and a "Moore et al." pairing is a forward citation, not prior art:

• US 7,080,362 B2 (Nazareth et al.), "Java virtual machine hardware for RISC and CISC processors," issued 2006-07-18, lists US 5,659,703 (Moore et al., 1997-08-19) in its references. Source: Justia, US 7,080,362.

This tells you '703 is cited by later stack/JVM hardware patents (i.e., it is treated as background art in the field of stack-based processor caching). It is not a § 102 reference against '703 and must not be charted as one.

C. A genuinely relevant contemporaneous document (with a caveat)

The closest-in-time technical publication I surfaced on this exact subject matter is:

• "Up pops the 32 bit stack microprocessor," Electronic Engineering, vol. 61, no. 750, June 1989, p. 79, XP000033120.

Caveat, stated plainly: I encountered this reference cited as the closest prior art in the EPO prosecution of EP 0 976 034 B1 (a stack-cache patent), not as a citation on the '703 front page (EP0976034B1). Its relevance is timing and subject matter — it predates the '703 priority date (1989-08-03) and describes a 32-bit stack microprocessor with separate parameter and return stacks whose tops are cached with pointer-based overflow/underflow — which is materially the '703 subject matter. Whether it is actually of record in '703, I could not confirm.

Why I can't complete the § 102 mapping you asked for

Your request has two data dependencies, and both are missing in this session (as the earlier-generated sections already flagged for one of them):

Mapping a reference to "which claim(s) it potentially anticipates under 35 U.S.C. § 102" is only meaningful once I have (i) the reference's actual disclosure and (ii) the claim language it must meet, element by element. I have neither in verified form for this patent. Any § 102 chart I produced now would be invention, not analysis.

How to retrieve the actual citations (primary sources)

To complete the task correctly, pull these, in order:

1. USPTO Patent Center / Image File Wrapper for US 08/482,185 — the "References Cited" list (form PTO-892, "Notice of References Cited") and any examiner-cited references. This is the controlling record.
2. The parent, Ser. No. 07/389,334 / US 5,440,749, front page "References Cited." As the division parent, this is the shortest path to the '703 citation pool.
3. Google Patents US5659703A, the "Patent Citations" and "Cited By" tables (present on the live page even though absent from the text handed to me).
4. Espacenet INPADOC family + "Also published as / Cited documents" for the 23537828 family.
5. Any reexamination record naming '703 specifically (prior sections note reexam activity in this portfolio centered on the '336 and '584 patents; a '703 certificate was never confirmed).

Bottom line

• I did not obtain the patent-citation list for US 5,659,703 and therefore cannot, in this session, name each cited reference with its filing/publication date, a description, and a § 102 claim mapping. I am flagging that as a hard gap rather than filling it speculatively.
• What is verified: the '703's division relationship to US 5,440,749 (the best proxy for its citation pool); one confirmed forward citation (US 7,080,362) that is not prior art; and a highly relevant June 1989 Electronic Engineering article on 32-bit stack microprocessors whose status as a '703 citation is unconfirmed.
• No contradiction with the prior sections — this task simply could not be completed for lack of the two required inputs (claims + citation list), which the earlier sections had already flagged as unverified.

If you can supply either the '703 front page (References Cited) or the '749 parent front page, I will chart every cited reference element-by-element against the claim set and return the § 102 anticipation analysis you asked for.

I'll pull the prior-art/citation record for US 5,659,703 and the key hierarchical-stack references before analyzing.

Let me pull the patent's own front-page reference list and its Cited-By set, since the "Prior Art" section wasn't included in the authoritative text I was given.

The supplied authoritative text contains no numbered "References Cited" table — I'll verify that and hunt for the closest pre-1989 hierarchical-stack art directly.

Obviousness Analysis — US 5,659,703 under 35 U.S.C. § 103

Prepared: 2026-04-26 (my environment clock reads 2026-09-30; flagged, not silently normalized, consistent with the earlier sections)

0. Scope caveats — read before the analysis

Three limitations on what follows, stated up front rather than buried:

(a) The "Prior Art section of this page" was not supplied to me. The task instructs me to use it, but the materials I have in this session are (i) the authoritative full text of US 5,659,703 as fetched from Google Patents, and (ii) the earlier-generated summary, litigation, and PTAB sections. The Google Patents text I received contains the bibliographic block, abstract, and specification but no "References Cited" / "Cited By" citation tables — the fetched text runs from the classification list straight to Definitions/Abstract/Description with no reference table. I therefore cannot enumerate the examiner-cited prior art and will not invent reference numbers. Everything below is either (1) art the patent itself admits on its face, or (2) art I independently retrieved and cite with a URL, or (3) training-data knowledge explicitly flagged as unverified.

(b) Claim text is still unverified. The prior summary flagged that the numbered claims were absent from the authoritative text; that remains true. The limitation decomposition below is built from the abstract and the "Summary of the Invention," which in this patent track the claim structure closely. Do not quote my reconstruction as claim language. If verbatim claims are required, pull the issued patent PDF or USPTO PatentCenter for US 08/482,185.

(c) Identifier discipline. I have not corrected or "fixed" any identifier. Where the patent says "Intel 8960," I quote it as written; I note the possible intended product only as an interpretive aside, not as a correction.

1. Legal framework applied

POSITA definition (used throughout)

A person of ordinary skill in the art as of August 1989 would have: a B.S. in electrical engineering or computer science (or equivalent), and 2–5 years of experience in microprocessor or computer architecture, including familiarity with the then-current RISC literature (Berkeley RISC, Stanford MIPS, IBM 801, SPARC, AMD 29000), the Intel x87 numeric coprocessor stack, and standard graduate-level computer-architecture treatment of memory hierarchies and stack caches. This is a relatively high skill level — the field in 1989 was small and sophisticated, and the references below are the canonical papers and manuals such a person would have read.

2. Decomposition of the claimed subject matter into limitations

Because the claim set is unverified, I analyze by limitation group, keyed to the abstract and Summary (the closest available proxy to the claims):

The crux is L4 + L7/L8. L1, L2, L3, L5, L6, L9 are individually ancient. A two-tier version (registers/latches → off-chip memory stack, with pointer-driven spill/fill on empty) was commercially shipping silicon in 1987–1988. The only genuinely distinguishing element is the interposition of a third, on-chip RAM tier between the latch tier and the system RAM, with pointer coupling extended across three levels.

3. Primary and secondary references

3.1 Admitted prior art on the face of the '703 patent (strongest, no verification burden)

The specification's Background makes express admissions that are usable as prior art against the claims:

• "the Sun SPARC and the Intel 8960 microprocessors" are identified as the exemplars of the RISC approach to which the invention is presented as an alternative. (Background, "Description of the Prior Art.") SPARC's register-window overflow/underflow spill-fill to a memory stack is therefore admitted prior art. This is the single most damaging admission in the document.
• "the Motorola 68000 and Intel 80X86 microprocessor families" — the CISC baseline.
• "the INMOS transputer" — discussed in the specification as an attempted multiprocessor strategy.
• "the PDP-8 and Data General NOVA" — expressly acknowledged as machines that "provide the ability to skip a single instruction."
• Latches are fast but transistor-expensive; on-chip RAM is ~5× slower but transistor-cheap; off-chip RAM is slowest. The patent's own numbers: latches ~3 nsec, on-chip RAM ~15 nsec, off-chip memory 80–220 nsec, on-chip 4–30 nsec. The inventor is thus stating the cost/speed gradient that supplies the motivation to combine, in the document itself.

3.2 Verified art retrieved this session

3.3 Training-data art — flagged as not independently verified in this session

I was cut off by a tool limit before I could verify these by search. I list them with explicit confidence levels so you can triage. Do not put any of these in a chart without pulling the primary document.

4. Grounds of rejection

Ground 1 — Am29000 (1987) in view of the memory-hierarchy principle

Map:

• L1, L2: Am29000 is a single-chip 32-bit RISC CPU with a stack-organized register file and an internal stack pointer (GR1) — ✔.
• L3 (first plurality of latch/register stack elements): the register file's reserved local-register area is implemented in fast on-chip storage, addressed off the stack pointer — ✔ (latch-vs-SRAM categorization is an implementation detail; the Am29000 register file is the fast tier).
• L5, L8-partial (off-chip system RAM tier + refill): the Am29000's spill-to-external-memory / fill-vacant-part trap pair is exactly a two-tier push-down stack with automatic refill on emptiness — ✔.
• L6, L9: transfer of the fast-tier items without touching the memory tier, and pointer-driven triggering off the stack pointer — ✔.
• L4, L7 (the intermediate on-chip RAM tier and the tier-2→tier-1 refill): missing. Am29000 teaches two tiers, not three.

Motivation to close the gap. This is where KSR does the work, and the record is unusually favorable:

1. The general technique is ancient and the field is the same. Adding an intermediate storage level to a two-level hierarchy is the canonical, predictable application of Wilkes (1965) — "a known technique" applied to "a known structure." KSR, 550 U.S. at 417 ("if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill").
2. The patent itself supplies the design incentive. The specification's own speed/cost table (latches ~3 ns but transistor-hungry; on-chip RAM ~15 ns with far fewer transistors; off-chip memory 80–220 ns) is a textbook statement of why one inserts an on-chip RAM level. A POSITA reading that gradient in 1989 would immediately identify the intermediate on-chip RAM tier as the cost-optimal choice. That is the inventor's own articulation of the motivation, and it can be quoted back at him.
3. Finite, identified, predictable solutions. KSR: "When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options." Here there were essentially two options — (i) widen the register file (dies), or (ii) insert an intermediate on-chip RAM stack with spill/fill (the '703's answer). Option (ii) is the cheaper and was predictable.
4. Reasonable expectation of success. Silicon proof existed: SPARC and the Am29000 were shipping; the spill/fill control logic was a solved problem. Nothing in the '703's third tier requires an unpredictable mechanism — the third tier is the same spill/fill mechanism the Am29000 already had, merely extended one level and re-based on a second pointer.

Anticipated patent-owner rebuttal: Am29000's spill/fill is trap/software-handler driven, whereas L9 recites the refill being triggered "as a consequence of transfers directed by the central processor unit." Counter: (i) if the claims do not expressly require hardware-automatic transfer, the trap handler is a transfer triggered by CPU-directed transfers (the very pushes/pops that exhausted the tier) — satisfaction by inherency under Swinehart; (ii) alternatively, hardware overflow detection per se was old (the 8087 raises a hardware stack-overflow condition; SPARC's window invalid mask is hardware). If the claim is limited to hardware-automatic cross-tier transfer, then Ground 1 becomes Ground 1+G and the gap narrows but does not close.

Ground 2 — SPARC (admitted prior art) in view of Am29000

Map: SPARC supplies L1, L2, L3, L5, L6, L8, L9-in-substance (current-window pointer plus window invalid mask, with overflow/underflow traps spilling/filling register windows to a memory stack). Am29000 supplies the generalization of the register file to a variable-size, pointer-managed local register stack ("more flexible since the 'window' size and amount of overlap are variable" — the survey literature's own words). The two together disclose a pointer-managed, variable-depth, stack-organized fast tier backed by a memory stack. Missing: L4's intermediate on-chip RAM tier.

Motivation: SPARC and Am29000 are both named in the '703 as the state of the art the invention improves upon — the field-of-endeavor and "same problem" showings are made by the patent's own words. Motivation to add the intermediate tier is identical to Ground 1's (memory hierarchy + the patent's own cost/speed gradient). Secondary reinforcement: SPARC's fixed 8/16/24-register windows suffer exactly the internal-fragmentation/allocated-but-unused problem that the '703's variable-depth hierarchical stack cures — that is a recognized, articulated engineering problem (the architecture text excerpt retrieved this session discusses precisely this trade-off: fixed-size windows "render implementation considerably simpler" but produce "high internal fragmentation"). A known problem in the prior art supplying the motivation is the strongest possible § 103 posture — it defeats the "no reason to modify" argument outright.

Ground 3 — Two-tier stack art in view of on-chip scratchpad RAM as a stack tier

If the claims' L4 is drafted broadly enough to read on any on-chip RAM used as a stack tier (as the abstract's language — "a second plurality of locations of random access memory corresponding to a like second plurality of stack elements" — appears to permit), then this ground is close to an anticipation-plus-obviousness hybrid:

• Microcontrollers of the era placed a stack in on-chip RAM as a matter of course (on-chip RAM stacks were routine in 8-bit and 16-bit MCU architectures).
• Combine that routine on-chip-RAM-stack teaching with Am29000/SPARC's spill/fill-on-empty off a stack pointer and you have L1–L9 without needing to argue about hardware automation: the on-chip RAM is the stack memory, the register/latch tier is the fast tier, and off-chip DRAM is the bottom tier.
• Motivation: reduce the ~80–220 ns off-chip penalty on the overwhelming majority of stack traffic (the patent's own numbers); exploit the 4–30 ns on-chip SRAM/register speed. Cost/benefit is explicit and the solution is one of two.

Caveat: I could not verify a specific pre-1989 MCU datasheet this session. Verify against a contemporaneous 8051/68HC11-class datasheet before relying on this ground.

Ground 4 — x87 numeric coprocessor stack (8087/80287) in view of Am29000 or SPARC

The 8087's 8-deep, 80-bit hardware LIFO stack with a documented stack-overflow exception whose recovery writes stack contents to memory establishes L3/L4-type behavior (a fixed plurality of hardware stack elements) plus the concept of memory-backed recovery. Combined with Am29000/SPARC's pointer-driven spill/fill, L1–L9 follow. Motivation: the register stack is architecturally shallow; the memory stack is unbounded; the mismatch is the same problem solved by SPARC and the Am29000 means. Confidence: moderate — verify the primary Intel manual.

Ground 5 — KSR "design choice / predictable variation" ground for the specific numbers and pointers

Even if a primary reference is found that discloses all of L1–L8, the dependent-claim-level limitations are separately vulnerable:

5. Secondary considerations (objective indicia) — and why they are weak here

6. Strength assessment and recommended playbook

Ranked grounds:

1. § 102(a)/(b) based on the '703's own admissions + Am29000 — strongest foundation going in.
2. Am29000 + SPARC + memory-hierarchy principle (§ 103) — the workhorse. Closes everything but L4, and L4 is closed by the KSR combination rationale reinforced by the patent's own cost/speed table.
3. SPARC/Am29000 + on-chip-RAM-stack MCU art (§ 103) — potentially near-anticipatory depending on how L4 is construed. Highest upside if the claims are broad.
4. 8087/80287 + Am29000/SPARC (§ 103) — moderate confidence, pending verification.
5. KSR design-choice ground for sizes/pointers (§ 103) — will knock out dependents regardless of which primary ground prevails.

Immediate verification tasks, in priority order:

1. Pull the actual claim set (USPTO PatentCenter / the issued PDF for US 5,659,703). Everything above is limitation-group analysis until this is done. Determine specifically whether L9's "coupled… as a result of transfers directed by the central processor unit" is in independent claim 1 or only in dependents — that single fact swings the difficulty of the whole case.
2. Pull the '703 front-page "References Cited" that I could not retrieve. The examiner's own art list is the fastest route to admissible prior art and may already contain the third-tier reference.
3. Verify the Intel i960 "local register cache" (i.e., the family's literal "Intel 8960") against a 1988–89 i960 datasheet/architecture manual. If it discloses a stack-organized on-chip register cache with a spill/fill fault, it is the single best primary reference for L4 and it is admitted by the patent itself.
4. Verify Am29000 User's Manual (1987) page cites for the spill-to-external-memory and fill-vacant-part language — I have the substance from the survey literature but not the manual's exact pages and figure numbers.

Things I have not done and do not claim: I have not produced a verbatim, element-by-element claim chart, because the claim text is not in the record before me. I have not supplied any patent number for prior art that I could not verify — deliberately, given the strict identifier rule. And I have not assessed the sibling patents ('749, '890, '584, '915, '336, '148), which share the disclosure and would present materially different claim scopes; if the goal is to invalidate the family, the analysis must be run per-patent, and my working hypothesis is that the '584 and '336 patents will be the harder ones, since those are the ones the enforcement campaign actually relied on and the ones with reexamination history.

7. Explicitly stated unknowns

• Verbatim claim language, claim count, independent-claim structure for US 5,659,703: not verified.
• The examiner-cited prior-art list (References Cited): not retrievable in this session — the Google Patents text I was given omits it, and my searches did not surface it.
• Whether the "Prior Art section of this page" the task refers to exists as a separate generated section: it was not included in the materials provided. If it exists, this analysis should be re-run against it; several of my moderate-confidence references (especially the i960 and the x87) would likely be supplied there with proper citations.
• The i960 "local register cache" and the Intel "8960" identification: moderate confidence, unverified.
• The 8087/80287 stack-overflow spill-to-memory recovery procedure: moderate confidence, unverified.
• The Berkeley RISC I/II, IBM 801, SOAR, CRISP, and ROMP references: training-data knowledge, not verified in this session, confidence as flagged in § 3.3.
• Datasheet-level support for on-chip-RAM stacks in contemporaneous microcontrollers (Ground 3): not verified.