US 6598148

I'll search for current docket and status information on this specific patent, then summarize.

Let me look for the actual claim text and any recent 2026 activity.

US 6,598,148 B1 — Verification Summary

Important caveat up front: I could not retrieve the claim text of US 6,598,148 from authoritative sources. The full patent document text you supplied (Google Patents scrape) contains the abstract, description and definitions but not the "Claims" section, and the search results surfaced the claim text only for the parent patent US 5,809,336, not for 6,598,148. My independent-claim summary below is therefore inferred from the abstract and specification and is explicitly flagged as unverified. I did not find any CAFC 2026 docket activity for this patent.

Bibliographic data (verified from the supplied document)

Priority chain (per the specification's first paragraph): 6,598,148 is a divisional of application 08/484,918 (filed 1995-06-07, issued as US 5,809,336), which is itself a divisional of application 07/389,334 (filed 1989-08-03, issued as US 5,982,231). This is a pre-AIA case with a 1989 priority date.

Disclaimer on the expiry: 1989-08-03 + 20 years = 2009-08-03, which is what the record shows. Consistent with a pre-1995 filing, the term ran from the earliest U.S. filing date. I'd treat the "Expired – Fee Related" label with mild caution; an expiration for failure to pay maintenance fees would normally produce a different termination than ordinary end-of-term expiry, and Google Patents attaches these labels automatically.

Abstract (verbatim, from the authoritative text)

"A microprocessor integrated circuit including a processing unit disposed upon an integrated circuit substrate is disclosed herein. The processing unit is designed to operate in accordance with a predefined sequence of program instructions stored within an instruction register. A memory, capable of storing information provided by the processing unit and occupying a larger area of the integrated circuit substrate than the processing unit, is also provided within the microprocessor integrated circuit. The memory may be implemented using, for example dynamic or static random-access memory. A variable output frequency system clock, such as generated by a ring oscillator, is also disposed on the integrated circuit substrate."

Independent claims — UNVERIFIED

I do not have the claim text for 6,598,148 and cannot give you a reliable element-by-element breakdown. What the record supports is the following, and I'm labelling it as inference:

Inferred claim 1 / core independent claim (from the abstract — the abstract of a U.S. patent ordinarily tracks claim 1): A microprocessor integrated circuit comprising, on a single integrated circuit substrate (a) a processing unit that operates in accordance with program instructions held in an instruction register; (b) an on-chip memory capable of storing information provided by the processing unit and occupying a larger area of the substrate than the processing unit (DRAM or SRAM); and (c) a variable output frequency system clock disposed on the same substrate, exemplified as a ring oscillator.

The "memory larger than the processing unit" limitation is the distinguishing feature of this divisional's claim set relative to its parent — the parent's claim 1 as retrieved instead recites the "entire ring oscillator variable speed system clock" plus an on-chip I/O interface and an independent second clock.

Do not rely on this inference. To get the actual independent claims you should pull the granted-claims text from USPTO PatentCenter / Public PAIR or the patentimages PDF (https://patentimages.storage.googleapis.com/81/ef/1b/0f2d82cda03b5a/US6598148.pdf) — I was unable to extract the claims from that PDF via search.

Family claim language that IS verified (US 5,809,336, same specification)

Because these share the specification, this is useful context for what the invention is about — and note the prosecution-history disclaimers that the courts applied:

• '336 claim 1 (retrieved via RPX Insight): "A microprocessor system, comprising a single integrated circuit including a central processing unit and an entire ring oscillator variable speed system clock in said single integrated circuit and connected to said central processing unit for clocking said central processing unit, said central processing unit and said ring oscillator variable speed system clock each including a plurality of electronic devices correspondingly constructed of the same process technology with corresponding manufacturing variations, a processing frequency capability of said central processing unit and a speed of said ring oscillator variable speed system clock varying together due to said manufacturing variations and due to at least operating voltage and temperature of said single integrated circuit; an on-chip input/output interface…; and a second clock independent of said ring oscillator variable speed system clock connected to said input/output interface."
• '336 claim 3 and claim 10 are method claims (clocking the microprocessor with an on-chip ring oscillator; clocking the I/O interface with a second clock).
• '336 claim 6 recites an oscillator whose rate tracks the CPU frequency as a function of "parameter variation in one or more fabrication or operational parameters."

The claim term "entire oscillator"/"entire ring oscillator" was construed narrowly, both in E.D. Tex. (Judge Ward) and in the ITC, to exclude an oscillator that relies on a control signal or an external crystal/clock generator (USITC Pub. 4847, https://www.usitc.gov/publications/337/pub_4847.pdf).

Litigation history on the record (no 2026 CAFC activity found)

Google Patents lists the following cases for this family, all historical:

• Cal. N.D. 3:05-cv-04837, 3:05-cv-04844, 3:05-cv-04845; Cal. E.D. 3:05-cv-04838, 3:05-cv-04847
• Cal. N.D. 5:08-cv-00882 / 3:08-cv-00882; Cal. E.D. 5:08-cv-00877
• N.Y.S.D. 1:09-cv-04083
• Cal. E.D./N.D. 5:10-cv-00816 / 3:10-cv-00816
• CAFC 14-1317 (2014) — the most recent Federal Circuit entry in the record

There is also a well-documented 2004 ownership dispute: Patriot Scientific v. Technology Properties Ltd. (TPL), Daniel Leckrone and Charles Moore over ownership of 6,598,148 and related patents (EE Times, 2004-11-11 and 2004-11-13, https://www.eetimes.com/patriot-rejects-offer-for-processor-patents/ and https://www.eetimes.com/Firm-dismisses-claims-made-by-IP-house-Patriot-Scientific/). This ownership fight is consistent with the current assignee field listing both the Equinox Trust (Moore) and Patriot Scientific.

On your instruction to check "CAFC 2026 dockets": I searched and found no 2026 Federal Circuit docket, appeal, or PTAB proceeding involving 6,598,148. The searches returned unrelated 2025/2026 matters (Novartis/Entresto, AeroVironment, various reexaminations of other patents). Given the patent shows as expired since 2009, active 2026 appellate litigation would be surprising. I cannot rule out a low-visibility 2026 filing, but I have no evidence of one — treat "no 2026 activity found" as the accurate statement rather than "none exists."

Third-party product listings (indicative of past enforcement)

The patent number appears in OnSpec/xSil product-sheet "covered by" lists alongside 5,809,336, 5,784,584, etc. (e.g., https://www.2020.siliconapps.com/wp-content/uploads/2011/04/xSil-258B-Product-Sheet-Rev1_6wm.pdf), indicating it was asserted as part of the portfolio that funded the 2005–2010 litigation wave.

Explicit uncertainty list

1. Claim text of 6,598,148 is unknown to me. The independent-claim breakdown above is inferred from the abstract, not verified. Flag any downstream use accordingly.
2. Assignee of record is ambiguous — Google Patents shows two current assignees; the 2009 assignment to "Moore, Charles H., TTE, UTD 03/21/2006 The Equinox Trust" and the 2005 termination of the Knobbe security interest suggest a contested chain.
3. No 2026 CAFC/PTAB activity located — absence of evidence, not confirmed absence.
4. Legal status labels are Google Patents' automated annotations, not a legal conclusion.

If you can supply the granted-claims PDF text (or allow a direct fetch of the patentimages PDF), I'll produce the verified element-by-element independent-claim breakdown.

I'll search patent-litigation sources for cases involving US 6,598,148 specifically.

Let me dig into specific case numbers and the TPL enforcement campaign.

Let me pull the dedicated patent-litigation databases for this specific patent and the later cases.

Bottom line

Yes — US 6,598,148 has a substantial documented litigation history, but essentially all of it is historic (2003–2010), and I found no case, appeal, or PTAB proceeding involving this patent after 2014. The patent is part of the "Moore Microprocessor Patent" (MMP) portfolio and was asserted alongside US 5,809,336 and US 5,784,584 by Patriot Scientific and later by Technology Properties Ltd. (TPL).

Two caveats before the table:

• Source quality is uneven. The most reliable hits are the Stanford NPE Litigation Database patent page for 6598148, RPX Insight docket 2:05-cv-00494, and the USITC publication (Pub. 4847), which reproduces the 5:08-cv-877-PSG and 5:08-cv-882-JF caption data. Where a case comes only from a Google Patents auto-generated family list, I say so.
• I am excluding look-alike patents. Search results repeatedly surfaced unrelated patents with a "'148" shorthand — US 6,758,148 (Schoeller Arca pallets), US 12,090,148 (Allergan, ANDA litigation), and US 6,066,584 (CeraMedic ceramics). None of those is this patent. Everything below is US 6,598,148 specifically, unless flagged.

Litigation involving US 6,598,148

Related non-infringement litigation, for completeness:

Case narratives

The 2003 Patriot wave (Case 1). Patriot announced suits in December 2003 against Sony, Fujitsu, Toshiba, NEC and Matsushita over the '336 ('1998) and '148 ('2003) patents (heise, https://www.heise.de/news/Patent-Streitigkeiten-um-Intel-Prozessoren-93149.html; https://www.heise.de/news/US-Entwicklerfirma-weitet-Ansprueche-um-Prozessor-Patent-aus-97603.html). Patriot's own December 20, 2005 press release describes these as "pending but dormant in the Oakland court for nearly two years" and confirms they were dismissed so TPL could refile in Texas (semiiphub mirror: https://semiiphub.com/news/patriot-scientific-lawsuits-filed-major-electronics-equipment-manufacturers). This is the one case family I could not attach a case number to.

The Texas case (Case 2) — the only merits rulings. Captioned Technology Properties Limited, Inc. v. Fujitsu Limited et al., 2:05-cv-00494, E.D. Tex., Judge T. John Ward (RPX Insight: https://insight.rpxcorp.com/litigation/3069-technology-properties-limitied-v-fujitsu; Stanford NPE: https://npe.law.stanford.edu/patent/6598148). Filed 10/24/2005; closed 12/20/2007. The asserted patents were 5,784,584, 5,809,336 and 6,598,148 (ARM/EE Times: https://www.design-reuse.com/news/202512445-arm-drawn-into-lawsuit-with-processor-technology-licensor/).

Defendants' counterclaims included an inequitable conduct theory directed at the prosecution of application 09/124,623 — the application that issued as 6,598,148 — naming attorney Drew Hamilton (E.D. Tex. answer text reproduced at https://www.ariva.de/forum/patriot-scientific-der-highflyer-2006-[261359](/patent/261359)?page=76).

Outcome: ARM (intervening defendant, Sept. 2006) won; TPL/Patriot admitted ARM's cores did not infringe the '584 unless reversed, and acknowledged no infringement of the '336 and '148. The Federal Circuit summarily affirmed on May 9, 2008 (Wiley Rein, https://www.wiley.law/pressrelease-335). Per that release, this was the first party-and-party win in the whole MMP campaign — previously "cases involving the three patents asserted by TPL and Patriot have always been settled out of court."

The Oakland DJ actions (Case 3). Five DJ suits by roughly 20 Japanese manufacturers against Patriot, TPL and Charles Moore, filed December 2005, seeking declarations that the three patents were not infringed and invalid (Patriot press release, Dec. 20, 2005). I have the Toshiba caption independently reproduced in a court filing as Case No. C-05-04838 MHP (Judge Marilyn Hall Patel, N.D. Cal.) — the caption reads Patriot Scientific Corporation, Charles H. Moore, and Technology Properties Ltd., complaint filed December 7, 2005 (https://insight.rpxcorp.com/litigation_documents/[2457820](/patent/2457820)).

⚠️ Jurisdiction conflict to flag: the previously generated section of this analysis listed 3:05-cv-04838 and 3:05-cv-04847 as E.D. Cal., following the Unified Patents auto-generated labels. The primary document (the complaint itself) and the USITC publication both place these Oakland cases in the Northern District of California. Oakland is in N.D. Cal., so I treat the N.D. Cal. attribution as correct and the E.D. Cal. label as a data-entry artifact in the aggregated feed. Same issue for 5:08-cv-00877 (previously labeled E.D. Cal.); USITC Pub. 4847 cites it as N.D. Cal.

The 2008–2010 wave (Cases 4–7). HTC Corp. v. Technology Properties Ltd., 5:08-cv-00882-JF (N.D. Cal., Judge Fogel) and 5:08-cv-00877-PSG (N.D. Cal.) generated the claim-construction record cited in USITC Pub. 4847 (https://www.usitc.gov/publications/337/pub_4847.pdf), which lists as admitted exhibits the February 26, 2008 amendment from the file history of US 6,598,148 and the October 29, 2010 Joint Claim Construction Statement. The Commission publication is where the narrow construction of "entire oscillator"/"entire ring oscillator" was applied. Cases 6 and 7 (S.D.N.Y. 1:09-cv-04083; the 2010 816 cases) come only from Google Patents' auto-generated family-litigation list and I could not verify parties or subject matter; they may concern the '336 or '584 rather than the '148.

What I could not confirm

1. Case numbers for the 2003 Patriot suits (Case 1) and for the Intel DJ action — not located.
2. Case 8, 14-1317 (CAFC, 2014). This appears only in the Google Patents family list. Given the '148 expired 2009-08-03, I would expect this to be a different MMP-family patent (e.g., a '336 reexamination appeal). Do not attribute 14-1317 to the '148 without a docket check. The RPX entry for 2:05-cv-00494 does show "DC CAFC" routing, so a 2008-era appeal from that case exists — I just don't have its number.
3. Outcome postures for Cases 3–7. Almost certainly dismissals/settlements following the Texas non-infringement result and the broad MMP licensing campaign (Intel and AMD license in 2005; ~150 targets noticed in 2006), but I have no docket-level proof of disposition for the individual DJ and 2008–2010 cases.
4. ITC investigation number. I can cite USITC Pub. 4847 as the document containing the '148 claim-construction exhibits, but I did not verify which 337-TA number it corresponds to.

Overall status

• No pending litigation involving 6,598,148 is known. The most recent verified activity is the 2010 joint claim construction statement; the most recent merits ruling is the 2008 CAFC summary affirmance in 2:05-cv-00494.
• The patent expired 2009-08-03 (20 years from the 1989-08-03 priority date), so it can no longer be asserted. Google Patents shows "Expired – Fee Related" — treat that label as an automated annotation, not a legal conclusion.
• No 2026 CAFC docket, appeal, or PTAB proceeding involving US 6,598,148 was found. That is absence of evidence, not proof of absence.

Primary sources for re-verification: Stanford NPE Litigation Database, https://npe.law.stanford.edu/patent/6598148 • RPX Insight, https://insight.rpxcorp.com/litigation/3069-technology-properties-limitied-v-fujitsu • USITC Pub. 4847, https://www.usitc.gov/publications/337/pub_4847.pdf • Unified Patents litigation portal, https://portal.unifiedpatents.com/litigation/caselist (query by patent number 6598148).

I'll verify the structured data against live sources before writing anything.

Let me check whether any AIA proceeding or reexam exists for the MMP family, and confirm no confusion with the LED-driver patent 7,843,148 that surfaced.

I could not complete a third round of verification (tool-step limit reached), but the two search rounds I ran plus the structured ODP block are consistent. Here is the analysis.

Proceedings overview

Zero AIA trial proceedings have ever been filed against US 6,598,148 B1. The breakdown is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials — not because every petition was rejected, but because no petition was ever filed. The canonical structured block ("The USPTO ODP API returns no AIA trial proceedings for this patent") is the controlling source, and my web searches surfaced no IPR, PGR, or CBM naming this patent. The defensive bottom line is not "the patent is hardened" and not "claim 1 is dead" — it is "this patent was never stress-tested at the PTAB, so there is no estoppel to inherit and no FWD to cite, but it also expired long ago, which moots most live-assertion risk."

Two collision warnings before anything else, because both are easy to mistake for this patent:

• US 7,843,148 (LED driver) is in active IPR — IPR2024-00073 — and its briefs and hearing transcripts (e.g., https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1554764](/patent/1554764)/…, https://ptacts.uspto.gov/ptacts/public-informations/petitions/1554764/download-documents?artifactId=…, and the related papers at https://ptacts.uspto.gov/ptacts/public-informations/petitions/1554764/download-documents?artifactId=sSvojU8hRHFIG5otHFyCdCKAsyJKhjExjgycdxSHw8R8CoGyJKsV970) use the shorthand "'148 patent" throughout. Those references have nothing to do with Moore's microprocessor patent.
• IPR2014-00424 is also referred to as the "'148 Decision" in one brief I retrieved (Nu Mark LLC matter, cross-cited in US 10,349,682's reference list) — that is a different patent again.

Any claim-level "FWD" or "unpatentable" language you may have seen attached to "'148" in a PTAB document almost certainly belongs to one of those two.

No proceedings to report — how I confirmed it

• Structured data (authoritative for this task): no AIA trial proceedings on file from the USPTO ODP.
• Independent search: queries for IPR/PGR/CBM petitions naming 6,598,148, and for the Moore Microprocessor Portfolio generally, returned only district court litigation, ITC activity, and ex parte reexaminations of sibling patents — no AIA trial on the '148 patent. I did not locate any proceeding number to populate the per-proceeding template, and per your instruction I will not invent one.
• Statutory reality check (why this is credible rather than a data gap):
  • PGR was never available. The '148 patent's claims have an effective filing date of 1989-08-03 (the application was filed 1998-07-29 as a divisional of 08/484,918). Post-grant review applies only to patents with claims having an effective filing date on or after 2013-03-16.
  • CBM was never available. The CBM program was confined to "covered business method" patents (financial products/services) and sunset on 2020-09-16. A stack-based RISC microprocessor architecture was never a candidate.
  • IPR was the only AIA vehicle — and IPR filings are overwhelmingly litigation-driven. By the time the AIA took effect on 2012-09-16, the '148 patent had already been dropped from the N.D. Cal. case (stipulated dismissal 2013-07-17) and the family's litigation energy had shifted to the '336 and '890 patents and the ITC.

The closest thing to a PTAB record — and it is not this patent

Alliacense (the TPL Group licensing arm) publicly summarized the family's ex parte reexamination campaign in a ~2009 release, "MMP Portfolio™ Prevails After Multiple Reexams" (https://www.businesswirechina.com/en/news/2341.html):

• US 5,809,336 — reexaminations filed by NEC, Toshiba, and the Public Patent Foundation, plus a further HTC attempt; USPTO indicated a Reexamination Certificate would issue in August–September 2009, claims confirmed.
• US 5,784,584 — reexamination certificate issued July 2009 over reexams filed by NEC and Toshiba.
• EP '730 — German Patent Court confirmed validity in January 2009 over a nullity action by Deutsche Telekom.

The '148 patent is conspicuously absent from that list. It was named in Alliacense's licensing and litigation messaging (the 2005–2006 releases describe it as "US '148: On-Chip Oscillator and Embedded Memory," https://www.design-reuse.com/news/202509842-alliacense-launches-major-licensing-program-for-fundamental-microprocessor-patents/ and https://semiiphub.com/pulse/news/hewlett-packard-becomes-system-manufacturer-license-moore-microprocessor-patent-portfolio), and it was asserted in litigation — but it never attracted the reexam or IPR fire that the '336 and '584 did. Note also that ex parte reexaminations are not AIA trials, carry no § 315(e) estoppel, and are not PTAB proceedings; I flag them here only because they are the nearest-in-kind validity record in the family.

Adjacent adversarial record on the '148 patent (not PTAB)

Since there is no FWD to analyze, the useful defensive intelligence is in the courts:

Strategic summary

Which claims are canceled vs. sustained vs. untested. None are canceled; none have been adjudicated at the PTAB. All claims of the '148 patent are untested before the Board. My earlier verification pass flagged that the granted claim text of US 6,598,148 was not retrievable from the sources available — the Google Patents scrape you supplied contains the abstract, description and definitions but no "Claims" section, and the claim text I found in the record belongs to the parent, US 5,809,336 (claims 1, 6, 10, 11, 13, 16). I repeat that flag here because it is load-bearing: I cannot give you a claim-by-claim survivorship list for a patent whose claim numbers I cannot confirm. Pull the granted claims from USPTO PatentCenter or https://patentimages.storage.googleapis.com/81/ef/1b/0f2d82cda03b5a/US6598148.pdf before quoting any claim number for this patent.

Estoppel landscape. There is essentially none, which cuts both ways. Because no petitioner has ever obtained a Final Written Decision on the '148 patent, § 315(e)(2) estoppel is not triggered against anyone — no prior petitioner, and no privy, is barred from raising art in district court on this patent. Conversely, a defendant today has no FWD to lean on and no free pass from a prior institution denial either: a denial of institution triggers no estoppel, and the Board's 2012–2015 institutional denials on other patents in this space (e.g., the many Denied entries in the large-defendant VirnetX/Nu Mark/Microsoft-Sony IPR clusters that my searches surfaced) are irrelevant here. Practically, the entire prior-art field remains open to a defendant, subject only to the ordinary § 282 burdens and whatever the ongoing litigation record has already put in play. The one genuine statutory ceiling is that only IPR was ever available; a pre-AIA patent cannot be PGR'd, and CBM has sunset.

Pattern signals. No single petitioner filed multiple IPRs on this patent — because none filed one at all. The patent owner (Patriot/TPL/Alliacense) historically preferred licensing over PTAB appeals: Alliacense reported 60+ licensees by 2009 and early licenses to Intel and AMD (https://www.eetimes.com/Intel-AMD-HP-pay-Patriot-24-million-for-licenses/), and the family's appellate history runs through district court appeals, not Board appeals. CAFC 14-1317 (2014) is the most recent Federal Circuit entry on the family in the Google Patents record; it is a district court/ITC-side appeal, not an appeal of any PTAB decision, and I could not verify its disposition from search — do not characterize it without pulling the opinion. There is no defensive aggregator (no Unified Patents, RPX, or similar) in this patent's chain; the family's opponents were the accused OEMs themselves (HTC, Acer, Asus, Barco, NEC, Toshiba, Fujitsu, Matsushita, HTC at the ITC).

Two record contradictions worth resolving before you act on a demand letter. (i) Google Patents reports the '148 patent as "Expired – Fee Related" with an anticipated expiration of 2009-08-03, i.e., 20 years from the 1989-08-03 priority date. That is internally odd: a fee-related lapse would ordinarily have occurred at a maintenance-fee window (3.5/7.5/11.5 years after the 2003-07-22 grant), and the label "Expired – Lifetime"/end-of-term would be expected for a term expiry. Alliacense's own 2005–2009 releases said the portfolio was "protected through the year 2015," and under the URAA transitional rule the '148 patent — the child of an application (08/484,918) filed 1995-06-07, one day before the June 8, 1995 changeover — would have taken the greater of 17 years from grant (2020-07-22) or 20 years from earliest filing (2009-08-03). That arithmetic is inconsistent with the Google Patents label and with Alliacense's 2015 claim. The real expiration dates should be confirmed in the USPTO PatentCenter's "Patent Term Adjustments/Expiration" data and the maintenance-fee history before you advise anyone that this patent is dead. (ii) My earlier summary noted ambiguous dual current-assignee entries (the Equinox Trust and Patriot Scientific); no assignment or ownership change in the PTAB record exists to resolve it, because there is no PTAB record.

Recommended next steps

1. State plainly that there is no PTAB relief to inherit. With zero AIA trials, there is no FWD to quote, no institution decision to cite, and no § 315(e)(2) estoppel. If an adversary or a vendor tells you the '148 patent "survived IPRs," that statement is false — what survived were ex parte reexaminations of other patents ('336 and '584). Consumer- and investor-facing sources have repeatedly blurred the family together (e.g., the forum discussion at https://investorshub.advfn.com/boards/profile.aspx?user=[345119](/patent/345119)&page=22 that runs the '336/'148 ring-oscillator arguments together), so insist on the patent number and the proceeding number in writing.
2. Confirm the term before anything else. Pull the PatentCenter maintenance-fee and term data for 6,598,148. If the term ran to 2020-07-22, a 2026 demand letter is purely a stale back-damages theory; if the patent truly expired in 2009, the entire assertion is facially time-barred for post-expiration conduct. Either way, the 6-year damages lookback of § 286 is the operative fight — see the '148 patent's statutory bars in 35 U.S.C. §§ 286 and 315(b).
3. If you expect to be sued, move fast on the § 315(b) clock. IPR is the only AIA vehicle for this patent. A petition must be filed within one year of service of a complaint alleging infringement; there is no second bite. Because no prior petitioner exists, you face no discretionary-denial General Plastic stacking problem and no § 325(d) "same or substantially the same art" problem from earlier Board proceedings — an unusually clean slate. Note the current landscape, though: the Acting Director's 2025-03-26 Interim Processes memorandum adds a discretionary-denial briefing track for patent owners that weighs "settled expectations" and the length of time the claims have been in force (see the Director's decision in IPR2025-00408, Dabico Airport Solutions Inc. v. AXA Power ApS, and the Kangxi Communication petition materials at https://fedcircuitblog.com/wp-content/uploads/2026/03/26-115_Kangxi-Communication_Petition-Only.pdf). A 1989-priority patent would be an extreme "settled expectations" case for discretionary denial — an argument that cuts for denial and against a petitioner. This is a further reason IPR on this patent was never attractive, and is worth flagging if opposing counsel claims a 2026 IPR is imminent.
4. Preserve the non-PTAB invalidity theories. The strongest historical attacks on this specific patent have been (a) the inequitable conduct / revival-declaration theory regarding application 09/124,623 (abandoned 2002-05-02; declaration filed 2002-04-29), and (b) § 102/§ 103 over the conventional-microprocessor art. Because no IPR FWD exists, neither is precluded by estoppel — but if you plan to rely on the inequitable conduct record, pull the actual EDTX/N.D. Cal. pleadings and the 09/124,623 file history from PatentCenter, since the only copy I could retrieve was a forum-reproduced filing of uncertain completeness.
5. Do not confuse this patent with US 7,843,148 (LED driver). That patent is in an active IPR, IPR2024-00073, with a live hearing record. If your file contains a research memo citing a "6,598,148 IPR," assume it is a number-collision error until the proceeding number is produced.

Explicit uncertainties in this memo. (1) No PTAB proceeding for 6,598,148 was found — absence of evidence based on the authoritative ODP block plus two search rounds, not a hand audit of every PTAB docket. (2) Granted claim text of 6,598,148 remains unverified (see the earlier section). (3) The expiration date is contradictory on the record and unresolved. (4) The 2012 N.D. Cal. Markman constructions for '148 terms, and the disposition of CAFC 14-1317, were not verified. (5) The inequitable-conduct allegations are sourced from a non-authoritative reproduction.

I'll research the assignment chain for US 6,598,148 across the sources available to me.

Good — I now have the claim text (useful context). Let me dig into the assignment and ownership records.

Let me try to pin down the specific recorded assignments and reel/frame numbers.

I have enough to reconstruct the chain, but I must be explicit about a material evidence gap: I could not directly query the USPTO Assignment Center (it is an interactive, session-based search that my tooling cannot drive), and none of the search results surfaced reel/frame numbers or correspondent-of-record data for this patent. What follows is therefore rebuilt from two cross-reference sources that mirror the same USPTO records — Google Patents' "Legal Events"/reassignment table (which is populated from USPTO assignment data) and contemporaneous press/SEC reporting on the ownership dispute. Every reel/frame I cannot verify is flagged rather than filled in. I have not fabricated any reel/frame numbers.

Inventors

Unusual pattern — yes, and it is the defining feature of this family:

• The two named inventors later became adverse parties over inventorship of the very same claim set. Patriot stated on 2004-11-23 that discovery "strongly suggests that Fish was the sole inventor of the '336 patent," and that Fish's interests had flowed Fish → Fish Family Trust → Nanotronics Corporation → Patriot, giving Patriot "100% of Fish's interests." Patriot simultaneously asserted that Moore and his colleagues were "selling and marketing interests in the '336 Patent with inaccurate claims of ownership and inventorship." (EE Times, 2004-11-23, https://www.eetimes.com/patriot-says-it-appears-to-be-owner-of-disputed-patent/; PRNewswire via design-reuse, https://www.design-reuse.com/news/202508488-patriot-scientific-says-it-appears-to-be-the-sole-owner-of-significant-patent-claims/.)
• This is not the "all inventors depart within 12 months" pattern. It is the inverse and more severe pattern: inventorship itself is contested, which is what produced the entangled dual-ownership chain below.

Original assignee

Patriot Scientific Corporation (San Diego / Carlsbad, CA; OTC: PTSC) — the "Original Assignee" field on the issued patent and the "Applicant" on Espacenet (PATRIOT SCIENT CORP).

• Product? Patriot's own self-description around the dispute was "an intellectual property company, developing and marketing innovative and proprietary semiconductor technologies into the … handheld wireless and smart card markets." It characterized the patent as covering "fundamental microprocessor technology." Whether Patriot commercially shipped a chip embodying this divisional's claims (on-substrate DRAM + ring-oscillator clock) is not evidenced in the record. The enforcement posture from 2004 onward was licensing/assertion, not manufacturing. Mark as unclear on product-embodying.
• Primary line of business at the time of the events: patent licensing/enforcement. By 2011 Patriot was publicly described as "the co-owner of the Moore Microprocessor Patent™ Portfolio licensing partnership with The TPL Group" (Patriot 8-K Ex-99.1, 2011-08-03, https://getfilings.com/sec-filings/[110805](/patent/110805)/PATRIOT-SCIENTIFIC-CORP_8-K/ptsc_8k-ex9901.htm).
• Current status: Operating, but as an IP-holding/licensing shell-like entity, not a chip company. It remains an SEC-reporting OTC issuer; no bankruptcy of Patriot appears in the record. Its joint-venture partner, however, did fail: "On March 20, 2013, TPL filed a petition under Chapter 11 … On March 5, 2018, TPL's Motion for Entry of Final Decree Closing Chapter 11 was granted."

Assignment timeline

Reliability note: Reel/frame and correspondent values are not available from the sources I could reach. The USPTO Assignment Center (https://assignmentcenter.uspto.gov/, also indexed at https://assignment.uspto.gov/patent/index.html) is the correct place to pull them; you should verify each row there. Rows below are sourced as marked. DNV = "did not verify" (no reel/frame obtainable).

• 1989-08-03 — Parent application 07/389,334 filed (now US 5,982,231). Priority anchor for the whole family. Source: patent specification, first paragraph.
• 1995-06-07 — Divisional 08/484,918 filed (now US 5,809,336). Source: same.
• 1998-07-29 / recorded 1998-07-29 — Reel DNV — Application filed by Patriot Scientific Corp; "Priority to US09/124,623." This is the application that issued as 6,598,148.
  • Conveyance: (application/priority data, not a recorded assignment)
  • Assignee: Patriot Scientific Corp.
  • Correspondent: unknown
  • Context: internal continuation of the MMP family; original-prosecution record.
• ~1990s–2000s (exact dates unknown) — Fish interest chain: Fish → Fish Family Trust → Nanotronics Corporation → Patriot Scientific. No dates or reel/frame available.
  • Conveyance: assignment (inter vivos and corporate transfers)
  • Assignor: Russell H. Fish, III / Fish Family Trust / Nanotronics Corporation
  • Assignee: successive; terminal assignee Patriot Scientific
  • Correspondent: unknown
  • Context: consolidation of the co-inventor's interest into the operating/IP assignee — the step that later anchored Patriot's claim to 100% of Fish's share. Source: EE Times, 2004-11-23.
• 2003-02-14 / recorded 2003-02-14 — Reel DNV — SECURITY INTEREST
  • Assignor: Patriot Scientific Corporation
  • Assignee/secured party: Knobbe, Martens, Olson & Bear, LLP
  • Correspondent: DNV (note: the secured party is itself a law firm — see signal 3 below)
  • Context: securitization — a law firm taking a security interest in Patriot's patents (typically for accrued legal fees).
• 2003-07-22 — Patent granted / Published US 6,598,148 B1 (not an assignment).
• 2004-11-11 to 2004-11-23 — Ownership dispute litigated. Patriot sues Technology Properties Ltd. (TPL), Daniel Leckrone and Charles Moore over ownership; Patriot rejects a $7.5M offer brokered by Relational Advisors LLC for patents US 5,809,336, 6,598,148, 5,440,749, 5,604,915, 5,530,890, 5,784,584 and 5,659,703. Not an assignment, but it is the causal event for the ownership structure on the patent.
  • Sources: EE Times 2004-11-11 & 2004-11-13; design-reuse PRNewswire 2004-11-11/15; PRNewswire 2004-11-23.
• 2005-08-08 / recorded 2005-08-08 — Reel DNV — TERMINATION OF SECURITY INTEREST
  • Assignor: Knobbe, Marten, Olson & Bear, LLP
  • Assignee: PATRIOT SCIENTIFIC CORPORATION
  • Correspondent: DNV
  • Context: release — the 2003 securitization unwound; Patriot's title cleared.
• 2006-03-21 — The Equinox Trust executed (UTD date carried in the recorded assignee name; not necessarily a recording date).
• 2009-03-24 / recorded 2009-03-24 — Reel DNV — ASSIGNMENT OF ASSIGNORS INTEREST (see document for details)
  • Assignor: MOORE, CHARLES H.
  • Assignee: MOORE, CHARLES H., TTE, UTD 03/21/2006, THE EQUINOX TRUST ("TTE" = trustee; "UTD" = under trust dated 2006-03-21)
  • Correspondent: DNV
  • Context: estate-planning / title-holding transfer of Moore's personal interest into his own revocable trust — not a transfer to an unrelated asserter. This is why Google Patents lists two current assignees (Equinox Trust and Patriot Scientific): the patent is co-owned.
• 2013-03-20 — TPL files Chapter 11 (partner of co-owner; not the assignee of record on this patent). Final decree 2018-03-05.
• 2019-09-06 — PDS (Phoenix Digital Solutions LLC, the Patriot/TPL MMP licensing JV) files a cert petition to the Supreme Court over MMP litigation; reporting describes PDS as "pursuing a litigation strategy." Not an assignment.

If the Assignment Center contains entries I could not reach (e.g., an Alliacense, TPL, or Phoenix Digital Solutions LLC recording against this patent), those would need to be added — I did not confirm any such recording on this patent. The MMP licensing is documented as running through the PDS joint venture and TPL/Alliacense as licensors/enforcers, not as recorded assignments of 6,598,148.

Timeline diagram

timeline
    title Ownership of US 6598148
    1989 : Priority application 07389334 filed
    1995 : Divisional 08484918 filed
    1998 : Divisional 09124623 filed by Patriot
    2003 : Security interest to Knobbe Martens
         : Patent issued 22 July
    2004 : Patriot sues TPL and Moore over ownership
    2005 : Security interest terminated
    2006 : Moore Equinox Trust executed
    2009 : Patent assigned to Equinox Trust
    2013 : TPL files Chapter 11
    2018 : TPL bankruptcy case closed

NPE / troll-pattern signals

1. Shell-entity transfer — unclear. No recording on this patent shows a move into a licensing-only LLC. The only quasi-shell vehicles in the picture — Phoenix Digital Solutions LLC (Patriot/TPL licensing JV), Alliacense, LLC (TPL's licensing arm) and TPL — are documented as licensors/enforcers, not as recorded assignees of 6,598,148. Do not treat this as present without a reel/frame showing a conveyance to them.

2. Known asserter in the chain — present (strong). The co-owner Patriot Scientific is a self-described "intellectual property company" that derived revenue "in a large part, from the Moore Microprocessor Patent™ Portfolio licensing partnership with The TPL Group," and the family was asserted against Intel, Sony, Fujitsu, Toshiba, NEC, Matsushita (2004) and, via PDS/TPL, against Amazon, Garmin, HTC, Huawei, Kyocera, LG, Nintendo, Samsung, ZTE, Acer, Barnes & Noble, Novatel in the 2012 ITC action. TPL's Alliacense and the PDS JV are pure licensing/enforcement entities. This is an enforcement-driven estate, not a manufacturing one. Sources: EE Times 2004-11-11; Patriot 8-K Ex-99.1 (2011); ITC/Complaint reporting quoted on publicly archived boards.

3. Repeat correspondent across the chain — unknown / cannot assess. I obtained no correspondent-of-record names on any link. One partial observation: the 2003-02-14 secured party is the law firm Knobbe, Martens, Olson & Bear, LLP, i.e., a patent law firm appears as a party in the chain — but that is a secured-lender role, not a correspondent-of-record determination, and the same firm does substantial operating-company work. Per your rule, a single appearance is not a finding. Pull the correspondent field from the Assignment Center for every recording before making this call.

4. Cascading transfers (<24 months through chained LLCs) — not present on the recorded chain. The recorded events on this patent span 2003→2009 with no rapid LLC-to-LLC hop.

5. Pre-litigation transfer (≤6 months before first suit) — not present. The first enforcement wave predates the 2009 Moore→trust recording; the Equinox recording is after the 2004–2008 litigation, so it cannot have been arranged to enable that assertion.

6. Bankruptcy fire-sale — present as a family event, but not as an assignment of this patent. TPL filed Chapter 11 on 2013-03-20 (final decree 2018-03-05). But TPL is not the assignee of record on 6,598,148, and I found no evidence this patent was sold in the TPL estate. Mark the patent-specific fire-sale as unclear.

7. Privateering — plausible, unclear. The structure is a licensing joint venture (Patriot + TPL → PDS; TPL/Alliacense conducting the licensing) rather than a classic operating-company-to-NPE privateer transfer. Patriot itself is the IP holder, so the "operating company cloaking enforcement behind an NPE" description does not fit cleanly.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN; title rests with Moore's trust and Patriot.

Verdict

NPE — moderate confidence.

The single strong signal is a known asserter in the chain: co-owner Patriot Scientific is a licensing-only IP company (per its own 2011 8-K describing revenue "in a large part" from the MMP licensing partnership), enforcing through TPL / Alliacense / Phoenix Digital Solutions LLC against large numbers of product companies — the Google Patents litigation entries for this family (Cal. N.D. 3:05-cv-04837/04844/04845 and 5:08-cv-00882, Cal. E.D. 3:05-cv-04838/04847 and 5:08-cv-00877, N.Y.S.D. 1:09-cv-04083, Cal. 5:10-cv-00816, and CAFC 14-1317) corroborate a sustained assertion campaign. I stop short of "high confidence" because the recorded assignment chain on this patent is thin and I could not verify a single reel/frame or correspondent — the only recorded conveyances are a 2003-02-14 security interest to Knobbe Martens (terminated 2005-08-08) and a 2009-03-24 estate-planning transfer of Moore's interest into his own Equinox Trust, neither of which is an NPE acquisition. Signals 1, 3, 4 and 5 are unverified or absent, so the rubric's "2+ strong signals" threshold for high confidence is not met on the evidence I can actually cite.

Verify here: https://assignmentcenter.uspto.gov/ (search by patent number 6598148) and the legacy index https://assignment.uspto.gov/patent/index.html — specifically pull reel/frame + correspondent for the 2003-02-14 security interest, the 2005-08-08 termination, the 2009-03-24 Moore→Equinox Trust assignment, and any recording by TPL, Alliacense, or Phoenix Digital Solutions LLC.

Contradiction flagged against the prior section

The earlier summary's inferred claim 1 (from the abstract) is contradicted by the claim text now retrieved (Espacenet, https://worldwide.espacenet.com/publicationDetails/claims?CC=US&NR=[6598148B1](/patent/6598148B1)&KC=B1&FT=D&date=20030722). Actual claim 1 adds two limitations absent from the abstract: "a plurality of column latches coupled to the processing unit and the memory, wherein, during a read operation, a row of bits are read from the memory and stored in the column latch," and the memory "using a majority of a total area of said single substrate." So the abstract does not track claim 1 cleanly, and the prior section's inferred independent claim should be treated as superseded. (Other independents: claims 4, 8, and 11.)

I'll search for the specific patent's citation data from authoritative sources.

I found the actual claim text — which contradicts the earlier unverified inference. Let me now search specifically for the patent's own front-page cited references.

I have partial citation data. Let me get the complete list of cited references and cross-check against the Google Patents page for US6598148 itself.

Prior-Art Analysis — US 6,598,148 B1

0. Scope, sources, and an important verification note

Assignment caveat first: you asked me to search the USPTO database. I could not pull the examiner's front-page "References Cited" directly from USPTO PatentCenter/Public PAIR full text in this session. What I could retrieve is:

• The granted claim text (via Espacenet's claims view for US6598148B1 — this is new and material; see §1).
• The cited-references list for the family (via the Google Patents page for the PCT counterpart WO1991002311A1, "High performance, low cost microprocessor," which is the international filing of the same 1989 specification). That page lists 23 patent citations.

Because those 23 citations come from the WO/PCT family page rather than the US front page, they are a close proxy but not a guarantee of US 6,598,148's exact front-page list. I retrieved 17 of the 23 before tool limits stopped further queries. Treat the list below as complete and verified for the 17 shown, incomplete for the remaining 6.

Date note: the task header says April 26, 2026; my operating date is 2026-09-30. This does not change anything — 6,598,148 is expired (anticipated expiration 2009-08-03, per the record) — but flagging it for consistency.

Applicable law: pre-AIA (priority 1989-08-03; application filed 1998-07-29). Prior art is judged under pre-AIA 35 U.S.C. § 102(a)/(b)/(e)/(g), not AIA § 102.

1. ⚠️ CONTRADICTION WITH THE PRIOR SECTION — read this before using the prior summary

The previously-generated section stated I did not have the claim text and inferred claim 1 as merely "processing unit + on-chip memory larger than the processing unit + variable-frequency clock." That inference was wrong, and the actual claims are materially broader and different. I have now retrieved the granted claims. The independent claims are:

• Claim 1 — processing unit; memory coupled to it; "a plurality of column latches coupled to the processing unit and the memory, wherein, during a read operation, a row of bits are read from the memory and stored in the column latch"; a variable speed system clock; all on a single substrate; the memory using "a greater area of said single substrate than said processing unit" and "a majority of a total area of said single substrate."
• Claim 4 — processing unit; memory occupying greater area and a majority of the substrate; and "a ring oscillator having a variable output frequency, wherein the ring oscillator provides a system clock to the processing unit."
• Claim 8 — processing unit "having one or more interface ports for interprocessor communication"; memory majority of substrate; ring oscillator as system clock.
• Claim 11 — a computational system: first processing unit + first memory (majority of substrate) + ring-oscillator clock on a first substrate, plus a second processing unit configured for interprocessor communication.
• Dependent claims 2–3, 5–7, 9–10, 12–13 add DRAM/SRAM, read/write support, a column latch in an interface port for serial communication (cl. 9), and memory controller means for performing DMA through the interface ports (cl. 10).

Consequence: any prior-art mapping must be judged against the "plurality of column latches" limitation (cl. 1), the "majority of total substrate area" limitation (cl. 1, 4, 8, 11), and the interprocessor-communication port limitations (cl. 8–13). The earlier inference omitted all three. Please discard the earlier inferred claim, not this one.

(Note: Espacenet rendered the claim text with a stray leading "442." artifact before claim 1 — a formatting artifact, not a claim number.)

2. The cited references (17 of 23 verified), with filing/publication dates

All filing dates below precede the 1989-08-03 critical date, so each qualifies as pre-AIA prior art at least under § 102(e) or § 102(b).

Not retrieved (6 of the 23): the WO page listing was truncated at ref. 17. I cannot name the remaining six. Given the pattern (Motorola-type microprocessor art of the mid-1980s), I would not assume any of them discloses the on-die variable-speed ring-oscillator clock.

Non-patent citations: I did not retrieve any for 6,598,148. The parent '336 record is known to carry NPL citations, but I have not verified the '148 front page.

3. Most relevant references mapped to specific claims

I assess these on technical correspondence to claimed elements, not on an examiner's § 102/§ 103 categorization (which I do not have).

Strongest candidates

US 4,665,495 A (TI, "Single-chip DRAM controller and CRT controller," filed 1984-07-23, pub. 1987-05-12) — the single most relevant cited reference. It discloses a DRAM controller integrated with a CRT controller on one chip, including serial/video shift-register data paths fed from row-latched memory data. This maps directly onto the "column latch," "row of bits read from the memory and stored in the column latch," and serial-shift-register elements of claim 1 and claim 9, and is relevant to the memory-controller/DMA element of claim 10. It does not disclose a ring-oscillator system clock or a processing unit sharing a substrate with a majority-area memory.

US 3,969,706 A (Mostek, DRAM integrated circuit, filed 1974-10-08, pub. 1976-07-13) — direct § 102 relevance to claim 2 (memory is DRAM) and to the general "memory on a common substrate" element. Not a microprocessor claim.

US 4,354,225 A (Nanodata, "Intelligent main store for data processing systems," filed 1979-10-11, pub. 1982-10-12) — a memory subsystem with on-board processing/control logic. Relevant to the "processing unit + memory" combination of claim 1 and to the "memory controller means … for performing direct memory access" language of claim 10. It is a store-centric system, not a single-substrate CPU-plus-majority-memory device, so it does not read on the "majority of total area" or ring-oscillator limitations.

US 4,945,479 A (Unisys, "Tightly coupled scientific processing system," filed 1985-07-31, pub. 1990-07-31) — a multiprocessor/tightly-coupled system. This is the most on-point citation for the interprocessor-communication limitations of claims 8, 11, 12, and 13 ("second processing unit … configured for interprocessor communication"; "interface port for establishing … communication between an internal register of said first processing unit and [a] second processing unit"). It does not disclose the on-die ring-oscillator clock.

US 4,586,127 A (Burroughs, multiple control stores for a pipelined microcontroller, filed 1982-11-03, pub. 1986-04-29) and US 4,807,115 A (Cornell, instruction issuing for multiple functional units, filed 1983-10-07, pub. 1989-02-21) — relevant background to the processing-unit and instruction-supply elements of claims 1/4/8, and to the spec's discussion of instruction fetching and pipelines. Neither touches the clock or column-latch limitations.

Weaker / background references

• US 4,200,927 A (IBM, multi-instruction-stream branch) and US 4,777,587 A (AMD, single-cycle branch) bear on instruction-fetch/branch behavior described in the specification, but no claim of 6,598,148 recites branching, so they do not map to any claim.
• US 4,390,961 A / US 4,484,300 A (Honeywell decimal multiply) map to the spec's multiply/polynomial discussion, which likewise is not claimed.
• US 4,562,537 A (TI, high-speed processor), US 4,819,158 A (Fujitsu, interruptible bus cycle), US 4,709,329 A (Data General, I/O device controller), US 4,173,789 A (Shibaura, multiplication control), US 4,240,137 A (Shibaura, structured-block execution), US 3,911,405 A (Sperry Rand, edit unit), US 4,488,227 A (Honeywell, program-counter stacking) — general-purpose background; each is at best a § 103 secondary reference and none individually reaches the independent claims.

4. § 102 anticipation assessment (explicit)

No single one of the 17 retrieved references appears to anticipate any of independent claims 1, 4, 8, or 11 under § 102. The two limitations that block single-reference anticipation are:

1. The on-substrate variable-frequency clock — claim 4/8/11 require "a ring oscillator having a variable output frequency … provid[ing] a system clock to the processing unit," and claim 1 requires a "variable speed system clock" on the same substrate. None of the 17 citations discloses a ring-oscillator-derived, process/voltage/temperature-tracking system clock on the same die as the CPU. This is the true point of novelty and, historically, it is the element the family's litigation turned on (the "entire ring oscillator" term construed narrowly in E.D. Tex. and the ITC).
2. "Memory … a majority of a total area of said single substrate" (claims 1, 4, 8, 11) — a die-area-ratio limitation that none of these references recites.

Where § 102 could plausibly be argued, it is only against dependent claims and only if a reference is read very broadly:

• US 3,969,706 → claim 2 / claim 5 (memory is DRAM).
• US 4,665,495 → claim 9 (column latch facilitating serial communication) and possibly claim 1's column-latch element — but not the full claim 1.
• US 4,945,479 → potentially claims 8 / 11 / 12 / 13 interprocessor-communication elements — but not the clock or area limitations in those claims.

Everything else is properly a § 103 candidate (secondary reference combined with a primary teaching of on-chip memory or of a clock), not § 102.

5. What I could not verify — do not treat as complete

1. 6 of the 23 cited references are unnamed (WO listing truncated at US 4,777,587). Any conclusion that "no cited reference anticipates" is bounded by this gap.
2. The citation list is from the PCT/WO1991002311A1 family page, not confirmed against US 6,598,148's own front page. The two lists are usually identical in a family like this, but I have not proven it.
3. No non-patent citations retrieved for 6,598,148.
4. No examiner § 102/§ 103 categorization retrieved — the "which reference anticipates which claim" mapping in § 3–4 is my technical assessment, and I have labeled it as such.
5. I did not find the examiner's reasons for allowance, which would show why the claims issued over these references (most likely the ring-oscillator-clock and die-area-ratio limitations).

To close the gap, the authoritative sources are USPTO PatentCenter for application 09/124,623 (front-page references and the examiner's citations), or the granted-patent PDF at patentimages.storage.googleapis.com/81/ef/1b/0f2d82cda03b5a/US6598148.pdf. If you can supply that PDF text or permit a direct fetch, I can complete the 23-reference table and verify each against the granted claims above.

I'll first try to recover the claim text and the prior-art references associated with this patent, since the supplied page's claim section is missing and its "Prior Art" area only gave me keywords and the 1989-08-03 prior-art date.

I recovered the actual granted claim text (Espacenet). Now let me verify the key prior-art references' identities and dates before building the §103 combinations.

Obviousness Analysis — US 6,598,148 B1 under 35 U.S.C. § 103

0. Correction and scope note (flagging a contradiction with the earlier section)

The earlier "Patent summary" section stated that the claim text of 6,598,148 was unobtainable and that the independent-claim breakdown was "inferred." That was accurate as of that search but it is now superseded. I retrieved the granted claims from Espacenet (https://worldwide.espacenet.com/publicationDetails/claims?CC=US&NR=[6598148B1](/patent/6598148B1)&KC=B1&FT=D). The claims are reproduced in §1 below and everything below is built on the actual claim language, not the abstract.

Second scope note, on your instruction to "use the results from the Prior Art section of this page": the supplied Google Patents page's Prior Art module contains only prior-art keywords (memory, processing unit, microprocessor, instruction, stack) and a prior-art date of 1989-08-03. It contains no citation list. The references below are therefore reconstructed from (a) the '336 front-page reference list (same family, same specification, https://patentimages.storage.googleapis.com/74/03/08/f8ef57046b7813/[US5809336](/patent/US5809336).pdf) and (b) the ex parte reexamination request filed against the '336 patent (http://www.pubpat.org/assets/files/patriotscientific/PUBPATPatriotScientific336Request.pdf). Items (b) are advocacy documents — the requester's characterizations of the references are flagged as such.

1. The claims actually at issue (verbatim, Espacenet)

The independent claims are 1, 4, 8 and 11. (Espacenet prints leading paragraph numbers "442.", "445." etc.; those are page artifacts, not claim numbers.)

1. A microprocessor integrated circuit comprising: a program-controlled processing unit operative in accordance with a sequence of program instructions; a memory coupled to said processing unit and capable of storing information provided by said processing unit; a plurality of column latches coupled to the processing unit and the memory, wherein, during a read operation, a row of bits are read from the memory and stored in the column latch; and a variable speed system clock having an output coupled to said processing unit; said processing unit, said variable speed system clock, said plurality of column latches, and said memory fabricated on a single substrate, said memory using a greater area of said single substrate than said processing unit, said memory further using a majority of a total area of said single substrate.

4. …a processing unit …; a memory … occupying a larger area of said integrated circuit substrate than said processing unit … a majority of a total area of said single substrate; and a ring oscillator having a variable output frequency, wherein the ring oscillator provides a system clock to the processing unit, the ring oscillator disposed on said integrated circuit substrate.

8. …a processing unit having one or more interface ports for interprocessor communication …; a memory … greater area … majority of total area; and a ring oscillator having a variable output frequency … provides a system clock … disposed on said substrate.

11. A microprocessor computational system comprising: a first processing unit …, a first memory …, a ring oscillator …; and a second processing unit coupled to said first processing unit and configured for interprocessor communication with said first processing unit.

Dependent claims add only: DRAM vs. SRAM (2, 3, 5, 6), read/write capability (7), "a first of said interface ports includes a column latch … facilitating serial communication" (9), "memory controller means … for performing direct memory access data transfer through said one or more interface ports" (10), a second substrate bearing the second CPU/memory (12), and interprocessor communication "between an internal register of said first processing unit and second processing unit" (13).

Two claim-drafting observations that drive the whole analysis:

1. Claim 1 does not recite a ring oscillator at all. It recites a "variable speed system clock." Claims 4, 8 and 11 recite a "ring oscillator," but none of the '148 claims recite "entire" — i.e., the word that the Federal Circuit held carries the Magar/Sheets prosecution disclaimers (fixed-frequency crystal; control-signal dependence). See Technology Properties Ltd. v. Huawei Techs. Co., 14-1317 (Fed. Cir. 2018) and USITC Pub. 4847 at 78 (https://www.usitc.gov/publications/337/pub_4847.pdf). Those disclaimers were made in the '336 prosecution, in a different application; importing them into the '148 claims is contestable, and claim 1's plain language contains no hook for them at all. That materially widens claim 1 relative to '336 claim 1 and makes obviousness easier to establish.
2. The two "area" limitations are pure die-area ratios (memory > CPU; memory > 50% of die). No structural novelty follows from a ratio; these are the inherent geometry of putting a commodity memory array next to a small logic core.

I could not confirm whether claim 1 was amended post-grant (e.g., by a reexamination certificate) into its present "variable speed system clock" form; if it was narrowed from a "ring oscillator" recitation, the analysis below is unaffected in substance because the primary reference (Ledzius) teaches a ring oscillator.

2. Legal framework and the person of ordinary skill

• Pre-AIA § 103(a) controls. Earliest effective filing date 1989-08-03 (application 07/389,334). Art published/patented before 1988-08-03 is § 102(b) art; art between 1988-08-03 and the filing/section-102(e) dates is § 102(a)/102(e) art. All references below except where noted predate 1988-08-03.
• POSITA: a B.S. in EE/CS with roughly 3–5 years of microprocessor and MOS IC design experience, familiar with DRAM architecture (row/column decode, sense amplifiers), with logic synthesis, on-chip oscillators, and DMA/multiprocessor interfaces. KSR Int'l v. Teleflex, 550 U.S. 398 (2007) (combination of known elements; the problem may be drawn from the patent's own background; predictable results = obvious); In re Keller; MPEP § 2143.
• Critical threshold point that a validity challenger must litigate first: whether claims 1 and 8–13 ("column latches," "interface ports for interprocessor communication," "memory controller means") are supported by the 1989 application under § 112 ¶ 1. If they are, only pre-1989 art counts. If they are not, the effective date slides to 1995-06-07 or 1998-07-29, and the entire 1990s embedded-DRAM/SoC/on-chip-PLL body of art becomes available — at which point these claims are close to indefensible. That priority exposure is the single largest § 103 risk in the file and is not addressed in the earlier sections.

3. The prior-art universe

Background art I know of but did NOT verify from this page (flagged per your rules): the INMOS transputer T414/T800 family (mid-1980s) — a single-chip CPU with on-chip RAM and four on-chip serial links purpose-built for interprocessor communication, sold as building blocks for processor arrays. This is the obvious primary reference for claims 8, 9, 11, 13, and the '148 spec itself concedes the point: "The INMOS transputer attempted a similar strategy, but at much lower speed and without the performance benefits inherent in the microprocessor 310 column latch architecture."

Applicant's own admissions usable as prior art (the specification describes the pre-existing art in the present tense): DRAM row/column architecture ("The DRAMs 311 access random bits in a memory array by first selecting a row of 1024 bits, storing them into a column latch, and then selecting one of the bits…"); DMA controllers "which may be located on the microprocessor integrated circuit, or provided separately"; external crystal clocks for I/O; multiprocessor systems "typically … built up from numerous board level or box level computers"; and the admitted cost/area/power problems with off-chip memory.

4. Element-by-element mapping of the independent claims

5. The combinations, and why a POSITA would have made them

Combination I — Ledzius + Magar + [single-chip microcomputer: Mostek/Hitachi/Boney] + [DRAM column-latch art: Pelgrom / ordinary DRAM] → claims 1, 4, 5, 6, 7

1. Magar puts the CPU and its clock-generation circuitry on one substrate and outputs multiple clock phases — establishing that co-fabricating clock generation with the CPU was conventional.
2. Ledzius replaces Magar's crystal-driven generator with a free-running on-chip ring oscillator whose frequency automatically tracks the die's process/temperature (and voltage) variation, used as the system clock, at maximum safe speed. That is the '148's entire clock concept, including the stated benefit ("CPU 70 will always execute at the maximum frequency possible, but never too fast").
3. A 1981–1985 single-chip microcomputer (Mostek 3870/F8; Hitachi HD6805W1; Boney '268) supplies CPU + writable on-chip memory on one die, with the memory array dominating the die area — meeting both "area" limitations and supplying the § 103 "same field, same problem" linkage.
4. Ordinary DRAM architecture supplies the column-latch limitation: RAS-driven row read into the column latch is how every DRAM works, and the '148 specification concedes this ("Row and column design is inherent in memory architecture").

Motivations (each independently sufficient, and all drawn from the record):

• Cost. The '148 background states the problem the inventors set out to solve: high-performance CPUs require expensive static RAM, so DRAM is usable "only in a hierarchical memory arrangement, with the static memories acting as a buffer." Removing that hierarchy is the stated objective → motivation to integrate a large memory with the CPU.
• Speed/bandwidth. The application's own premise is that "the bottleneck in most computer systems is the memory bus," and the admitted DRAM access-time fact (85 nsec part → ~25 nsec page-mode) motivates the row-latch/column-latch reuse.
• Power. The application admits that DRAM I/O drivers "dissipate most of their power" and that the CPU spends a third of its power on I/O pads — integrating the memory eliminates those pads. KSR: this is a recognized design incentive, not hindsight.
• Clock. Ledzius supplies the express motivation to clock the logic from an on-chip oscillator whose rate tracks the same parameters that limit the logic — i.e., the very "self-compensating, maximum speed" rationale.
• Predictability. Every element is a conventional circuit operated in its ordinary way; the only "new" content is the ratio of memory area to logic area and the co-fabrication, both inherent in the combination. No unexpected result is asserted for these claims.

On the § 112 squeeze worth noting for a challenger: if TP argues the "memory" must be a large writable array (per the spec's DRAM/SRAM examples and the "storing information provided by the processing unit" language), it narrows toward the integrated-DRAM art; if TP argues for a broad reading (ROM/EPROM plus RAM under the generic term "a memory"), then the single-chip microcomputer references of the early 1980s anticipate/obviously render the memory element. Either reading yields an invalidity route; the patentee cannot simultaneously read "memory" broadly enough to keep '148 claim 1 distinct from the MCU art and narrowly enough to escape the integrated-DRAM art.

Combination II — Ledzius + transputer-type serial-link processor + Guttag/Thaden → claims 8, 9, 10, 13

• The transputer family (mid-1980s) discloses exactly claims 8/11/13's architecture: a single-chip CPU, on-chip RAM, and dedicated on-chip interprocessor communication ports (serial links), expressly sold for constructing processor arrays; the '148 specification acknowledges this strand of prior art ("The INMOS transputer attempted a similar strategy…"). Flag: I could not verify the transputer details from this page; treat as a lead to be documented before filing anything.
• Guttag independently discloses an on-chip interface module exchanging coupling control signals, addresses and data with the CPU and an external bus — the claim-8 "interface ports," and (per the reexam request) Guttag's interface is clocked by a fixed external clock, which is precisely the '148's decoupling of the variable-speed core from the fixed-speed interface.
• Claim 9's "column latch facilitates serial communication": the '148 specification itself concedes that a DRAM column latch is a 1024-bit register and that the same latch can be repurposed as a shift register for serial output (video/DMA). Repurposing a DRAM column latch as a serial shift register is therefore not merely obvious — it is admitted to be the ordinary use of that hardware.
• Claim 10's "memory controller means … DMA through the ports": the '148's own background admits DMA controllers "may be located on the microprocessor integrated circuit, or provided separately," and Thaden discloses on-chip memory-controller integration on a single chip.
• Motivation: distributed processing to break the Von Neumann bottleneck (the application's own stated objective) plus the admitted problem that multiprocessor systems lose up to 50% of bus speed "just getting through the interfaces" — a POSITA would put the link shift registers on the same die as the memory to avoid that loss.

Combination III — multiprocessor claim set (11, 12)

Two coupled processors each with on-chip memory and an on-chip ring-oscillator clock. Once Combination I is accepted for a single chip and Combination II for the ports, claim 11's "second processing unit … configured for interprocessor communication" is the ordinary duplication of a known element to obtain the expected benefit (In re Harza; KSR: "a court must ask whether the improvement is more than the predictable use of prior art elements according to their established functions"). Claim 12 adds only that the second CPU has its own substrate/memory — a textbook obvious duplication of parts.

A single-reference (anticipation-adjacent) variant worth pleading in the alternative

The '336 reexam request asserted that Hitachi alone (with Boney for the instruction-set features) discloses "a ring oscillator, microprocessor and input/output interface on the same IC." If the HD6805W1 data book's on-chip clock source is a ring oscillator and its on-chip memory field dominates the die, then claim 4 of the '148 could be challenged under § 102(b) rather than § 103 — a materially stronger posture. This must be verified against the data book pages (Exhibit 11 of the reexam request) before reliance; I have only the requester's characterization.

6. Where the obviousness case is weakest (be honest about this)

1. Ledzius's disclosure is characterized to me only through an advocacy document. Before this analysis is used, obtain US 4,691,124 and confirm: (a) the oscillator is a ring oscillator; (b) it is used as the system clock for the CPU, not merely as a bias/timing element; (c) frequency varies automatically with voltage as well as process/temperature. The '148's "variable speed system clock" (claim 1) is a low bar, but "ring oscillator having a variable output frequency" (claims 4/8/11) requires (a).
2. The "majority of a total area of said single substrate" limitation is the best non-obviousness argument available to a patent owner, on the theory that 1989 single-chip microcomputers had memory-dominant dies only for read-only memory, and that user-writable-RAM-dominant dies did not exist as a commercial product until embedded DRAM (early 1990s). Counter: the claim says "a memory," not "RAM," and the specification's own § 112 counterpart (memory larger than the CPU) is nowhere tied to writability; and the applicant's own admission that the dual CPU totals "fewer than 50,000 transistors" makes the area ratio a mathematical consequence of integration.
3. Prosecution disclaimer risk cuts against the challenger on claims 4/8/11 if a court imports the '336 Magar/Sheets disclaimers (no control signal; frequency not fixed by any external crystal) into the '148 claims. Mitigations: (i) the '148 claims contain no "entire" term; (ii) the disclaimer was made in a different application (the '336) and the Federal Circuit's holding was expressly tied to the "entire oscillator" phrase; (iii) claim 1 contains no "ring oscillator" and no "entire" — so no disclaimer hook exists for claim 1 at all, and Combination I satisfies claim 1 with Ledzius or even with a Sheets-type on-die VCO.
4. Secondary considerations. The record shows only that PTSC began a "patent compliance" campaign in mid-2003 and that its Ignite1 chip is said to embody the patent (https://semiiphub.com/news/patriot-scientific-contends-patents-mpu-design). For commercial success or industry praise to rebut obviousness there must be a nexus to the claimed features (memory-area ratio; on-chip ring oscillator) rather than to the product as a whole; nothing on the record supplies that nexus. Conversely, the 2004 ownership/inventorship dispute (Patriot Scientific v. Technology Properties Ltd.) and the inequitable-conduct allegations in the NEC pleadings are relevant to enforceability, not to § 103, but they weaken the patent owner's litigation posture generally.
5. Unverified leads, not to be relied on: an internet-forum post discussing a "Talbot" reference in the '148 prosecution, and the suggestion that claim 1's "variable speed system clock" recitation reflects a post-grant amendment. Both are unverified and should be resolved from the official file wrapper (USPTO PatentCenter for application 09/124,623) before any of this is used in a paper.

7. Bottom line

Under pre-AIA § 103(a) and KSR, all thirteen claims of US 6,598,148 are vulnerable, with the strongest attacks being:

• Claims 1, 4, 5, 6, 7 — Ledzius (on-chip variable-speed ring-oscillator system clock) in view of Magar (on-die clock generation for a microprocessor) further in view of a 1980s single-chip microcomputer (Mostek 3870/F8; Hitachi HD6805W1; Boney '268) and the admitted ordinary DRAM row-to-column-latch architecture. Motivation: cost/performance/power of eliminating the off-chip memory interface — the very problem the '148 specification recites in its Background.
• Claims 8, 9, 10, 13 — the same combination plus an on-chip serial interprocessor link per the transputer (to be documented) and Guttag/Thaden for on-chip interface and separate interface clocking.
• Claims 11, 12 — obvious duplication of the Combination I device into a two-processor system.
• Alternative posture: if the Hitachi HD6805W1 data book confirms an on-chip ring-oscillator clock with a memory-dominant die, claim 4 is directly attacked under § 102(b).

The two decisive variables are (i) whether Ledzius's oscillator is used as the CPU system clock, and (ii) whether the "memory … majority of total area" limitation is read to require user-writable RAM — the latter being simultaneously the patent owner's best defense and, because the specification's own area numbers make the ratio a consequence of integration, a defense that a POSITA would likely be found to have reached predictably.