US 6774033

I'll verify the patent details and check for any 2026 CAFC docket activity.

Let me check for any 2026 Federal Circuit docket activity specific to this patent.

Let me check specifically for any 2026 docket activity.

US Patent 6,774,033 — Verification Summary

I searched for this specific number (6,774,033 / US6774033B1) and cross-checked against the patent text, PTAB records, and Federal Circuit records. Here is what the authoritative sources show.

Bibliographic data

Assignment chain: Cypress Semiconductor → Sansocca Alandro A.B., LLC (2010) → Callahan Cellular L.L.C. (2015, merger) → Intellectual Ventures Assets 156 LLC (2020) → Innovative Silicon Solutions, LLC (2020, nunc pro tunc) → HD Silicon Solutions LLC (2021, change of name).

Abstract (verbatim)

"In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop."

Plain-language overview of the independent claims

The patent has two independent claims: claim 1 and claim 15. (Claims 2–14 depend from claim 1; claims 16–17 depend from claim 15.)

Claim 1 — A method of forming a local interconnect layer in an integrated circuit, comprising two steps: (1) deposit a first film containing titanium nitride over an oxide layer; and (2) deposit a second film containing tungsten over the first film. Together the two films form the metal stack of the local interconnect layer. Notably, claim 1 recites no thickness ranges, no etch steps, and no deposition technique — those are all in dependent claims.

Claim 15 — A method of forming a local interconnect layer, comprising: (1) sputter a first titanium-nitride-containing film over an oxide; and (2) sputter a second tungsten-containing film over the first film in the same tool used to sputter the first film (i.e., in-situ deposition). Again, the two films form the metal stack of the local interconnect layer.

Independent-claim scope is therefore quite broad: claim 1 covers essentially any TiN-over-oxide + W-over-TiN local-interconnect stack regardless of process specifics, and claim 15 adds the in-situ/same-tool sputtering limitation.

Related dependent-claim features (for context)

Claim 2 (in-situ deposition), claim 3 (sputtering), claim 4 (≤ ~600 Å total stack), claims 5–7 (≤300 Å TiN, ≤300 Å W, ~300 Å each), claim 8 (sheet resistance ≤ ~10 Ω/sq.), claim 9 (etch W stopping on TiN, etch TiN stopping on oxide), claim 11 (fluorine-based etchant for W), claim 12 (chlorine-based etchant for TiN), claim 13 (probing W to electrically test), claim 14 (resist over W), claim 16 (≤600 Å stack), claim 17 (probing).

Litigation / PTAB history (relevant to your docket question)

• IPR2021-00752 (Microchip Technology Inc. v. HD Silicon Solutions LLC), filed 2021-04-23, instituted 2021-11-09, Final Written Decision 2022-11-07: claims 1–7 and 9–17 unpatentable as obvious over U.S. Patent 5,847,463 (Trivedi); claim 8 survived.
• IPR2022-00105 (Microchip Technology Inc. v. HD Silicon Solutions LLC), filed 2021-11-04 — not instituted (procedural).
• Federal Circuit Appeal No. 23-1397 (HD Silicon Solutions LLC v. Microchip Technology Inc.), decision 2025-02-06: the court held the Board's construction of "comprising tungsten" was erroneous (it should mean elemental tungsten), but the error was harmless; the obviousness affirmance was upheld. Judges Lourie, Stoll, Cunningham. An inter partes review certificate referencing IPR2021-00752 was issued 2025-06-24.
• District court matters appearing in the record include HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20-cv-01092 (W.D. Tex., transferred to N.D. Cal., 3:21-cv-08295) and a W.D. Tex. case No. 1:25-cv-01320.

Regarding "CAFC 2026 dockets" — explicit uncertainty

I found no 2026 Federal Circuit docket activity associated with US 6,774,033. The only Federal Circuit appeal for this patent that my searches surfaced is No. 23-1397, decided 2025-02-06 (and the associated appeal cited in some records as 23-1943/23-1397). The patent itself was recorded as expired – lifetime as of 2022-11-04, and the Federal Circuit affirmance of invalidity became final in 2025. I did not locate any 2026 CAFC docket entry, briefing, or oral-argument item tied to this number.

Caveat: my searches hit a step limit before I could exhaustively query PACER/CM-ECF for the Federal Circuit's 2026 term. I cannot affirmatively rule out a newly filed 2026 matter, but nothing in the USPTO patent record, PTAB records, or the Federal Circuit sources I retrieved indicates any 2026 appellate activity for 6,774,033. I would flag this as a genuine gap rather than a confirmed negative.

Sources consulted

• Google Patents record for US6774033B1 (full text, claims, legal events, litigation links)
• PTAB Final Written Decision, IPR2021-00752 (Paper, 2023-01-06)
• Federal Circuit opinion, No. 23-1397 (2025-02-06), cafc.uscourts.gov
• Unified Patents / ipverse / Docket Navigator-style case summaries for IPR2021-00752 and IPR2022-00105

I'll research litigation involving US patent 6774033.

Let me gather more detail on the specific cases.

Let me confirm a couple of final details on the NXP case and the appeal outcome.

Litigation Involving U.S. Patent No. 6,774,033

Preliminary note on scope and sources: U.S. Patent 6,774,033 ("Metal stack for local interconnect layer"), filed November 4, 2002, granted August 10, 2004, expired November 4, 2022, is currently held by HD Silicon Solutions LLC (formerly Innovative Silicon Solutions, LLC; originally Cypress Semiconductor Corp.). Per the Google Patents / Unified Patents records for this specific patent number, two (2) U.S. district court cases are recorded as involving the '033 patent. I have not auto-corrected any identifiers below.

The following is based on the Google Patents page for US6774033 (which lists both district court cases as "litigation" for this patent), Unified Patents' docket entry for 6774033, the N.D. Cal. (formerly W.D. Tex.) docket reproduced in PTAB exhibits, Dockets.Justia.com, UniCourt, and the Federal Circuit records.

District Court Litigation

Case 1 — HD Silicon Solutions LLC v. Microchip Technology Inc.

Cases 2 — HD Silicon Solutions LLC v. NXP Semiconductors N.V. et al.

Caveat: The W.D. Tex. docket listing for 1:25-cv-01320 shows seven exhibits but the public docket summary I retrieved does not itemize patent numbers. The Google Patents page for US6774033 specifically lists case 1:25-cv-01320 as litigation involving this patent, and the Stanford NPE litigation dataset lists the case under NXP Semiconductors N.V. as alleged infringer. I could not independently confirm from the docket excerpt that the '033 patent is among the seven asserted there, so treat "the '033 patent is asserted against NXP" as supported but not docket-verified at the claim level.

Related Administrative Proceedings (PTAB / USPTO) — Not District Court Litigation, but Directly on the '033 Patent

These are listed because they were the operative validity challenges on the '033 patent and drove the outcome of the Microchip district court case:

• IPR2021-00752 — Microchip Technology Inc. v. HD Silicon Solutions LLC. Filed April 23, 2021; instituted November 9, 2021; Final Written Decision November 7, 2022 holding all but one of the 17 challenged claims unpatentable as obvious over U.S. Patent No. 5,652,185 (Trivedi) and secondary art. Patent Owner notice of appeal January 6, 2023.
• IPR2022-00105 — Microchip Technology Inc. v. HD Silicon Solutions LLC. Filed November 4, 2021; institution denied May 9, 2022.
• (Federal Circuit) 23-1397 — HD Silicon Solutions LLC v. Microchip Technology Inc.. Opinion dated February 6, 2025 (Lourie, Stoll, Cunningham, JJ.). The Court affirmed the Board's obviousness determination and the affirmed invalidity holding, even though it found the Board had erroneously construed the claim term "comprising tungsten" (which the Court held means elemental tungsten, not tungsten compounds). The erroneous construction was harmless because Trivedi discloses layers of both a tungsten compound and elemental tungsten.
• IPR Certificate — an inter partes review certificate was issued June 24, 2025 (Trial No. IPR2021-00752), cancelling the invalidated claims.
• Ex parte reexamination 90/016,219 — requested by NXP USA Inc. (listed on the patent's validity-challenge record; EPR).
• (Federal Circuit) 23-1943 — HD Silicon Solutions LLC v. Microchip Technology Inc., nonprecedential judgment affirming (Rule 36) the Board in IPR2021-01567 (a different patent, U.S. 7,158,742, not the '033 patent); noted here only to avoid confusion with the '033 appeal.

Summary

There are two district court actions known to involve U.S. Patent 6,774,033:

1. HD Silicon Solutions LLC v. Microchip Technology Inc. — 6:20-cv-01092 (W.D. Tex.), transferred to 3:21-cv-08295-SK (N.D. Cal.); filed November 30, 2020; dismissed with prejudice, closed April 14, 2025.
2. HD Silicon Solutions LLC v. NXP Semiconductors N.V. et al. — 1:25-cv-01320 (W.D. Tex.); filed August 19, 2025; open/pending.

The patent's validity claims were largely invalidated in IPR2021-00752 (affirmed by the Federal Circuit on February 6, 2025), and the patent expired November 4, 2022.

Sources: Google Patents US6774033B1 (https://patents.google.com/patent/US6774033/en); Unified Patents patent page (https://portal.unifiedpatents.com/patents/patent/6774033); N.D. Cal. docket 3:21-cv-08295-SK (reproduced at ptacts.uspto.gov); Dockets.Justia.com docket 1:2025cv01320 (https://dockets.justia.com/docket/texas/txwdce/1:2025cv01320/1172860072); Justia CAFC opinion 23-1397 (https://law.justia.com/cases/federal/appellate-courts/cafc/23-1397/); Cassetext/GreyB PTAB records for IPR2021-00752 and IPR2022-00105.

Note: I did not have live access to PACER for these dockets in this session; docket details above are drawn from the sources cited, which reproduce PACER/PTAB filings. The NXP case outcome is "open" as of the most recent available docket data (August 2025) and should be re-verified against PACER for any 2025–2026 developments.

I'll research the PTAB proceedings identified in the patent record and verify outcomes via web search.

PTAB Proceedings — US 6,774,033 B1 ("Metal Stack for Local Interconnect Layer")

Data-integrity flag before anything else. The "PTAB proceedings on file" block states that the USPTO ODP API returns no AIA trial proceedings for this patent. That is inconsistent with the patent's own Google Patents record, which carries two PTAB litigation entries (IPR2021-00752 and IPR2022-00105), a Rule 42.8 mandatory-notice cross-reference, and a K1 inter partes review certificate issued 2025-06-24. Web verification confirms both proceedings are real. I treat the ODP block as a stale/incomplete ingest and report the two confirmed proceedings below, per your instruction to flag anything search surfaces. I do not treat the ODP silence as evidence of no PTAB activity.

Proceedings overview

Two AIA trials on file, both against the same patent, same petitioner (Microchip Technology Inc.), both now terminated: 1 proceeding ended with claims invalidated (FWD + Federal Circuit affirmance + IPR certificate), and 1 proceeding ended in a denial of institution (procedural). Zero active proceedings, zero settlements, zero claims affirmed on the merits apart from claim 8 alone.

Bottom line for a defendant today: The patent is expired (status: "Expired – Lifetime," expiration 2022-11-04) and claims 1–7 and 9–17 have been canceled on final judgment that was affirmed by the Federal Circuit and memorialized in an IPR certificate on 2025-06-24. If a demand letter or complaint cites claim 1, any dependent claim other than claim 8, or claim 15, it is citing canceled claims — that theory is dead on arrival. The only thing left standing is claim 8 (the ≤10 Ω/sq sheet-resistance dependent claim), which the Board declined to hold unpatentable, and which depends from the now-canceled claim 1.

IPR2021-00752 — Microchip Technology Inc. v. HD Silicon Solutions LLC

• Type: Inter Partes Review
• Filed: 2021-04-23
• Status: Final Written Decision (claim-level outcome: unpatentable). Plain-English gloss: challenger won; patent narrowed to a single dependent claim.
• Judge panel: Frances L. Ippolito (opinion author), Robert L. Kinder, Arthur M. Peslak — Administrative Patent Judges. (Nathan A. Engels appears on related-petition panels in the same family.)
• Parties / counsel: Petitioner Microchip Technology Inc. (lead: Sanjeet Dutta; pro hac vice: Brett M. Schuman, Rachel M. Walsh — Goodwin Procter). Patent Owner HD Silicon Solutions LLC, formerly Innovative Silicon Solutions LLC (lead: Justin J. Oliver; back-up: Sarah S. Brooks, Seth Boeshore — Venable LLP).
• Petition grounds: All 17 claims challenged under 35 U.S.C. § 103. Principal art was U.S. Patent 5,847,463 (Trivedi) — a local interconnect structure with "tungsten silicide and titanium nitride layers, or … a tungsten layer covered on opposite sides thereof with titanium nitride" — alone and in combinations with secondary references including U.S. Patent 6,534,401 (Joo), a 1997 IEDM Technical Digest publication (Yang), and U.S. Patent 6,103,623 (Lien). Claim 8 (the ≤10 Ω/sq limitation) was mapped to a Trivedi + Yang combination, with Yang's reported ~2.06 Ω/sq PVD-TiN/CVD-W stack supplying the numeric teaching. (Note: secondary sources number the grounds differently — one summary calls Trivedi+Yang "Ground 2," the oral-hearing transcript calls the claim-8 combination "Ground 3" and places claim 7 in a Trivedi+Joo+Yang ground. I report the substance rather than the disputed ground numbers.)
• Institution decision: Instituted on all challenged claims on 2021-11-09 (all 17 claims of the '033 patent). The petition had been filed ~11 months into the N.D. Cal. litigation (HDSS v. Microchip, No. 3:21-cv-08295-SK, N.D. Cal.).
• Final Written Decision: Issued 2022-11-07. Claims 1–7 and 9–17 held unpatentable as obvious; claim 8 was not shown to be unpatentable. (Corroborated by the Federal Circuit's opinion and multiple secondary reports; see links below.) The FWD issued three days after the patent's 2022-11-04 expiration date.
• Key merits issue — claim construction of "comprising tungsten." The Board construed the term broadly as "any form of tungsten, including both elemental tungsten and tungsten compounds" and found the claims obvious over Trivedi (which discloses a tungsten silicide, i.e., a compound) and its secondaries. The Patent Owner argued at the oral hearing that "there is no dispute that Trivedi describes a tungsten silicide layer, not a tungsten layer," and pressed that tungsten silicide is not a metal stack.
• Settlement / termination: No settlement. Case terminated 2022-11-07 by the FWD.
• Appeal: Yes — appealed to the Federal Circuit. Docket No. 23-1397, HD Silicon Solutions LLC v. Microchip Technology Inc., decided 2025-02-06, precedential. Panel: Lourie, Stoll, Cunningham (Judge Lourie authoring).
  • Holding 1 — claim construction: reversed/erroneous. "A claim to 'tungsten,' on its own, therefore refers to elemental tungsten." The court held the Board improperly weighted extrinsic evidence against explicit intrinsic evidence (claim 1 recites "comprising titanium nitride" — a compound — versus "comprising tungsten" with no second element; the spec "exclusively refers to tungsten as a singular component, i.e., as an element"; dependent claim 12's "chlorine-based etchant" shows the drafter used open-ended modifiers when compounds were intended).
  • Holding 2 — obviousness: affirmed. The error was harmless: "Trivedi itself teaches that either tungsten silicide or elemental tungsten may be used to form the [second] local interconnect layer," and either disclosure renders claim 1 obvious. HDSS's substantial-evidence attack on the motivation to combine for the dependent claims was rejected — the Board gave a "thorough and well-reasoned explanation"; "HDSS presents no argument in response"; "at bottom, [HDSS] asks us to reweigh the evidence, which we decline to do."
  • Disposition: affirmed.
  • Opinion: https://www.cafc.uscourts.gov/opinions-orders/23-1397.OPINION.2-6-2025_2464314.pdf — also at https://www.courtlistener.com/opinion/[10330126](/patent/10330126)/hd-silicon-solutions-llc-v-microchip-technology-inc/
• Certification: Inter partes review certificate (kind code K1) issued 2025-06-24 for IPR2021-00752 (per the patent's legal-events record). This is the instrument that gives the cancelation effect at the Office.
• PTAB record: https://portal.unifiedpatents.com/ptab/case/IPR2021-00752 (Unified's free docket aggregator — not evidence that Unified Patents filed the challenge).

Defensive value: Claims 1–7 and 9–17 are dead, and the death certificate survived Federal Circuit review in a precedential opinion. Any infringement theory built on claim 1, claim 15 (the second independent claim), or any dependent claim in those ranges is premised on canceled claims. The CAFC opinion also handed defendants a precedential claim-construction rule ("tungsten," standing alone, means elemental tungsten) that constrains how HDSS can read its own claims.

IPR2022-00105 — Microchip Technology Inc. v. HD Silicon Solutions LLC

• Type: Inter Partes Review
• Filed: 2021-11-04 (five days before the Board instituted IPR2021-00752; the '105 petition itself argues "Considerations Under 35 U.S.C. § 325(d)" and § 314(a))
• Status: Not Instituted – Procedural (structured-data verbatim as carried in the patent record); Institution Denied, institution decision 2022-05-09. Plain-English gloss: the Board declined to open a second trial on the same patent — it never reached the merits.
• Judge panel: Frances L. Ippolito, Robert L. Kinder (Jr.), Arthur M. Peslak. (These APJs sat jointly on the family-wide pro hac vice order covering both '033 proceedings and six sibling-patent IPRs.)
• Claims challenged: 1, 2, 3, 5, 8, 9, 10, 11, 13, 15, 17 — a subset of the '752 claim set, notably re-challenging claim 8, the only claim that had survived… actually, at filing the '752 FWD did not yet exist; the subset reflects a narrower, refined follow-on attack.
• Petition grounds: I could not retrieve the merits recitation or the denial rationale. The petition expressly briefed discretionary denial under § 325(d) and § 314(a), consistent with a follow-on/second-bite petition filed while IPR2021-00752 was pending on the same patent and the same art.
• Institution decision: Denied 2022-05-09. ⚠️ I do not have the Board's stated reason (likely a § 325(d) / § 314(a) or General Plastic follow-on analysis, given the petition's own framing and the identical claim/art overlap with the instituted '752). I decline to attribute a specific rationale to the panel without the paper. Verify against PTAB E2E Paper 6–8 of IPR2022-00105 before relying on it.
• Final Written Decision: None — no trial, no FWD, no claim-level holding.
• Settlement / termination: Terminated by denial of institution; no settlement.
• Appeal: None. A denial of institution is non-appealable (§ 314(d)); no Federal Circuit activity on this docket number appears.
• PTAB record: https://portal.unifiedpatents.com/ptab/case/IPR2022-00105

Defensive value: Procedurally, this is a nullity — it decided nothing and creates no estoppel independent of the '752 (Petitioner Microchip is already estopped under § 315(e)(2) from the '752 grounds anyway). Its real value is as a pattern artifact: it shows the Board would not open a second front on the '033 patent while the first was pending, and it deprives HDSS of any argument that the patent was "vindicated" by surviving a second challenge — claims 1–3, 5, 9–11, 13, 15, 17 were never adjudicated on the merits in '105; as to those claims the only merits adjudication is the '752 FWD that canceled them.

Strategic summary

Claim status across the portfolio of adjudications.

So the surviving claim set of US 6,774,033 is claim 8 only — and that is a dependent claim that depends from canceled claim 1 ("The method of claim 1 wherein the first film and the second film form a metal stack having a sheet resistance equal to or less than about 10 Ohm/sq."). Practically, any assertion of claim 8 carries claim 1's limitations with it, so the claim-construction and obviousness reasoning the Federal Circuit blessed for claim 1 remains live for claim 8. Claim 8 is narrow (a numeric sheet-resistance threshold on a two-film TiN/W stack) and, given the patent's 2022-11-04 expiration, is not a vehicle for ongoing royalties.

Estoppel landscape. Post-affirmance, § 315(e)(2) bars Microchip and its privies/RPIs from asserting in a civil action, or in an ITC proceeding, any ground the petitioner raised or reasonably could have raised in IPR2021-00752 — the full Trivedi-centered obviousness story over Joo, Yang, and Lien, plus any § 102/§ 103 theory based on patents or printed publications that a skilled searcher would have found. That estoppel does not run against a new, unrelated defendant; a fresh defendant can still petition for IPR on claim 8 using § 102/§ 103 grounds of patents and printed publications (the § 311(b) limit — no product/system art, no public-use or on-sale art in an IPR). The claim-8-specific ground actually litigated (Trivedi + Yang's 2.06 Ω/sq) failed in '752, so any new attack on claim 8 must come from different art or a materially different combination — and it must confront the same expired-patent economics: no forward-looking relief, only a § 286 six-year back-damages window ending 2022-11-04 (and, for the 2025 W.D. Tex. filing, laches/pendency arguments to be examined on the actual asserted patent — I cannot tell from the record which patent 1:25-cv-01320 asserts).

Pattern signals.

• Same petitioner, multiple bites. Microchip filed at least eight IPRs against the HD Silicon Solutions portfolio in a single wave — IPR2021-00752 ('033), IPR2021-01042 ('619), IPR2021-01089 ('299), IPR2021-01265 ('404), IPR2021-01420 ('731), IPR2021-01421 ('731), IPR2021-01567 ('002), and IPR2022-00105 ('033) — all handled by the same Goodwin Procter team with the same Venable opposition team, and all captioned under one joint pro hac vice order. This is a coordinated campaign, not a one-off. Several of the siblings did not fare as well (e.g., IPR2021-01420 was denied institution on motivation-to-combine grounds).
• Patent owner fought all the way up. HDSS appealed IPR2021-00752 to the Federal Circuit, lost on both the construction issue (won the issue, lost the case) and the substantial-evidence issue, and took it up in a precedential opinion. There is no indication of a petition for certiorari on the '033 patent (the Supreme Court docket item surfaced in search, 24-866, concerns U.S. 10,562,680 — a different patent; do not attribute it here).
• No defensive aggregator. The recurring "Unified Patents" URLs in the record are Unified's free public docket aggregators, not filings by Unified Patents. The petitioner of record in both '033 proceedings is Microchip Technology Inc., a litigating defendant — not an NPE-defense coalition.
• Procedural history of the parallel litigation: W.D. Tex. 6:20-cv-01092; N.D. Cal. 3:21-cv-08295-SK (HDSS v. Microchip); Fed. Cir. 23-1397; and a new W.D. Tex. filing, 1:25-cv-01320.

Recommended next steps

1. If you are a defendant being asserted on claims 1–7 or 9–17: stop and say so. The disposition is unambiguous — "claims 1–7 and 9–17 … unpatentable" — affirmed in HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23-1397 (Fed. Cir. Feb. 6, 2025) (precedential), https://www.cafc.uscourts.gov/opinions-orders/23-1397.OPINION.2-6-2025_2464314.pdf, and now embodied in the IPR certificate issued 2025-06-24. A complaint pleading canceled claims is vulnerable to a Rule 11/§ 285 motion and, at minimum, to a motion to dismiss for failure to state a claim. Pull the certificate from PTAB E2E and attach it.
2. If you are being asserted on claim 8, the analysis is different and narrower. Confirm from the FWD and certificate exactly what was "not shown to be unpatentable," then attack on (a) invalidity on art not before the Board — not Trivedi/Yang, which lost; (b) § 112 indefiniteness of the "about 10 Ohm/sq" recitation (the Federal Circuit's elemental tungsten construction now constrains the claim read); and (c) damages — the patent expired 2022-11-04, so there is no injunction and no post-expiration royalty; the entire exposure is a pre-expiration back-damages theory inside the § 286 window, subject to laches-type and notice defenses.
3. Do not over-read the ODP silence. The ODP "no proceedings" return is wrong here. When you brief or negotiate, cite the four independent anchors: the '752 FWD (2022-11-07), the CAFC opinion (2025-02-06), the IPR certificate (2025-06-24), and the '105 denial (2022-05-09). docket links: https://portal.unifiedpatents.com/ptab/case/IPR2021-00752 and https://portal.unifiedpatents.com/ptab/case/IPR2022-00105.
4. Open items to verify before filing anything substantive: (i) the verbatim claim-by-claim disposition table and ORDER in the IPR2021-00752 FWD (I could not pull the paper text directly — confirm whether the FWD's order lists "claims 1–7 and 9–17" exactly, and how it phrases claim 8); (ii) the institution-denial rationale in IPR2022-00105 (Paper issued 2022-05-09); (iii) the checklist of claims canceled in the K1 certificate, and whether the Office canceled claim 8 or left it confirmed; (iv) whether any reissue or reexamination was filed by HDSS after the FWD (the FWD's standard reissue/reexam notice language makes this worth a PACER/PatentCenter check); and (v) the asserted patent in W.D. Tex. 1:25-cv-01320 — if a '033-family patent is asserted, the expiration and cancelation story above is directly dispositive.

Confidence notes: the proceeding numbers, filing/institution/FWD dates, panels, petitioner/owner identities, and the claim-1–7/9–17-invalid-claim-8-survives outcome are high confidence (multiple independent sources + the CAFC opinion). The '105 denial reasoning, the certificate's exact content, and the ground-by-ground numbering inside the '752 petition are not confirmed — flagged above rather than filled in.

I'll verify the assignment records and litigation context against live sources before writing up.

Let me dig for the assignment-record correspondents and confirm corporate status details.

I hit my research-tool limit mid-verification, so a few fields (notably recorded correspondents) could not be fully confirmed. I flag those explicitly below rather than filling them in.

Sources used: the authoritative Google Patents record provided (which reproduces the USPTO legal-events reel/frame data), the PTAB Final Written Decision in IPR2021-00752, the Federal Circuit opinion in HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23-1397 (Feb. 6, 2025), district-court dockets (W.D. Tex. 6:20-cv-01092; N.D. Cal. 3:21-cv-08295; W.D. Tex. 1:25-cv-01320), and the Stanford NPE Litigation Database / RPX Insight asserter records.

Inventors

Pattern note: all four inventors executed a single assignment to Cypress dated 2002-10-31 — three days before the 2002-11-04 filing date — i.e., a standard, contemporaneous employment/invention assignment, not a post-hoc cleanup. I found no evidence of inventors departing Cypress within 12 months of filing, and the patent remained with Cypress for roughly eight years afterward (until the 2010 sale). The classic "inventors leave, then portfolio is fire-sold" precursor is not present here. (Caveat: I did not pull each inventor's employment history independently; "not present" reflects absence of any contrary record in the sources reviewed.)

Original assignee

Cypress Semiconductor Corporation, San Jose, California (legal-event owner field: "CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA").

• Business: a fab-owning semiconductor manufacturer — SRAM, USB controllers (EZ-USB), PSoC programmable systems, NOR flash. It is not a holding company.
• Product practice: US 6,774,033 is a fabrication-process patent (method of forming a tungsten-over-titanium-nitride local interconnect stack), not a product patent. It would be practiced inside Cypress's own fabs on memory/logic lines rather than embodied in a separately identifiable shipped product. Whether any specific Cypress part practiced the claimed process is not determinable from the record; I will not assert it either way.
• Current status: Cypress no longer exists as an independent company — it was acquired by Infineon Technologies AG (agreement announced June 3, 2019; transaction completed April 2020, per Infineon's public announcements). It was not in bankruptcy, and the 2010 divestiture predates the Infineon deal by a decade. Cypress was a profitable operating company at the time of the sale.

Assignment timeline

Records below are the reel/frame entries as surfaced in the patent's Google Patents legal-events record, which mirrors the USPTO Assignment Center abstract of title. Important caveat: the Assignment Center's correspondent-of-record field (attorney/firm who filed each recording) is not reproduced in the legal-events data, and I was unable to complete independent retrieval of it for every link before exhausting my search budget. Where I have a correspondent, I say so and cite it; elsewhere I say "not retrieved."

• 2002-10-31 (executed) / recorded 2002-11-04 — Reel 013460/0336

  • Conveyance: Assignment of assignors' interest
  • Assignor: Mira Ben-Tzur; Dafna Beery; Gorley L. Lau; Krishnaswamy Ramkumar
  • Assignee: Cypress Semiconductor Corporation (California)
  • Correspondent: not retrieved — the 2002 record's correspondent field is not exposed in the fetched legal-events data. Not inferred.
  • Context: original employment/invention assignment on filing (not a transfer between companies).

• 2010-07-30 (executed) / recorded 2010-11-05 — Reel 025328/0024

  • Conveyance: Assignment of assignors' interest
  • Assignor: Cypress Semiconductor Corporation
  • Assignee: SanSocca Alandro A.B., LLC (Delaware)
  • Correspondent: not retrieved (see caveat). No recurrence evidence available for this link.
  • Context: divestiture / portfolio monetization — the operating company sells a Cypress-origin patent block into a Delaware acquisition vehicle. This is the first break in operating ownership.

• 2015-08-27 (executed) / recorded 2015-12-30 — Reel 037406/0037

  • Conveyance: Merger (not a purchase)
  • Assignor: SanSocca Alandro A.B., LLC
  • Assignee: Callahan Cellular L.L.C. (Delaware)
  • Correspondent: not retrieved.
  • Context: internal reorganization — the Sansocca vehicle is merged into Callahan Cellular L.L.C., a Delaware holding entity. (Callahan Cellular is publicly associated with the Intellectual Ventures family of holding companies; the merger is consistent with that, though I did not independently verify IV's ownership of Sansocca in this session.)

• 2019-12-16 (executed) / recorded 2020-01-17 — Reel 051550/0682

  • Conveyance: Assignment of assignors' interest
  • Assignor: Callahan Cellular L.L.C.
  • Assignee: Intellectual Ventures Assets 156 LLC (Delaware)
  • Correspondent: not retrieved.
  • Context: transfer into an expressly named Intellectual Ventures asset vehicle — the assignee's own legal name identifies the acquirer; this is direct, non-inferential evidence of IV ownership.

• 2020-01-10 (executed, nunc pro tunc) / recorded 2020-03-23 — Reel 052199/0838

  • Conveyance: Nunc pro tunc assignment
  • Assignor: Intellectual Ventures Assets 156 LLC
  • Assignee: Innovative Silicon Solutions, LLC (recorded as California)
  • Correspondent: Fahim Aftab — correspondent/submitter of the recordation, e-mail fahim@hongdungroup.com, phone 949-791-9366 (per the recordation documentation filed as Ex. 1004 in IPR2021-01420, signed 03/23/2020, covering the IV Assets 156 → Innovative Silicon Solutions transfer of the Cypress-origin portfolio). The receiving-party address shown on that recordation form was 2382 Rockfield Blvd., Suite 170, Lake Forest, California 92630. Flag: this appears only once in the chain I can document — a single appearance, not a recurrence, so it does not by itself establish a repeat-player pattern. Verify the correspondent field for Reel 052199/0838 directly in the Assignment Center before relying on it.
  • Context: transfer to an assertion vehicle — a nunc pro tunc execution date backdated ~10 weeks before recording.

• 2020-01-10 (effective) / recorded 2020-03-28 — Reel 052253/0751

  • Conveyance: Corrective assignment (to correct the address of the receiving party — California → Texas)
  • Assignor: Intellectual Ventures Assets 156 LLC
  • Assignee: Innovative Silicon Solutions, LLC (re-recorded as Texas)
  • Correspondent: not retrieved; the signature/submitter on the underlying transaction documents is the same Fahim Aftab noted above.
  • Context: administrative correction only — same parties, same date of effect; no change in ownership. Notably it is the address of the NPE that needed fixing, moving the record from California to Austin, Texas.

• 2020-11-10 (effective) / recorded 2021-01-14 — Reel 054993/0795

  • Conveyance: Change of name
  • Assignor: Innovative Silicon Solutions LLC
  • Assignee: HD Silicon Solutions LLC (Texas) — the current assignee of record
  • Correspondent: not retrieved.
  • Context: change of name only — but occurring 20 days before the first infringement suit (below).

Recorded litigation events tied to this patent (not assignments, but part of the title/assertion record): IPR2021-00752 filed 2021-04-23 by Microchip Technology Inc. (Final Written Decision: claims 1–7 and 9–17 unpatentable; claim 8 survived); IPR2022-00105 filed 2021-11-04 by Microchip (indexed by Google/Unified as Not Instituted — Procedural); inter partes review certificate issued 2025-06-24 (IPRC, kind code K1). The patent's legal status is Expired – Lifetime, with anticipated expiration 2022-11-04 and maintenance fees paid at 4, 8, and 12 years.

Timeline diagram

timeline
    title Ownership of US 6774033
    2002 : Filed by Cypress Semiconductor
         : Inventors assign rights to Cypress
    2010 : Cypress sells to Sansocca Alandro AB LLC
    2015 : Sansocca merges into Callahan Cellular LLC
    2019 : Callahan transfers to Intellectual Ventures Assets 156
    2020 : IV Assets 156 assigns to Innovative Silicon Solutions
         : Renamed HD Silicon Solutions LLC
         : Suit v Microchip filed in W D Texas
    2025 : Federal Circuit affirms invalidity of most claims

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT. The chain leaves operating ownership in 2010 and never returns: Cypress → SanSocca Alandro A.B., LLC (Reel 025328/0024, executed 2010-07-30) → Callahan Cellular L.L.C. (Reel 037406/0037) → Intellectual Ventures Assets 156 LLC (Reel 051550/0682) → Innovative Silicon Solutions, LLC → HD Silicon Solutions LLC (Reel 054993/0795). The downstream entities are Delaware/Texas holding and licensing LLCs with no products in commerce; the current owner's only public footprint is as a plaintiff in infringement suits (Stanford NPE Litigation Database and RPX Insight both list HD Silicon Solutions as the asserter in HD Silicon Solutions v. Microchip and HD Silicon Solutions v. NXP). The recordation form for the 2020 transfer also shows a service-style California street address rather than a corporate campus, and the address had to be "corrected" from California to Texas at Reel 052253/0751.

2. Known asserter in the chain — PRESENT. Two independent hits: (a) Intellectual Ventures Assets 156 LLC (Reel 051550/0682, executed 2019-12-16) is, by its own recorded legal name, an Intellectual Ventures asset entity, and IV is on the named asserter list; (b) the current owner HD Silicon Solutions LLC is a serial plaintiff — HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20-cv-01092 (W.D. Tex., filed 2020-11-30; transferred to N.D. Cal. as 3:21-cv-08295) and HD Silicon Solutions LLC v. NXP USA, Inc., No. 1:25-cv-01320 (W.D. Tex., filed 2025-08-19) — with RPX Insight and the Stanford NPE database cataloguing it as the asserter.

3. Repeat correspondent across the chain — UNCLEAR / insufficient evidence. The only correspondent I could retrieve is Fahim Aftab (e-mail fahim@hongdungroup.com, 949-791-9366), appearing as correspondent/submitter on the 2020-03-23 IV Assets 156 → Innovative Silicon Solutions recordation (the transaction corresponding to Reel 052199/0838), as shown in the recordation documentation filed as Exhibit 1004 in IPR2021-01420. That is one appearance, and most firms do both NPE and operating-company work; per the stated standard, one appearance is not a finding. The correspondent fields for Reels 013460/0336, 025328/0024, 037406/0037, 051550/0682, 052253/0751, and 054993/0795 were not retrieved and are not guessed at. This signal needs an Assignment Center pull before it can be scored either way.

4. Cascading transfers — PRESENT. Four recorded ownership events in under 12 months: executed 2019-12-16 (Reel 051550/0682), 2020-01-10 (Reels 052199/0838 and 052253/0751, the latter a same-party correction), and effective 2020-11-10 (Reel 054993/0795). Three of the first four are within a 25-day window (2019-12-16, 2020-01-10, 2020-01-10), and the link into the asserting entity was executed nunc pro tunc with a backdated effective date — a hallmark of a deliberately constructed standing record.

5. Pre-litigation transfer — PRESENT. The Change of Name to HD Silicon Solutions LLC took effect 2020-11-10 (Reel 054993/0795), and the first infringement suit naming this patent — HD Silicon Solutions v. Microchip, No. 6:20-cv-01092 — was filed 2020-11-30 in the Western District of Texas: 20 days later. The upstream nunc pro tunc assignment into the asserting entity was executed 2020-01-10 (Reel 052199/0838), ~10.7 months before suit. The combination — fresh name, Texas address correction, Texas forum, brand-new plaintiff — fits the venue-and-standing-engineering pattern, though the 20-day gap is the tightest and most probative datum.

6. Bankruptcy fire-sale — NOT PRESENT. Cypress was solvent and independent when it sold the patent in 2010; it was later acquired by Infineon (completed 2020), not liquidated under Chapter 7/11. No bankruptcy docket appears anywhere in the chain.

7. Privateering — NOT PRESENT (not supported). Cypress sold the rights in 2010 and is not a beneficiary of the 2020–2025 assertions: the defendants are Microchip and NXP, not Cypress competitors, and Cypress/Infineon does not appear as a real party in interest in the IPRs or the district-court cases reviewed. The Cypress→IV-family sale is better characterized as portfolio monetization than as a proxy campaign run on the seller's behalf. Marking present would require an SEC filing or litigation-financing disclosure tying Cypress/Infineon to the assertions, which I did not find.

8. Defensive aggregator — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at HD Silicon Solutions LLC, an active plaintiff. RPX and Unified appear in this file only as indexers of the Microchip IPRs (Google's "Petitioner" field on the IPR links points at Unified's public portal, but the actual petitioner of record in both IPR2021-00752 and IPR2022-00105 is Microchip Technology Inc.). The patent has not been neutralized by acquisition — though it has been substantially invalidated (below).

Verdict

NPE — high confidence.

At least three strong signals converge on the same reel/frame record: (i) ownership left an operating manufacturer in 2010 for a chain of Delaware/Texas holding and licensing entities — Reel 025328/0024 (Cypress → SanSocca Alandro A.B., LLC, executed 2010-07-30), Reel 037406/0037 (merger into Callahan Cellular L.L.C.), Reel 051550/0682 (into Intellectual Ventures Assets 156 LLC, executed 2019-12-16); (ii) the terminal assignee is a named serial asserter, HD Silicon Solutions LLC (Reel 054993/0795, name change effective 2020-11-10), plaintiff in HD Silicon Solutions v. Microchip (W.D. Tex. 6:20-cv-01092) and HD Silicon Solutions v. NXP USA (W.D. Tex. 1:25-cv-01320); and (iii) the pre-suit restructuring — nunc pro tunc assignment executed 2020-01-10, Texas address correction at Reel 052253/0751, rename effective 2020-11-10, suit filed 2020-11-30, 20 days later. This is an assertion vehicle whose ownership chain was arranged for enforcement, not an operating company asserting against competitors.

Status caveat worth flagging for any licensing analysis: the asset is largely spent. The PTAB's Final Written Decision in IPR2021-00752 (Nov. 7, 2022) held claims 1–7 and 9–17 unpatentable over U.S. 5,847,463 (Trivedi), and the Federal Circuit affirmed on Feb. 6, 2025 (HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23-1397), finding the Board's construction of "comprising tungsten" erroneous but harmless. Only claim 8 survived, and the IPR certificate issued 2025-06-24; the patent itself had already expired on 2022-11-04 for failure to pay the 20-year maintenance fee. So the NPE verdict is historically correct, but the "high-confidence NPE" chain now owns an expired patent with a single surviving claim.

Verification link: USPTO Assignment Center / Patent Assignment Search, query patent number 6774033 — https://assignment.uspto.gov/patent/index.html (Assignment Center front end: https://assignmentcenter.uspto.gov/). Pull the abstract of title for Reels 013460/0336, 025328/0024, 037406/0037, 051550/0682, 052199/0838, 052253/0751, and 054993/0795 to fill in the correspondent-of-record fields that I could not retrieve.

I'll search for the patent and its cited prior art references.

Let me get details on the second cited reference.

Let me verify bibliographic details for both cited references.

Prior-Art Analysis — U.S. Patent No. 6,774,033 B1

1. Verification of the Patent (USPTO record)

The patent's independent claims are directed to (i) a method of forming a local interconnect layer by depositing a titanium‑nitride first film over an oxide layer and a tungsten second film over the first film (claim 1), and (ii) the same step performed by sputtering in the same tool (claim 15).

Per the operating rules, all identifiers are read literally; US 6,774,033 is not to be confused with any similar number, and only this patent's own citations were used.

2. Patent Citations of Record on US 6,774,033

The face of US 6,774,033 (and the Google Patents "Citations (2)" section) lists exactly two references cited by the examiner. Both were used against the application during prosecution.

Reference A — US 6,232,209 B1 ("Fujiwara et al.")

Brief description: Discloses a three‑layer gate electrode (not a local interconnect) consisting of a doped polycrystalline‑silicon layer, a barrier layer (W, WN, TiN, etc.), and a metal layer (e.g., W). The metal layer and barrier layer are etched using the barrier layer and/or the polysilicon layer as an etching stopper. Fluorine‑based chemistry is used for etching the W metal layer; the reference solves etch‑endpoint and etch‑selectivity problems.

§ 102 exposure (as reflected in the file history of the '033 application):
In the Office Action mailed 2003‑09‑17 and responded to on 2003‑12‑16 (app. 10/287,258, art unit 2824), the examiner rejected:

• § 102(b) anticipation by Fujiwara: prosecution claims 1–3, 9–14, 18 and 20
• § 103(a) obviousness over Fujiwara: prosecution claims 4–8 and 19

Because prosecution claims 15–17 were cancelled and replaced by claims 18–20, the prosecution claim numbers map to the granted set as: 18→15, 19→16, 20→17. Accordingly, the references above correspond to § 102/§ 103 challenges against granted claims 1–3, 9–14, 15, 17 (102(b)) and 4–8, 16 (103(a)).

Outcome / rebuttal: The applicants traversed, arguing Fujiwara's barrier layer 4 and metal layer 5 are parts of a gate electrode 7 (col. 9, lines 44–48), not a local interconnect layer, and that local interconnects and gate electrodes have materially different process requirements. On that basis claims 1 and 18 (granted 1 and 15) and their dependents were argued to be patentable over Fujiwara, and the application proceeded to allowance (Notice of Allowance mailed 2004‑03‑17). § 102 is therefore only a potential, not a confirmed, anticipation — the examiner's rejection did not stand.

Reference B — US 6,228,761 B1

Brief description: Addresses over‑etching that disconnects diffusion regions at field edges during damascene local‑interconnect formation. A nitrogen‑containing etch‑stop layer (PECVD SiON or SiN) is deposited, then enriched with nitrogen via a nitrogen plasma to increase its etch selectivity relative to the overlying dielectric and the underlying silicide (TiSi₂, CoSi₂, WSi₂, NiSi₂). Tungsten is deposited into the local‑interconnect opening. It is a local‑interconnect reference but is directed to etch‑stop selectivity and nitrogen enrichment of a dielectric, not to a TiN/W metal stack.

§ 102 exposure: This reference is listed among the "References Cited" on the face of US 6,774,033, but in the prosecution papers I could retrieve, the confirmed § 102(b)/§ 103(a) rejections were based on Reference A (Fujiwara). I found no confirmed § 102 rejection grounded on US 6,228,761. Its teaching of tungsten in a local interconnect is the aspect most relevant to '033's tungsten film, but it does not disclose a TiN‑under‑W stack, so a § 102 anticipation mapping is not supportable on the record available; at most it is background/§ 103 art.

3. The Most Relevant Prior Art Actually Litigated (IPR)

The reference with the greatest practical relevance to the validity of US 6,774,033 is not one of the two examiner citations but the IPR art:

• IPR2021‑00752 — Petitioner Microchip Technology Inc., filed 2021‑04‑23 (Final Written Decision). Primary reference: "Trivedi" (U.S. Patent disclosing TiN + tungsten‑silicide layers, FIG. 2/FIG. 5). Secondary references: Joo, Gunturi, Lai, Kizilyalli, Hayashi.
• IPR2022‑00105 — also Microchip, filed 2021‑11‑04 — Not Instituted (procedural).
• IPR certificate (K1) issued 2025‑06‑24 for IPR2021‑00752.
• Related litigation: N.D. Cal. 3:21‑cv‑08295; W.D. Tex. 6:20‑cv‑01092; W.D. Tex. 1:25‑cv‑01320; Fed. Cir. 23‑1397.

In the IPR, Petitioner argued Trivedi discloses claim 1's structure (TiN film under a film "comprising tungsten," the tungsten being in the form of tungsten silicide, WSi_x), and that a POSITA would read "comprising tungsten" and "metal stack" to include tungsten silicide. Patent Owner (HD Silicon Solutions) argued the reverse (elemental‑tungsten requirement) and distinguished gate electrodes from local interconnects — the same distinction used during original prosecution against Fujiwara.

Caveat: I could not retrieve the substantive result of the IPR2021‑00752 Final Written Decision (e.g., which claims, if any, were cancelled or confirmed). I therefore do not assert an outcome beyond the fact that the certificate issued on 2025‑06‑24.

4. Summary Table of Patent Citations of Record

5. Notes and Limitations

• § 102 category: Both cited references granted/published more than one year before the '033 filing date (2002‑11‑04), so any anticipation would fall under § 102(b) (statutory bar), as the examiner actually applied.
• The examiner's § 102 rejection (Reference A) was withdrawn after amendment of claim 1 to expressly recite a "local interconnect layer." The mapping above describes the examiner's asserted anticipation, not an adjudicated invalidity.
• I could not obtain the application number for US 6,228,761 (I did not find it in the sources retrieved) or the substantive outcome of IPR2021‑00752; those are explicitly flagged rather than guessed.
• Any anticipation conclusion is a preliminary, claim‑chart‑level assessment based on the patent text and retrieved prosecution/IPR documents, and should be confirmed against the full file wrapper and the IPR Final Written Decision.

I'll ground this analysis in the actual cited prior art. Let me pull details on the two examiner-cited references and a few closely related documents.

I have strong primary-source material, including the actual IPR record on this patent. Let me confirm the IPR outcome and the Federal Circuit appeal, since those bear directly on the § 103 analysis.

Obviousness Analysis — U.S. Patent No. 6,774,033 B1 ("Metal Stack for Local Interconnect Layer")

Note on sources: The following is built on (a) the full text of the '033 patent as fetched from Google Patents, (b) the two references listed in the page's Patent Citations (2) section, (c) the page's Similar Documents list, and (d) the litigation/PTAB entries that the page itself links (IPR2021‑00752, IPR2022‑00105, IPR certificate K1, CAFC No. 23‑1397). Where a reference's disclosure could not be verified from the fetched material, I say so rather than fill the gap. This is an analysis, not a legal opinion.

1. Legal framework and the controlling date

• Priority/filing date: November 4, 2002; granted August 10, 2004. Because the application was filed before March 16, 2013, pre‑AIA 35 U.S.C. §§ 102/103 govern. References must therefore qualify under § 102(a), (b), (e), or (f) as of November 4, 2002 (with the one‑year § 102(b) bar cutting off at November 4, 2001).
• Governing obviousness test: Graham v. John Deere (scope/content of prior art; differences; PHOSITA level; secondary considerations) as refined by KSR Int'l v. Teleflex, 550 U.S. 398 (2007) — a claimed combination may be obvious where the elements are known, the combination yields predictable results, and there is an articulated reason (design incentive, known benefit, "try it and see," or a finite number of identified, predictable solutions). The PTAB applied exactly this framework in the IPR on this patent, expressly listing the KSR "design incentives / market forces," "known technique to improve similar devices," and "predictable results" rationales.
• Analogy: The '033 claims are directed to interconnect metallization in integrated circuits. Damascene local-interconnect fill, gate‑stack metallization, contact/via plug metallization, and subtractively patterned local interconnect lines are all reasonably pertinent to the problem the patent addresses (forming a thin, low‑resistivity patterned conductor over an oxide with an etch‑selective stop). They are therefore analogous art.

POSITA (as found in the IPR, undisputed by the patent owner): a master's degree in EE, materials science, or physics plus 3–5 years of semiconductor device/fabrication experience, or a bachelor's degree in EE plus more experience. The '033 patent's own subject matter is process engineering at the thin‑film deposition/etch level, so this level of skill is the right lens.

2. What claims 1 and 15 actually require (scope of the prior art)

Critically, neither independent claim recites an etch step, a resist, a mask, a probe, thickness, or resistivity. Claim 1 reduces to a two‑step deposition sequence (TiN then W) over an oxide layer, on a local interconnect layer. That breadth is dispositive of most of the § 103 analysis below: it collapses the distance between the claim and any art that shows a tungsten layer over a titanium‑nitride layer over an oxide in an interconnect context, whether deposited by sputtering, CVD, or PVD.

The specification itself supplies the reason to combine. The Background states flatly:

"A local interconnect layer may be conventionally formed by depositing a film of titanium nitride over an oxide layer. For example, a 1000 Angstroms or 700 Angstroms thick titanium nitride film may be deposited over an oxide layer by sputtering."

That is a binding admission that a sputtered TiN local interconnect over an oxide is prior art (pre‑AIA, applicant's own admission of what was "conventionally" done). The patent then identifies the two problems the W cap solves — resist poisoning by nitrogen from TiN, and the fixed problem of titanium oxynitride (hard, unprobeable, higher resistance) — and states the advantages of tungsten: "relatively low resistivity compared to titanium nitride," "chemically stable," permitting in‑situ deposition in the same cluster tool. These are precisely the articulated, predictable‑benefit rationales KSR requires.

3. The two references on the page's "Patent Citations (2)" list

3.1 US 6,228,761 B1 — Advanced Micro Devices (priority 1999‑10‑14; granted 2001‑05‑08)

"Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide"
URL: https://patents.google.com/patent/US6228761

What it teaches (verified from the fetched text):

• A local interconnect formed by a damascene/fill process: an opening is etched through a dielectric, stopped on a nitrogen-containing etch‑stop layer (PECVD SiON or SiN), and the opening is then "filled with a conductive material, such as tungsten 34," over a barrier layer.
• The invention addresses over‑etch of the interconnect opening through the etch‑stop layer into the underlying silicide/diffusion region ("a dip 30 into the substrate") at the field edge. The fix is enriching a nitrogen‑containing etch‑stop layer with a nitrogen plasma (with the express option of doing it in‑situ in the same PECVD chamber).
• Express teaching of a barrier layer beneath a tungsten conductor in a local interconnect, and of an etch‑selective nitride layer between the tungsten conductor and the underlying oxide/silicide.

Gap I could not verify from the fetched material: whether the '761 barrier layer is expressly titanium nitride. The abstract and fetched description confirm "a barrier layer" but the snippet I retrieved does not name TiN. I flag this because the examiner's citation may have relied on the generic barrier‑layer disclosure. A § 103 case built on '761 alone would therefore be incomplete as to the "first film comprising titanium nitride" limitation and would need a second reference (below) to supply TiN specifically.

3.2 US 6,232,209 B1 — Mitsubishi Denki K.K. (priority 1999‑06‑11; granted 2001‑05‑15)

"Semiconductor device and manufacturing method thereof"
URL: https://patents.google.com/patent/US6232209

What it teaches (verified from the fetched text and the Google Patents concept/claim indices):

• A stacked conductor with a metal layer over a barrier (nitride) layer: the conventional structure analyzed is "a tungsten (W) layer as a metal layer 5, a tungsten nitride (WN) layer as a barrier layer 4, and a polycrystalline silicon layer 3," with a silicon‑nitride hard mask.
• Titanium nitride appears in the reference's own claim set ("Titanium nitride … claims description 4"), i.e., TiN is an expressly claimed nitride/barrier material option.
• Tungsten is likewise claimed ("tungsten … claims description 7/8").
• "in‑situ" appears in the reference's claimed subject matter — supporting in‑situ processing of the stack.
• The core technical problem it solves is exactly the etch‑selectivity problem the '033 patent later recites as an advantage of its TiN underlayer: a fluorine‑containing gas used to etch the W metal layer also etches the underlying nitride barrier and removes SiO₂, gouging a "recess 16 … through gate insulating layer 2 to semiconductor substrate 1"; the fluorine etch also makes endpoint detection of the W/WN etch difficult; and Cl₂/O₂ plasma gives poor W:SiN selectivity (diluting the hard mask that later serves as a self‑aligned‑contact stop).
• Its solution is a two‑step, chemistry‑differentiated etch of a nitride layer and an overlying metal layer using a mixed gas of O₂ plus one of CF₄, CHF₃, CH₂F₂, with the oxygen concentration higher for the metal (W) layer than for the nitride layer — i.e., an etch that stops selectively on the underlying nitride.

That is a textbook teaching of (i) a W layer over a nitride (including TiN) barrier layer, (ii) the need for etch selectivity between them, and (iii) stopping an overlying‑metal etch on an underlying nitride so as not to gouge the oxide beneath.

4. Combination A — US 6,232,209 (Mitsubishi) in view of US 6,228,761 (AMD), with the applicant's admitted TiN local interconnect

This is the natural reading of the page's citation list and, in my view, the combination the examiner was weighing (and ultimately did not use to reject, which is itself significant — see §7).

How the elements map:

• Oxide layer + local interconnect context: '761 (dielectric over silicide/diffusion; local interconnect opening) and the '033 Background admission.
• First film comprising titanium nitride: '209 (TiN expressly among the claimed nitride/barrier materials in a W‑over‑barrier stack) and/or '761's barrier layer.
• Second film comprising tungsten over the first: '209 (W metal layer over the nitride barrier) and '761 (tungsten fill over a barrier).
• Metal stack of the local interconnect layer: '761 (local interconnect) + '209 (stack metallurgy).
• Sputtering / same‑tool (claim 15): '209's in‑situ processing disclosure plus conventional PVD practice; the '033 Background admits sputtered TiN local interconnects.

Motivation to combine (articulated, not hindsight):

1. Same field, same problem. Both references are directed to the identical problem the '033 patent posits: depositing/etching a tungsten‑based conductor without destroying the layer beneath it. '761 solves it with a nitrogen‑enriched etch stop in a local interconnect; '209 solves it with an etch chemistry that stops on a nitride under a W layer. A POSITA improving either would look to the other.
2. Known material, known property. TiN's dual role as a diffusion barrier/adhesion layer and an oxide‑compatible etch stop was well established (and the '033 patent itself concedes both: "titanium nitride … may be patterned using an oxide layer as an etch stop. Additionally, titanium nitride may serve as a barrier and adhesion layer for a subsequently deposited tungsten film"). Selecting TiN as the barrier under W is a KSR "known element with known function" combination.
3. Predictable benefit of the W cap. The '033 specification enumerates the benefits that the combination would have been expected to deliver: lower stack resistivity ("Tungsten also has a relatively low resistivity compared to titanium nitride"), chemical stability (avoiding nitride‑to‑resist interaction), and the elimination of a separate oxidation/PECVD step and tool. A POSITA would have recognized these as predictable, not unexpected.
4. Fabrication efficiency. '209's in‑situ claim language and the routine availability of multi‑chamber PVD cluster tools (the '033 patent cites Applied Materials' ENDURA as commercially available) supply the reasoning for claim 15's "same tool" limitation with no new equipment development.
5. A finite, predictable set of options. Given two nitride barriers in commercial use (TiN, WN) and two refractory conductors (W, W‑silicide), selecting TiN+W is the kind of "finite number of identified, predictable solutions" KSR treats as obvious — and the results (Table 1/2 below) were unsurprising.

Weaknesses of this specific pairing: (a) '761's fill geometry is not a blanket stack subtractively patterned into lines, and claim 1 arguably does not care (it recites only deposition); (b) '761's barrier material is not confirmed as TiN; (c) '209's context is a gate stack, not a local interconnect — the "analogous art / reasonable expectation" rebuttal a patent owner would press. The combinations in §5 answer (c) directly.

5. Combination B — the stronger, as‑adjudicated combinations (from the PTAB record linked on the page)

The page links IPR2021‑00752 ("Final Written Decision") and IPR2022‑00105 ("Not Instituted"). Those records supply grounds that are materially stronger than the examiner's two references, and the outcome is instructive.

5.1 Ground 1 — Trivedi, U.S. Pat. No. 5,847,463 (primary reference in IPR2021‑00752)

Per the Federal Circuit's February 6, 2025 opinion in HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23‑1397 (https://www.cafc.uscourts.gov/opinions-orders/23-1397.OPINION.2-6-2025_2464314.pdf), Trivedi is "directed to a method of forming a local interconnect structure" having "tungsten silicide and titanium‑nitride layers, or alternatively a tungsten layer with titanium nitride over it." The petitioner's demonstratives quote Trivedi's structure as a stack in which a first barrier layer is "preferably substantially composed of titanium nitride (TiN) … formed using a conventional process such as sputtering," with a layer formed thereover, and a photoresist formed over that layer. Trivedi also discloses both a tungsten‑silicide layer and an elemental tungsten layer as the overlying film.

Claim 1 read on Trivedi: TiN barrier layer over oxide layers; tungsten layer over the TiN; the combination forming the local interconnect's metal stack; photoresist directly on the W/no‑poisoning benefit realized. Claim 1's "comprising tungsten" was construed by the Board to cover tungsten compounds (tungsten silicide); the Federal Circuit rejected that construction and held "comprising tungsten" requires elemental tungsten — but affirmed anyway, because substantial evidence supported the Board's alternative finding that Trivedi discloses elemental tungsten as the second film. That is the key point for § 103 purposes: the reference itself, under the correct claim construction, discloses the limitation.

Motivation: Trivedi is the same field (local interconnect), addresses the same etch‑selectivity/poisoning problems, and its TiN layer is expressly described as sputtered — the same process recited in claim 15.

5.2 Ground 2 — Trivedi in view of Joo, U.S. Pat. No. 6,534,401

Joo ("Method for Selectively Oxidizing a Silicon/Metal Composite Film Stack") discloses composite film stacks of silicon/barrier/metal for electrodes and interconnects, with a tungsten film over a barrier layer, and TiN as an express alternative to WN as the barrier. It supplies (i) the interconnect (not merely gate) context for the W‑over‑TiN stack and (ii) PVD/sputtering as the deposition technique for both layers, supporting claims 2, 3, 5, 6, 15 and 16.

Motivation (as argued and accepted): both layers can be formed by sputtering, "possibly in a single sputtering chamber," which a POSITA would recognize simplifies and speeds manufacturing and reduces equipment needs; and Joo supplies a functional thickness range for the W layer adjacent to a nitride barrier, addressing claim 6. This is the classic KSR "known technique to improve a similar process with predictable results" rationale.

5.3 Other dependent‑claim grounds (IPR2021‑00752)

• Claims 2, 11, 12 — Trivedi + Lien: fluorine‑based etch for the tungsten layer (e.g., SF₆) and chlorine‑based etch for the titanium nitride (BCl₃/Cl₂) are conventional, chemistry‑driven selections; the '033 specification itself recites exactly these (SF₆ for W stopping on TiN; BCl₃ or Cl₂ for TiN stopping on oxide), and other art of record (e.g., U.S. 6,103,623, claim 12: "second dry etching ambient, comprised of SF₆") confirms the ordinary skill level.
• Claims 13, 17 — Trivedi + Johnson: electrical probing of an exposed W surface is a routine in‑line test step; the patent's own Table 1 data were obtained by "conventional 4‑point probe electrical testing."
• Claim 8 — Trivedi + Yang: this ground failed (see §6).
• Claim 7 (300 Å W / 300 Å TiN) — Trivedi + Joo + Yang: the specific paired thicknesses are routine optimization of a result‑effective variable (sheet resistance), and the patent's Table 1 shows a monotonic trend with W thickness — 25.67 → 17.12 → 10.88 → 9.41 Ω/sq. for 100/300, 200/200, 300/200, 300/300 — i.e., the claimed point sits at the end of a predictable trend rather than off it.
• Claim 4 / claim 16 (≤ ~600 Å stack): satisfied by the disclosed pairs (300+300, 200+300, etc.).
• Claim 14 (resist directly on the W): Trivedi discloses photoresist formed over its overlying layer.
• Lead claim 9 / claim 10 (etch the second film stopping on the first; etch the first stopping on the oxide; oxide over a semiconductor substrate): Trivedi and the '761 etch‑stop teaching supply both steps; the '033 patent's stated advantage that "a film 103 of titanium nitride advantageously helps prevent gouging of oxide layer 102" is precisely the problem US 6,232,209 identified and solved (fluorine etch of W also removing SiO₂).

5.4 IPR2022‑00105 — Lin (U.S. 6,083,827)‑based grounds (not instituted)

The second IPR relied on U.S. 6,083,827 (Lin), "Method for Fabricating Local Interconnect," alone for claim 1 ("Lin is directed to a 'method for fabricating a local interconnect' … The local interconnect, formed over several oxide regions, includes a metal stack of a tungsten layer over a titanium‑nitride layer") and in combinations with Peng (U.S. 6,043,148), Huang (US 2002/0137356), and Lo (U.S. 5,643,632). Lin alone would be the cleanest lead reference in the whole record — an actual local interconnect with a W‑over‑TiN metal stack — but the petition was Not Instituted (Procedural), so no merits determination exists on it. Its existence nonetheless matters to the § 103 picture: it shows the W‑over‑TiN local interconnect stack was squarely in the art before November 2002.

6. Claim 8 — the one claim that survived, and why it complicates the analysis

Claim 8 (dependent on claim 1) adds: "wherein the first film and the second film form a metal stack having a sheet resistance equal to or less than about 10 Ohm/sq."

• The Board found Microchip did not prove claim 8 unpatentable, while invalidating claims 1–7 and 9–17. The Federal Circuit affirmed. Notably, the final record contained "no argument or evidence directed to secondary considerations of nonobviousness" — so claim 8's survival rests on the petitioner's evidentiary gap, not on an affirmative showing of unexpected results.
• The gap is easy to see and easy to criticize: the patent's own Table 1 (in‑line) shows the 300/300 stack at 9.41 Ω/sq. (σ = 0.27) and Table 2 (end‑of‑line) at 9.22 Ω/sq. (σ = 0.21), versus 10.88 (300/200), 10.71 (200/300), 17.12 (200/200), and 25.67 (100/300). Because claim 8 depends only on claim 1, any 300/300 W‑on‑TiN stack that meets claim 1 automatically meets claim 8 — i.e., claim 8 may add no independent patentable weight beyond an inherent result of the claim‑1 combination. A properly supported obviousness case on claim 8 would need (i) evidence that the cited stack thicknesses inherently yield ≤10 Ω/sq. (an inherency/result‑effective‑variable argument), or (ii) a teaching of the numerical range in the art. Neither was established.
• Practical consequence: after the Federal Circuit's affirmance, the page records an IPR certificate (K1) issued June 24, 2025 for trial IPR2021‑00752, which reflects cancellation of the claims held unpatentable, leaving claim 8 as the surviving issued claim. That is consistent with the newest district‑court filing listed on the page (W.D. Tex. 1:25‑cv‑01320, 2025) — though I cannot confirm from the page which claims that suit asserts.

7. Why the examiner's two cited references apparently did not produce a rejection

Two structural reasons, both of which a § 103 challenger must overcome:

1. No single one of them shows the claimed stack in a local interconnect. '761 shows tungsten in a local interconnect but via a damascene fill over a generic barrier, and I could not confirm TiN specifically. '209 shows a W‑over‑nitride (TiN/WN) stack, sputtered/in‑situ and etch‑selective to an underlying oxide, but in a gate stack, not a local interconnect. Neither reference, alone, discloses "a metal stack of the local interconnect layer" formed by depositing TiN then W as layers over an oxide.
2. The examiner had no evidence of the combination's articulated reason to combine. Nothing in '761 or '209 describes resist poisoning from TiN, and neither frames its W layer as a solution to that problem. The motivation for the combination therefore has to be constructed from (a) the applicant's own Background admission that sputtered TiN local interconnects were conventional and suffered resist poisoning, and (b) the known properties of W (low resistivity, chemical stability, PVD‑compatibility) — which is exactly the reasoning the '033 specification itself sets out, and which the petitioner successfully relocated into the prior art via Trivedi and Joo in IPR2021‑00752.

8. Bottom line

• Claims 1, 9, 10, 14 over Trivedi alone; claims 2–7 and 15–16 over Trivedi in view of Joo; claims 11–12 over Trivedi in view of Lien; claims 13, 17 over Trivedi in view of Johnson — this is the combination set that was adjudicated obvious (IPR2021‑00752 FWD, Nov. 7, 2022), affirmed by the Federal Circuit on Feb. 6, 2025 under a corrected claim construction requiring elemental tungsten, and memorialized by IPR certificate K1 on June 24, 2025.
• The page's two examiner‑cited references (US 6,228,761 and US 6,232,209) are not, by themselves, a complete § 103 case for independent claims 1 and 15: '761 lacks a confirmed TiN film in a blanket stack and uses a fill geometry; '209 is gate‑stack, not local‑interconnect, art. They become usable only when combined with the applicant's own admitted sputtered‑TiN‑over‑oxide local interconnect and a reference (Trivedi, Lin, or the WO 1997/017724‑type "local wiring" disclosures) that supplies the W‑over‑TiN stack in a local interconnect.
• Claim 8 remains standing and is the analytically weakest part of the patent, but it survived because the petitioner did not marshal inherency or art evidence for the "≤ about 10 Ohm/sq." limitation, not because the limitation was shown to be non‑obvious. Its survival under a claim‑1‑only dependency, given the patent's own Table 1/2 data, is the most obvious remaining attack surface.
• No secondary considerations were presented or credited anywhere in the record; the final written decision expressly notes the absence of such evidence.

Caveats / unverified items: (1) I could not confirm from the fetched excerpt whether US 6,228,761's barrier layer is expressly titanium nitride; (2) the exhibit numbering differs across the two petitions (e.g., "Ex. 1004" refers to Lin in the IPR2022‑00105 papers and to Trivedi in the IPR2021‑00752 papers), so citation labels should not be cross‑used between proceedings; (3) the FWD date is reported as Nov. 7, 2022 by the PTAB docket aggregators while one PTAB document header reads "DATED: January 6, 2023" — I have not reconciled these; (4) I have not verified which claims the 2025 W.D. Tex. action asserts.