US 5530890

I'll search for current information on this patent, including any recent litigation activity.

Let me check for any recent (2026) litigation and verify the current legal status.

US Patent 5,530,890 — "High Performance, Low Cost Microprocessor"

Bottom line on the search request

I found no CAFC docket for US 5,530,890 in 2026. Nothing in the currently indexed Federal Circuit activity involves this patent number. The Google Patents litigation record for this patent lists only district-court and CAFC cases from roughly 2008–2018 (e.g., CAFC 14‑1317, 16‑1306, 16‑1307, 16‑1309, 16‑1311, 18‑1439, 18‑1440, 18‑1441, 18‑1444, 18‑1445; Supreme Court No. 19‑324). Given that the patent expired June 25, 2013, a live 2026 appeal would be unusual. I flag this as absence of evidence rather than proof — my search of the 2026 CAFC calendar was not exhaustive.

Bibliographic data

Assignees of record (per Google Patents assignment history): Nanotronics Corp. → Patriot Scientific Corp. (Oct. 1996); ITV Corp. (Sept. 1997, from Moore); Technology Properties Limited (Oct. 2003, from ITV and Moore); Moore, Charles H., TTE, UTD 03/21/2006 The Equinox Trust (Mar. 2009). Patriot Scientific and Technology Properties Limited remain listed among current assignees.

Abstract (as published)

A microprocessor (50) includes a main central processing unit (CPU) (70) and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making up the microprocessor (50). The main CPU (70) has a first 16 deep push down stack (74), which has a top item register (76) and a next item register (78), respectively connected to provide inputs to an arithmetic logic unit (ALU) (80) by lines (82) and (84). An output of the ALU (80) is connected to the top item register (76) by line (86). The output of the top item register at (82) is also connected by line (88) to an internal data bus (90). A loop counter (92) is connected to a decrementer (94)… Stack pointer (102), return stack pointer (104), mode register (106) and instruction register (108) are also connected to the internal data bus (90)… The internal address bus provides inputs to the memory controller (118) and to an incrementer (144)… The DMA CPU (72) provides inputs to the memory controller (118) on line (148).

In substance: a deliberately simple, low-pin-count 32-bit stack-based RISC microprocessor that talks directly to DRAM over a triple-multiplexed address/data bus, with a separate DMA processor handling device-side memory traffic.

Prosecution / reexamination history (important for claim scope)

The patent was substantially rewritten in reexamination (Certificate C1, published in the Official Gazette). The certificate states:

• Claims 1–4 — cancelled
• Claims 5–10 — confirmed
• New claims 11–20 — added and determined patentable

This means the enforceable claim set as of the certificate is claims 5–20, not the original claims 1–4. Any 2012–2018 assertion of this patent would have rested on the certificate claims.

Plain-language overview of the independent claims

⚠️ Uncertainty disclosure: The authoritative full text supplied to me is truncated before the original claims section, so I do not have verbatim text for original independent claims 1–4 or for confirmed claims 5–10. What I can state authoritatively:

Claim 11 (new independent claim added in reexamination — verbatim from the certificate):

"11. A microprocessor, which comprises a main central processing unit and a separate direct memory access central processing unit in a single integrated circuit comprising said microprocessor, said main central processing unit having an arithmetic logic unit, a first push down stack with a top item register and a next item register, connected to provide inputs to said arithmetic logic unit, an output of said arithmetic logic unit being connected to said top item register, said top item register also being connected to provide inputs to an internal data bus, said internal data bus being bidirectionally connected to a loop counter, said loop counter being connected to a decrementer, said internal data bus being bidirectionally connected to a stack pointer, return stack pointer, mode register and instruction register, said stack pointer pointing into said first push down stack, said internal data bus being connected to a memory controller, to a Y register of a return push down stack, an X register and a program counter, said Y register, X register and program counter providing outputs to an internal address bus, said internal address bus providing inputs to said memory controller and to an incrementer, said incrementer being connected to said internal data bus, said direct memory access central processing unit providing inputs to said memory controller, said memory controller having an address/data bus and a plurality of control lines for connection to a random access memory."

In plain terms: the microprocessor chip = two CPUs on one die (a main CPU + a separate DMA CPU); the main CPU is built around an ALU fed by the top two entries of a push-down stack (top-of-stack also feeding an internal data bus); that bus ties together the loop counter/decrementer, stack pointer, return stack pointer, mode register, instruction register and memory controller; three address registers (X, Y, program counter) drive an internal address bus with an incrementer; the DMA CPU feeds the same memory controller, which exposes an address/data bus and control lines to RAM. It is essentially a structural (apparatus) claim to the FIG. 2 architecture.

Original independent claims 1–4 (now cancelled) — inferred from the SUMMARY OF THE INVENTION, not verbatim: these appear to have covered (a) the CPU + DRAM + bus with multiplexing means placing row addresses, column addresses and data on the same bus, and (b) the instruction-fetch means that pulls multiple sequential instructions in a single memory cycle (including assembling instructions from a PROM into DRAM). I cannot confirm exact wording or numbering.

Claims 5–10 (confirmed): Based on the summary structure, these most plausibly correspond to independent claims directed to:

• the DMA/co-processor arrangement in which the DMA unit fetches both CPU instructions and its own instructions on the shared bus;
• the multiple-instruction fetch path with an instruction register, a counter, and a decoder issuing increment/reset control (including SKIP and MICROLOOP behavior);
• the ALU + push-down stack + register-file/return-stack combination;
• the output-enable feedback circuit (sensing circuit + driver that measures rise time on the OE line and returns a READY signal to adapt memory bus timing);
• the ring-counter, process-tracking variable-speed system clock paired with an independent crystal clock for the I/O interface; and
• the multi-level stack split across on-chip latches, on-chip RAM, and off-chip RAM with separate pointers.

Several further aspects detailed in the specification — the polynomial-generation ALU (A, B starting-polynomial, C feedback-term registers plus a down counter) and the serial fast-multiply ALU (result register, bit-reversed multiplier register, multiplicand register, down counter) — are described as arithmetic-logic modes and may be embodied in dependent claims of that confirmed set rather than in separate independents. I am not certain which of these are independent claims versus dependent claims, and I do not have their verbatim language.

Litigation context

The patent was part of the Moore Microprocessor Patent (MMP) portfolio (with US 5,440,749 and US 5,809,336), asserted by Patriot Scientific / Phoenix Digital Solutions / Technology Properties Limited against numerous technology companies from roughly 2008 onward. Reported outcomes included an adverse Federal Circuit ruling, a denial of Supreme Court review on November 4, 2019 (No. 19‑324), after which Patriot Scientific's SEC filings state the microprocessor patents were "no longer enforceable," with all US/European/Japanese portfolio members expiring between Aug. 2009 and Oct. 4, 2016. This is consistent with the June 25, 2013 expiration date shown for the '890 patent.

Caveats

• I could not obtain verbatim text of original claims 1–10; my descriptions of them are inferred from the SUMMARY OF THE INVENTION paragraphs and should be verified against the official patent copy before being relied upon.
• I found no 2026 CAFC activity for this patent; do not treat that as a definitive negative without re-checking PACER/CAFC dockets directly.
• The Google Patents page notes that its legal-status and assignee data are assumptions, not legal conclusions.

I'll search multiple sources for litigation involving US 5,530,890.

Good leads. Let me dig into specific case numbers, the ITC investigation, and the Federal Circuit/Supreme Court appeals.

Litigation Involving U.S. Patent No. 5,530,890 ("'890 patent")

Bottom line: Yes — the '890 patent has an extensive litigation history, but essentially all of it arises from the same long-running assertion campaign over the so-called "Moore Microprocessor Patent" (MMP) portfolio. The '890 patent was asserted as one of a bundle of related patents (principally U.S. 5,440,749, U.S. 5,809,336, U.S. 5,784,584 and 6,598,148) by Patriot Scientific Corp. and/or Technology Properties Ltd. ("TPL"). Notably, in nearly every case I could document, the '890 claims were dismissed, stipulated out, or never reached a merits trial — the one case that went to a jury verdict (HTC) went to the '336 patent only.

Methodology / source note: I searched the Unified Patents litigation portal (referenced via portal.unifiedpatents.com/litigation/caselist and PTAB exhibit material), Justia/Docket Alarm federal dockets, Casetext opinions, Stanford NPE Litigation Database (npe.law.stanford.edu), SEC filings (Barnes & Noble 8-K; Patriot Scientific/Mosaic ImmunoEngineering 10-Q), and contemporaneous trade press (EE Times, Design-Reuse, heise). Where I could not verify a specific docket number or outcome, I say so explicitly rather than filling the gap.

1. Ownership / priority disputes (pre-enforcement)

Sources: EE Times, "Patriot rejects offer for processor patents" (Nov. 11, 2004) and "Firm dismisses claims made by IP house Patriot Scientific" (Nov. 13, 2004); Design-Reuse/PRNewswire releases of Nov. 11 and Nov. 15, 2004.

2. 2008–2010 declaratory-judgment actions in N.D. Cal. (the core '890 cases)

Sources: Docket Alarm/Justia dockets for 5:08-cv-00882 and 5:08-cv-05398; Casetext, HTC Corp. v. Technology Properties Ltd.; Justia doc. 75 in Barco (order granting motion to dismiss Count One).

Other N.D. Cal. case numbers associated with this patent in Google Patents' litigation metadata (defendant mapping not verified): 3:10-cv-00816; 5:08-cv-00877 / 5:08-cv-00882 / 5:08-cv-05398 (E.D. Cal. and N.D. Cal. entries).

3. The 2012 wave — TPL / Patriot / Phoenix Digital Solutions assertion campaign

Filing date: July 24, 2012 — Technology Properties Limited LLC, Phoenix Digital Solutions LLC and Patriot Scientific Corporation filed a coordinated set of N.D. Cal. infringement complaints asserting U.S. 5,809,336 ('336), U.S. 5,440,749 ('749) and U.S. 5,530,890 ('890), alongside an ITC complaint filed July 23, 2012.

Named targets (per the parties' own descriptions and the Stanford NPE database): Acer, Amazon.com, Barnes & Noble, Garmin, HTC, Huawei, Kyocera, LG Electronics, Nintendo, Novatel Wireless, Samsung, Sierra Wireless, and ZTE.

Other 2012 docket numbers listed in Google Patents' litigation metadata for this patent (specific defendant mapping not confirmed by my searches): N.D. Cal. 3:12-cv-03863, 3:12-cv-03865, 3:12-cv-03876, 3:12-cv-03878, 3:12-cv-03881, 4:12-cv-03861, 4:12-cv-03865, 4:12-cv-03879, 5:12-cv-03870; E.D. Cal. 3:12-cv-03870, 3:12-cv-03877, 3:12-cv-03879.

ITC: the July 23, 2012 complaint led to a Section 337 investigation (the N.D. Cal. stay orders refer to it without stating the investigation number in the passages I retrieved). The specific investigation number (e.g., a 337-TA-8xx) is not verified by my sources and I will not guess it. The ITC ultimately found no violation as to the asserted '336 patent claims, and TPL did not appeal to the Federal Circuit (as recited in Barnes & Noble's motion practice).

4. Appeals — Federal Circuit and Supreme Court

Sources: Google Patents litigation metadata for US5530890A (listing CAFC cases 14-1317, 16-1306, 16-1307, 16-1309, 16-1311, 18-1439 through 18-1445; Supreme Court No. 19-324; and the district-court dockets); Mosaic ImmunoEngineering/Patriot Scientific Form 10-Q (FY2020 Q2) narrative at the "Commitments and Contingencies" and "Litigation" footnotes.

5. Related but distinct: reexamination (not litigation, but outcome-determinative)

• Ex parte reexamination of the '890 patent was initiated Jan. 19, 2009; an amended patent emerged March 1, 2011. Claims 1–4 were cancelled; claims 5–10 confirmed; new claims 11–20 added. The claims asserted in the HTC/TPL case were new claims 11, 12, 13, 17 and 19, and the reexamination added the limitation "said stack pointer pointing into said first push down stack" to independent claim 11 (per the Casetext opinion in HTC Corp. v. Technology Properties Ltd.). Barco's parallel reexamination history involved the '584 patent (notice of intent to reexamine Apr. 21, 2009; amended Claim 29 emerged July 21, 2009; further reexam request denied Nov. 4, 2009).
• The '890 patent's anticipated expiration is June 25, 2013 per Google Patents' legal-status metadata (which the portal marks as an assumption, not a legal conclusion). Trade press (heise, July 2012) similarly noted the '890 and '749 patents were expiring, leaving only the '336 patent with meaningful remaining life — which explains why '890/l'749 claims were progressively dropped and damages-only theories pursued.

6. Gaps and caveats (so you don't over-rely on this)

1. Filing dates for the 2004–2006 ownership suit (Patriot v. TPL/Leckrone/Moore) and any companion ITC action are not verified; only contemporaneous press coverage pins the dispute to Nov. 2004 with trial expected early 2005.
2. Defendant-to-docket-number mapping for most of the July 24, 2012 N.D. Cal. complaints is unverified. I confirmed LG = 3:12-cv-03880 (Stanford NPE DB) and Kyocera = 4:12-cv-03860 (Justia order). Barnes & Noble's docket number is not given in the SEC filing excerpt I retrieved.
3. The 2012 ITC investigation number is not verified. I deliberately did not assign a 337-TA-number because my sources did not state one.
4. CAFC Nos. 14-1317, 16-1306/1307/1309/1311 are documented only as entries in Google Patents' litigation metadata for US5530890A; I could not retrieve captions or dispositions within my search budget.
5. Several cases that name the '890 patent in early pleadings (Barco, HTC, the 2012 wave) later dropped the '890 claims; if you need the operative outcome for the '890 patent specifically, the key data points are: DJ Count One dismissed (Barco, Feb. 19, 2010) and stipulated dismissal of all '890 claims (HTC, Sept. 19, 2013).

Characterization for an opinion/clearance purpose: the '890 patent is expired (anticipated expiration June 25, 2013), was subject to ex parte reexamination that cancelled original claims 1–4 and added claims 11–20, and does not appear to have ever produced a merits judgment of infringement or a damages award. Its litigation value came from being bundled with the still-live '336 patent, which is where the jury verdict and all appellate activity actually occurred.

I'll start by verifying the structured block's "no AIA proceedings" signal against what's publicly findable, since this patent (Moore/TPL "MMP" portfolio) had a notorious assertion campaign.

Let me dig into whether any AIA trial ever targeted the '890 patent specifically, and identify the litigation chain (including the Supreme Court case 19-324 in the family data).

AIA Trial Proceedings — U.S. Patent No. 5,530,890 ("High performance, low cost microprocessor")

Proceedings overview

Total AIA trial proceedings on file: 0 (zero) — the structured USPTO ODP block reports no IPR, PGR, or CBM proceeding for US 5,530,890, and my independent web checks surfaced none: 0 active / 0 with claims invalidated / 0 with claims sustained / 0 settled / 0 institution denials. The bottom-line defensive posture is unusual and important: there is no PTAB record here to attack or to rely on — but that is not evidence the patent is a hardened rock. The '890 patent was fought over almost entirely in ex parte reexamination and in district court between 2008 and 2011, i.e., before IPR existed as a practical weapon (petitions could first be filed 2012‑09‑16), and the patent is now expired (Google Patents legal status: "Expired – Lifetime"; anticipated expiration 2013‑06‑25). A defendant today inherits a reexamination-narrowed, expired patent — not a PTAB-hardened one.

Reliability note. The absence of proceedings is sourced from the structured ODP block you supplied plus my searches (queries targeting "5,530,890" IPR, 5,530,890 CBM/PTAB, and Moore/TPL portfolio proceedings), which returned no AIA case number naming this patent. I cannot rule out an unindexed or sealed proceeding; the free, authoritative check is the PTAB E2E / Patent Center "PTAB proceedings" tab and the PTAB Decisions site. Treat "zero" as verified-negative-as-of-today, not as an absolute.

Closest matches I checked and ruled out (do not confuse these with '890 proceedings)

Family litigation data in the ODP block (district court and CAFC case links, and U.S. Supreme Court No. 19‑324) is litigation, not PTAB activity.

What actually happened to this patent (and why it matters more than a PTAB record)

Because you have no PTAB FWD to read, the operative validity/admissibility events are these — flagged by source and confidence:

1. Ex parte reexamination narrowed the claims. Assertion-side and court records confirm the '890 emerged from reexamination with amended claims. In Acer, Inc. v. Technology Properties Ltd., N.D. Cal. Case No. 5:08‑cv‑00877 JF/HRL (order dated 2011‑05‑13), the court recorded that the parties did not oppose "the substitution of claims 1 and 2 of the `890 patent by replacement claims 11 and 12" (and Barco did not oppose substitution of claim 1 by claim 11). Secondary-source summaries of the same order state that TPL served its amended '890 contentions on the day the reexamination certificate issued (reported 2011; I did not verify the exact certificate date). → If a demand letter cites claims 1–2 of the '890, those original claim numbers were replaced; the live scope is the replacement claims.

2. Intervening rights defeated pre‑certificate damages. In HTC Corp. v. Technology Properties Ltd., N.D. Cal. (2013, Judge Grewal), the court granted HTC partial summary judgment of non-infringement of the '890 patent on the ground that the reexamination amendments substantively narrowed the claims, entitling HTC to intervening rights precluding liability for infringement before the reexamination certificate issued. (Sourced from a third-party case summary of the ruling — verify against the slip order before relying on it in a brief.)

3. Expiration. Per the ODP/Google Patents record: anticipated expiration 2013‑06‑25; status "Expired – Lifetime." For a party accused today, that caps exposure via 35 U.S.C. § 286 (six-year lookback before the complaint) and eliminates injunctive relief — TPL/Alliacense already conceded as much publicly once the sibling '749 patent lapsed.

4. Enforcement history and appeals. The ODP family data lists district-court campaigns (E.D. Tex. 2008: 2:08‑cv‑00226/00227/00228; N.D. Cal. 2012: 3:12‑cv‑03860 through 03881) and CAFC appeals 14‑1317, 16‑1306, 16‑1307, 16‑1309, 16‑1311, 18‑1439, 18‑1440, 18‑1441, 18‑1444, 18‑1445, plus U.S. Supreme Court No. 19‑324. Phoenix Digital Solutions' public reporting states it filed its cert petition on 2019‑09‑06 following a Federal Circuit decision, yielding "mixed results." I have not verified the specific holdings or dispositions of those appeals; treat the docket numbers as leads, not findings.

Strategic summary

Canceled vs. sustained vs. untested — in the AIA-trial sense, everything is untested. No claim of the '890 has been adjudicated by the PTAB, so there is no claim of 5,530,890 that is "canceled by the Board" and no claim that is "confirmed by the Board." The only dead claims are the original claims 1 and 2, which were replaced by reexamination claims 11 and 12; and even those were replaced, not canceled — which is itself a trap, because the replacement claims 11/12 are narrower by construction and carry the intervening-rights baggage described above. Any plaintiff asserting this patent must plead the post-reexamination claims, and any defendant must pull the reexamination file wrapper to fix the priority date (1989‑08‑03 prior-art date; this application filed 1995‑06‑07 as a division of Ser. No. 07/389,334, now US 5,440,749) and confirm the effective filing/priority chain.

Estoppel landscape: essentially empty, which cuts both ways. Because no IPR/PGR/CBM was filed, § 315(e)(2) estoppel never attached to anyone, and § 315(b) one-year time bars are irrelevant — no petition was ever filed. Practically, a defendant is not limited to a narrow prior-art "toolbox" by a prior petitioner's estoppel. Conversely, you cannot ride an existing petitioner's work: you would have to build your own petition from scratch (if you even want one — see below). The real bars to worry about are § 325(d) (the Office and any future tribunal will see the reexamination record), collateral estoppel / issue preclusion from any final district-court or CAFC judgment involving the same claims, and the intervening rights doctrine already proven out by HTC.

Pattern signals. No defensive aggregator (e.g., Unified Patents) IPR appears in this chain — the "890" hits in litigation data are TPL-side enforcement, not defensive filings. The challengers' weapon of choice was ex parte reexamination, not AIA trials, which is typical for a 1989-priority, pre-AIA patent that had already expired by the time IPRs became available. The patent owner (now the Moore Equinox Trust / Patriot Scientific / Technology Properties chain) was an aggressive appellant, litigating up to the Supreme Court (No. 19‑324), and TPL/Alliacense publicly stated the portfolio "generated mixed results."

Recommended next steps

• Do not budget for a PTAB-based defense on the assumption that the Board has already narrowed this patent. It hasn't touched it. If you want Board relief, you must file your own IPR — but weigh whether an expired patent with six-year, past-damages-only exposure justifies the cost of an IPR-plus-appeal, versus a district-court invalidity/non-infringement defense leveraging the reexamination record.
• Pull the reexamination file wrapper first. Confirm (a) the exact reexamination certificate date and its claim listing, (b) that original claims 1 and 2 were replaced by claims 11 and 12, and (c) the amendment language that gave HTC its intervening-rights partial SJ of non-infringement. If your demand letter cites claims 1, 2, or the pre-2011 claim language, that is a directly impeachable pleading.
• Verify the negative before relying on it. Check PTAB E2E and USPTO Patent Center → "PTAB proceedings" for US 5,530,890 (and for the sibling '749, '336, '584, and '148 patents, which saw the actual reexam fights). If a proceeding exists that ODP hasn't ingested, ping me with the case number and I'll add the claim-level outcome and CAFC disposition.
• Bound exposure by date. With expiration at 2013‑06‑25 and § 286's six-year lookback, establish the complaint service date and confirm no pre-complaint licensing notice revives longer damages; absent a preliminary injunction the "willful infringement" theory was already held insufficient as to the '890 by the 2013 N.D. Cal. ruling.
• Check the ownership/standing chain (MOORE, CHARLES H., TTE, UTD 03/21/2006 THE EQUINOX TRUST; Patriot Scientific; Technology Properties Limited; Phoenix Digital Solutions) — the 2019 cert petition and the Santa Clara County ownership dispute over the sibling '336 patent show this chain has been contested, and a standing gap is a cheap early defense.

Key sources: Google Patents record for US5530890A (expiration and family litigation links); CourtListener docket for Technology Properties Limited LLC v. Samsung Electronics Co., Ltd., 3:12‑cv‑03877; Acer, Inc. v. Technology Properties Ltd., N.D. Cal. No. 5:08‑cv‑00877 (2011‑05‑13 order on amended infringement contentions).

I'll cross-check the assignment record using the sources available to me before reconstructing the chain.

Let me attempt to pin down the reel/frame numbers and correspondents of record.

Let me make one more targeted attempt at reel/frame and correspondent data before finalizing.

US 5,530,890 — Ownership chain and NPE pattern analysis

Data-integrity note before the timeline. My available tooling for this task is a web-search tool; it does not expose the USPTO Patent Assignment Search fields (reel/frame, execution date, correspondent of record). I attempted four targeted searches for reel/frame numbers and correspondent names and none surfaced them. Google Patents' legal-events record — which is part of the authoritative full text supplied to me — gives the recording dates and parties but no reel/frame and no correspondent. I am therefore reporting the chain below without reel/frame citations and without correspondent names, and I am not inventing placeholders for them. Those two fields must be pulled directly at https://assignmentcenter.uspto.gov/ (or the mirrored search at https://assignment.uspto.gov/patent/index.html) before this chain is relied on for standing or ownership purposes. Verified record: https://patents.google.com/patent/[US5530890A](/patent/US5530890A)/en#legalEvents

Contradiction flagged. uspto.report (https://uspto.report/patent/grant/5,530,890) states the grant is "currently assigned to Nanotronics Corporation." That contradicts both the Google Patents assignment record and the litigation record (which describes TPL and Patriot as owners/co-owners). uspto.report is displaying stale original-assignee data and should not be relied on for current ownership. This does not contradict anything in the previously generated summary section; it is an external-source error.

Inventors

Caveats on employer — read carefully. I am not able to establish the inventors' employer at filing directly from the assignment record, and I flag this rather than assert it:

• No inventor→Nanotronics assignment appears anywhere in the recorded chain. The earliest recorded link is Nanotronics Corp. → Patriot Scientific (recorded 1996-10-28). If Moore and Fish were employees of Nanotronics, their rights would normally appear by way of an employment or assignment instrument — possibly recorded against the parent application 07/389,334 (now US 5,440,749) rather than against this divisional. Unclear; verify at the Assignment Center by searching the '749 and the parent application number.
• The public account (moderate confidence, not confirmed in the sources I retrieved) is that Moore and Fish designed the stack-based ShBoom microprocessor at Nanotronics, and that the design was later commercialized by Patriot Scientific as the PSC1000 / IGNITE family. Treat this as reported context, not a documentary finding.

Unusual pattern — yes, and it is a real one. Moore's personal interest did not flow to the original assignee. The record shows Moore → ITV Corporation, recorded 1997-09-08, i.e. Moore's interest left the chain barely a year after Nanotronics → Patriot (1996-10-28) and never re-joined the original assignee's line. That split in the chain is the direct cause of the 2004–2005 inventorship/ownership litigation between Patriot and the Moore/TPL side, and of the 2005 Stipulated Final Judgment (N.D. Cal. C-04-0618 JF) holding TPL "at least a co-owner" of the '890. This is a divergence-of-title pattern, not a classic pre-fire-sale inventor exodus — but the practical consequence (litigation over who owned the patent, followed by a forced co-ownership settlement) is the same.

Original assignee

Nanotronics Corp. — named as original assignee on the issued patent (issue date 1996-06-25).

• Primary line of business: semiconductor / microprocessor design. Nanotronics is the entity associated with the ShBoom stack-based processor that is the subject matter of this patent family. Moderate confidence — I could not verify Nanotronics' corporate registration, product shipment, or current status from the sources retrieved.
• Did it ship a product embodying the claims? The commercially visible product embodying this family was the PSC1000 / IGNITE line marketed by Patriot Scientific, and separately licensed processor cores (e.g., the PSC1000A core licensed to a Japanese electronics-industry association unit in Feb 1999, per the PTSC news archive surfaced in search). Whether Nanotronics itself shipped silicon is unclear.
• Current status: unclear. No evidence retrieved of dissolution, bankruptcy, or continued operation. Note that Nanotronics appears in the assignment record only as an assignor (1996) and is not listed among the current assignees on Google Patents.

Because Nanotronics transferred the patent approximately four months after issuance, its own status is largely academic — but the fact of a prompt post-issue transfer should be recorded.

Assignment timeline

Reel/frame and correspondent fields: not retrievable in this session. See the data-integrity note above. Where I record "recorded YYYY-MM-DD," that date comes from the Google Patents legal-events record and is a recording date, not an execution date — Google does not supply execution dates here. Do not treat these recording dates as execution dates.

1. execution date unknown / recorded 1996-10-28 — Reel/Frame not retrievable

   • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
   • Assignor: Nanotronics Corporation
   • Assignee: Patriot Scientific Corporation
   • Correspondent: not retrievable — cannot assess recurrence.
   • Context: Transfer from the original assignee to the commercializer, recorded ~4 months after issue; Patriot was Nanotronics' intended commercialization vehicle.

2. execution date unknown / recorded 1997-09-08 — Reel/Frame not retrievable

   • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST")
   • Assignor: Moore, Charles H. (inventor, individually)
   • Assignee: ITV Corporation
   • Correspondent: not retrievable.
   • Context: Divergence of title — the inventor's personal half-interest exits the original-assignee line and lands at an entity of Moore's own, ~1 year after link 1. This is the root of the later co-ownership dispute.

3. execution date unknown / recorded 2001-11-20 — Reel/Frame not retrievable

   • Conveyance: Security Interest ("SECURITY INTEREST (SEE DOCUMENT FOR DETAILS)")
   • Assignor: Patriot Scientific Corporation
   • Assignee: Swartz Private Equity, LLC
   • Correspondent: not retrievable.
   • Context: Securitization / financing collateral — Patriot pledges the portfolio against private-equity debt. Not a transfer of title.

4. execution date unknown / recorded 2002-05-23 — Reel/Frame not retrievable

   • Conveyance: Convertible Debenture ("(NOTE ARTICLE IV)")
   • Assignor: Patriot Scientific Corporation
   • Assignee: Lincoln Ventures, LLC
   • Correspondent: not retrievable.
   • Context: Securitization — same debt relationship as link 3, different lender.

5. execution date unknown / recorded 2002-08-05 — Reel/Frame not retrievable

   • Conveyance: Convertible Debenture
   • Assignor: Patriot Scientific Corporation
   • Assignee: Lincoln Ventures, LLC
   • Correspondent: not retrievable.
   • Context: Securitization — second Lincoln debenture recorded on the same patent three months later.

6. execution date unknown / recorded 2002-09-03 — Reel/Frame not retrievable

   • Conveyance: Amended Secured Promissory Note and Addendum
   • Assignor: Patriot Scientific Corporation
   • Assignee: Swartz Private Equity, LLC
   • Correspondent: not retrievable.
   • Context: Securitization — amendment and re-recording of the Swartz collateral.

7. execution date unknown / recorded 2003-02-14 — Reel/Frame not retrievable

   • Conveyance: Security Interest
   • Assignor: Patriot Scientific Corporation
   • Assignee: Knobbe, Martens, Olson & Bear, LLP
   • Correspondent: not retrievable. (Note: the assignee here is itself a law firm; whether it filed as its own correspondent cannot be confirmed.)
   • Context: Distress signal, not an ownership event — a major IP law firm taking a security interest in the patent portfolio strongly implies unpaid legal fees and a cash-constrained assignee in early 2003. This is the single most probative entry for Patriot's financial condition immediately before the 2003 transfer to TPL.

8. execution date unknown / recorded 2003-10-30 — Reel/Frame not retrievable

   • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST")
   • Assignors: ITV Corporation and Moore, Charles H.
   • Assignee: Technology Properties Limited
   • Correspondent: not retrievable.
   • Context: Transfer-to-asserter / consolidation — TPL assembles the Moore-side half-interest. Combined with Patriot's retained half, the '890 becomes jointly owned, the structure that lasted through the entire 2006–2013 assertion campaign. Recorded ~8 months after link 7.

9. execution date unknown / recorded 2005-08-08 — Reel/Frame not retrievable

   • Conveyance: Termination of Security Interest (release)
   • Assignor: Knobbe, Marten, Olson & Bear, LLP (note: spelled "Marten" singular in the Google record — reported literally, not auto-corrected)
   • Assignee: Patriot Scientific Corporation
   • Correspondent: not retrievable.
   • Context: Lien release — clearing the 2003 law-firm collateral, coincident with the June 7, 2005 Master Agreement / Commercialization Agreement among Patriot, TPL and Moore that settled the inventorship litigation and installed Alliacense as exclusive licensing agent.

10. execution date unknown / recorded 2009-03-24 — Reel/Frame not retrievable

    • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST")
    • Assignor: Moore, Charles H.
    • Assignee: Moore, Charles H., TTE, UTD 03/21/2006 The Equinox Trust
    • Correspondent: not retrievable.
    • Context: Estate planning / intra-personal trust transfer, not an NPE transfer. Note the three-year lag: the trust is dated 03/21/2006, the recording is 03/24/2009 — recorded after the Barco action (filed 2008-12-01) and the TPL counterclaims (2009-02-17) had already begun. It transfers only whatever residual interest Moore still held after the 2003 ITV/Moore→TPL assignment; the extent of that residual interest is unclear and worth confirming, because the Google Patents "current assignee" list still carries the Equinox Trust alongside Patriot and TPL.

11. execution date unknown / recorded 2012-02-10 — Reel/Frame not retrievable

    • Conveyance: Release by Secured Party
    • Assignor: Swartz Private Equity, LLC
    • Assignee: Patriot Scientific Corporation
    • Correspondent: not retrievable.
    • Context: Title cleanup ahead of the 2012 assertion wave — see signal 5, below.

12. execution date unknown / recorded 2012-02-10 — Reel/Frame not retrievable

    • Conveyance: Release by Secured Party
    • Assignor: Lincoln Ventures, LLC
    • Assignee: Patriot Scientific Corporation
    • Correspondent: not retrievable.
    • Context: Title cleanup, recorded the same day as link 11, retiring the 2001–2002 securitization liens.

No assignment to Phoenix Digital Solutions LLC is recorded on this patent, despite PDS appearing as a co-plaintiff with TPL and Patriot in the July 24, 2012 N.D. Cal. complaints and the August 24, 2012 ITC action. That is consistent with PDS holding assertion/licensing rights by agreement (the 2005 joint-venture structure) rather than title. Flagged as an open item — confirm by searching the Assignment Center for the '890 and for PDS as assignee.

Timeline diagram

timeline
    title Ownership of US 5530890
    1989 : Priority date Aug 3
    1996 : Issued Jun 25 to Nanotronics Corp
         : Assigned to Patriot Scientific Corp
    1997 : Moore interest assigned to ITV Corp
    2001 : Security interest to Swartz Private Equity
    2002 : Security interests to Lincoln Ventures
         : Amended note to Swartz Private Equity
    2003 : Law firm security interest recorded
         : Moore and ITV interest to TPL
    2005 : Law firm lien terminated
    2009 : Moore interest to Equinox Trust
    2012 : Swartz and Lincoln liens released
         : ITC and District Court suits filed
    2013 : Patent expires Jun 25

NPE / troll-pattern signals

Reminder: reel/frame citations are unavailable in this session, so each call below is anchored to recording dates and event types from the legal-events record plus the litigation record. Reel/frame must be added at the Assignment Center for a fully citable version.

1. Shell-entity transfer — PRESENT (qualified).
The patent did not move to a classic anonymous Delaware/Texas single-purpose LLC with a registered-agent address. What it did do is move, at 2003-10-30, from the inventor's holding vehicle (ITV Corporation) into Technology Properties Limited, which the N.D. Cal. court described as a privately held entity whose licensing arm, Alliacense Limited, licenses the patents "on behalf of TPL and Patriot" (Barco NV v. Patriot Scientific Corp., N.D. Cal. No. C08-5398-JF; Acer, Inc. v. Technology Properties Ltd., N.D. Cal. No. 5:08-cv-00877). TPL shipped no product. The evidence for licensing-only status is the court record and the absence of any TPL product, not the entity's name — which is the correct basis for the call. Marked qualified rather than outright present because TPL was a pre-existing joint-venture partner of Patriot, not a purpose-built shell.

2. Known asserter in the chain — PRESENT.
Technology Properties Limited (assignee of record from 2003-10-30) and Patriot Scientific Corporation are documented high-volume patent asserters; Alliacense and Phoenix Digital Solutions are their licensing/assertion vehicles. Corroboration: the Stanford NPE litigation database classifies the 2012 Technology Properties Ltd. LLC et al v. LG Electronics action (N.D. Cal. 3:12-cv-03880, which names the '890) with "NPE Status: Non Practicing Entity" (https://npe.law.stanford.edu/case/153010). The '890 was asserted by TPL/Patriot against HTC (E.D. Tex. 2:08-cv-226, filed 2008-06-04), Barco (counterclaim 2009-02-17), Sirius XM (declaratory action 2009), and Amazon (N.D. Cal./ITC, July 2012). None of TPL, Alliacense, or Phoenix Digital Solutions matches the enumerated lists in the task prompt (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg) — but they are independently documented asserters via Unified Patents / Stanford / RPX-tracked dockets, which satisfies the signal.

3. Repeat correspondent across the chain — UNCLEAR. Correspondent-of-record data was not retrievable. This is the most important unresolved field in this analysis, because a single recurring recording attorney across links 3–12 (or a recurrence of the 2003 TPL assignment's correspondent on the other MMP patents) would convert this from "unclear" to a concrete finding. Recommend pulling correspondent for every entry at the Assignment Center and diffing against the other MMP patents ('749, '336, '148, '584, '915, '703).

4. Cascading transfers through chained LLCs in <24 months — NOT PRESENT.
There is no LLC cascade. What exists instead is a financing-distress cluster: four security-interest filings in roughly 15 months (2001-11-20 Swartz; 2002-05-23 and 2002-08-05 Lincoln; 2002-09-03 Swartz), followed by a law-firm security interest (2003-02-14, Knobbe Martens) and then the TPL assignment eight months later (2003-10-30). That is a distressed-seller pattern, not a shell-entity cascade. The single true ownership transfer in thirteen years is the 2003 TPL assignment.

5. Pre-litigation transfer — PRESENT, in the specific form of a title-record cleanup.
No ownership assignment falls within six months of the first '890 suit (filed 2008-06-04); the nearest prior ownership event is 2003-10-30. However — and this is the concrete finding — both securitization liens (Swartz and Lincoln) were released on the same day, 2012-02-10, which is 5.5 months before the coordinated filing wave of 2012-07-24 (N.D. Cal. complaints against LG, Amazon and others) and approximately 6.5 months before the ITC complaint of 2012-08-24. Cleaning the chain of title immediately before a coordinated assertion campaign is the classic purpose of that maneuver. Marked present with the qualification that it is a lien release, not an ownership transfer.

6. Bankruptcy fire-sale — NOT PRESENT. No Chapter 7 or Chapter 11 proceeding involving Nanotronics, Patriot, ITV, or TPL appears in the record, and no judicial sale of the '890 was found. Patriot's 2001–2003 distress manifested as secured private-equity debt and a law-firm lien, not bankruptcy. Absence of evidence is stated as such.

7. Privateering — PRESENT.
The structure from 2003-10-30 onward is a hybrid privateering arrangement: an entity with genuine products (Patriot, which commercialized the PSC1000/IGNITE and licensed cores) retained a half-interest while a pure licensing entity (TPL) held the other half, and TPL's wholly owned licensing arm (Alliacense) ran the demand-letter and litigation program "on behalf of TPL and Patriot" (N.D. Cal. No. C08-5398-JF). By the time of the 2008–2013 campaigns, Patriot itself had repositioned as an IP licensing company — its June 2005 press material describes it as having moved from "that little guy who's suing all the big guys" to commercializing and licensing its portfolio. The economic substance is an operating-era portfolio being asserted against the industry by a dedicated licensing vehicle.

8. Defensive aggregator — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. No such entity appears as assignee at any link. The patent was instead neutralized by expiry: anticipated expiration 2013-06-25, consistent with the Google Patents status "Expired – Lifetime," and the previously generated section's note that Patriot's SEC filings describe the MMP patents as no longer enforceable following the denial of certiorari in No. 19-324 (2019-11-04). Expiry is not the defensive-aggregator signal — do not conflate the two.

Verdict

NPE — high confidence.

Justification. Two independent strong signals plus two supporting ones, all grounded in dated record entries rather than naming: (i) the 2003-10-30 assignment placing the Moore/ITV half-interest in Technology Properties Limited, an entity with no products whose licensing arm Alliacense was found by the N.D. Cal. court to license the patents "on behalf of TPL and Patriot"; (ii) Technology Properties / Patriot / Alliacense / Phoenix Digital Solutions are documented high-frequency asserters, and the Stanford NPE database classifies the '890 case (N.D. Cal. 3:12-cv-03880) as "Non Practicing Entity"; supported by (iii) the 2012-02-10 same-day release of the Swartz and Lincoln liens 5.5 months before the 2012-07-24 and 2012-08-24 assertion wave; and (iv) the privateering structure created by the 2005 Master Agreement and Commercialization Agreement. The one material gap is signal 3 (repeat correspondent), which is unresolved because reel/frame and correspondent fields were not retrievable here — I flag rather than fill that gap. Note also that the patent expired 2013-06-25, so the verdict describes the historical chain; there is no presently assertable right.

Verify and complete at: https://assignmentcenter.uspto.gov/ (search patent number 5530890) and the mirror https://assignment.uspto.gov/patent/index.html — retrieve reel/frame, execution date, and correspondent of record for each of the twelve entries above, then re-run the signal-3 test by diffing correspondents across US 5,440,749, US 5,809,336, US 5,784,584 and US 6,598,148.

I'll research the prior art cited against US 5,530,890. Let me run several targeted searches.

Prior-Art Analysis — US 5,530,890 ("High performance, low cost microprocessor")

1. Retrieval status: an explicit failure disclosure

I was not able to retrieve the (56) "References Cited" list for US 5,530,890 from the sources available to me. I ran targeted searches against the Google Patents record (https://patents.google.com/patent/US5530890A/en), the sibling family member, and the reexamination/litigation document trail. The results returned only:

• Google Patents' algorithmic "prior art keywords" — microprocessor, stack, register, instruction, memory. These are machine-generated subject tags, not citations.
• The bibliographic/litigation/classification record — no front-page citation list.
• The Espacenet claims page for US 5,440,749 (the parent), not for the '890.
• Unrelated search reports for other patents (e.g., US 8,764,326; WO 2009/096871; WO 2008/082591) whose "References Cited" sections merely happened to contain the digit string.

The authoritative full text supplied to me is truncated before the claims section and before the (56) references-cited section. So this is not a case where I can rank references I can see — I cannot see them at all. Per my operating rules, I will not fabricate a citation table, publication dates, or § 102 mappings for references I have not verified.

The table you asked for — full citation, publication/filing date, brief description, and anticipating claim(s) for each patent citation — cannot be produced honestly from what I have. Below is (a) what I can ground, (b) an element-by-element § 102 exposure map for the operative claims, and (c) exactly where the authoritative list is obtainable.

2. Prior art identified inside the four corners of the '890 specification

The specification's "Description of the Prior Art" and body text name these references/systems. These are the closest thing to citations I can ground in the authoritative text, and each is tied to the claim feature the patent uses it to distinguish over.

§ 102 bottom line on these

None of the references named in the specification, standing alone, discloses all elements of claim 11 (two CPUs on one die + ALU fed by top-two-stack entries + loop-counter/decrementer + stack pointer/return stack pointer/mode register/instruction register + X/Y/PC address registers + incrementer + DMA CPU feeding the same memory controller). Each is, at most, a § 102 or § 103 reference against one limitation:

• SRAM-buffered DRAM hierarchies → against the bus-multiplexing and multi-level-stack claims, but they teach toward SRAM, not the claimed direct-DRAM arrangement.
• Conventional DMA controllers → against the DMA-fetch claim, but they require main-CPU involvement, which the claim negates.
• PDP-8 / NOVA → against a one-instruction-skip limitation only; they do not disclose the 4-byte instruction register or the microinstruction counter reset.
• HP stack calculators → against the bare stack concept, not the ALU-coupled top-two-register structure.

3. The reexamination prior art — the highest-value gap

Prior-section note (carried forward as authoritative): Reexamination request 90/009,388, filed January 16, 2009, resulted in certificate US 5,530,890 C1, with claims 1–4 cancelled, claims 5–10 confirmed, and new claims 11–20 added. That reexamination is where substantive prior art was actually applied against this patent, and the file history is the single most probative document for "the most relevant prior art for US 5530890."

I did not retrieve that file's prior-art citations, and I will not guess at them. Everything below in § 3 is off-limits to me right now. The third-party requester's §§ (i)(A)–(C) submissions are what you actually want.

4. Family-adjacent document retrieved (NOT prior art — flagged to avoid a § 102 error)

I did retrieve verbatim claim text for US 5,440,749 ("High performance, low cost microprocessor architecture," issued 1995-08-08) via Espacenet:

Claim 1 — "A microprocessor system, comprising a central processing unit integrated circuit, a memory extend [sic] of said central processing unit integrated circuit, a bus connecting said central processing unit integrated circuit to said memory, and means connected to said bus for fetching instructions … configured and connected to fetch multiple sequential instructions from said memory in parallel and supply the multiple sequential instructions to said central processing unit integrated circuit during a single memory cycle, said bus having a width at least equal to a number of bits in each of the instructions times a number of the instructions fetched in parallel, said central processing unit including an arithmetic logic unit and a first push down stack connected to said arithmetic logic unit …"

Claim 9 — the CPU + DRAM + "multiplexing means … to provide multiplexed row addresses, column addresses and data on said bus" combination, combined with the parallel multiple-instruction fetch and the push-down-stack-fed ALU.

⚠️ Do not treat US 5,440,749 as prior art against US 5,530,890. The '890 is a division of application 07/389,334 (filed Aug. 3, 1989), from which the '749 also issued. They share the same priority date and the same inventors. The '749 is a family member, not "by another" for § 102(e) purposes, and it is not prior art at all. I flag this because the '749's claim text superficially reads like anticipation of the '890's cancelled claims 1–4 and is likely to be miscited as such by automated tools.

Useful cross-reference though: the '749 claim text is the best available evidence for the content of the '890's cancelled original claims 1–4, which the earlier section of this analysis could only infer. The '749 claim 9's "multiplexed row addresses, column addresses and data on said bus" wording corroborates the earlier inference about the '890's original claim 1.

5. § 102 exposure map for the operative claim set (claims 5–20)

This is the framework you need regardless of which specific references the file wrapper names. Each row is a limitation in certificate claim 11; the right column is the type of single reference that would have to disclose it for a § 102 anticipation.

A reference anticipating claim 11 must hit every row. Realistically, the meaningful § 102 candidates are contemporaneous stack/zero-operand microprocessor designs (e.g., Forth-oriented hardware stack CPUs of the mid-1980s) and transputer-class multiprocessor chips — but I have not verified which, if any, were cited in this patent's file, and I decline to name them as "citations."

6. Where to obtain the authoritative citation list (do this before relying on anything)

1. USPTO Patent Center / Public PAIR, application 08/480,206 → "References Cited" and "Foreign References" tabs, plus the "Fee(s)"/"Documents" tabs.
2. Reexamination file for 90/009,388 — the third-party requester's prior-art submissions and the Examiner's § 102/§ 103 rejections. This is the highest-value document and is where the substantive dispute over this patent's validity lives.
3. PTOL-892 / reexamination certificate US 5,530,890 C1 in the Official Gazette — states exactly which claims were cancelled, confirmed, and added (consistent with the prior section: 1–4 cancelled, 5–10 confirmed, 11–20 added).
4. Global Dossier / Espacenet — for the foreign search reports on the 07/389,334 family, which frequently cite art not cited by the US examiner.
5. The 2012–2018 district court and CAFC briefs (e.g., CAFC 14-1317, 16-1306/-1307/-1309/-1311, 18-1439/-1440/-1441/-1444/-1445) — invalidity contentions there name the art actually asserted, which is often different from the examiner-cited art.

7. Confidence and contradictions flagged

• High confidence: the specification's own prior-art discussion (all quotes above are from the supplied authoritative text); the bibliographic data; the reexamination outcome (1–4 cancelled, 5–10 confirmed, 11–20 added); the expiration on 2013-06-25.
• Zero confidence / not retrieved: the identity of the examiner-cited U.S. and foreign patent references on the '890's face, and the prior art of record in reexamination 90/009,388. I have deliberately not invented them.
• Contradiction flagged: this task's header says "Current Date: April 26, 2026," while the operating context and the page-fetch timestamp say 2026-09-30. I have not reconciled these; if the April date governs, the "no 2026 CAFC activity" finding in the prior section still stands on its own terms but should be re-run against that date.
• Identifier discipline: "Intel 8960" is reproduced literally as it appears in the patent. I have not silently corrected it to Intel i860/i960. Likewise "US 5,440,749," "90/009,388," and "07/389,334" are used as printed.
• Caution against a foreseeable error: do not cite US 5,440,749 against US 5,530,890 as prior art. Same family, same priority, same inventors.

If you can supply the (56) list, the reexamination file history, or a Patent Center export, I can complete the per-reference citation table with dates, descriptions, and § 102 claim mappings in one pass.

I'll gather the prior-art references tied to this patent before analyzing. Let me run several searches in parallel.

The search results gave me the certificate text and a key lead (the May '948 reference). Let me dig for the actual prior-art list on the patent page and the reexamination record.

Obviousness Analysis — US 5,530,890 ("High Performance, Low Cost Microprocessor") under 35 U.S.C. § 103

0. Evidence base, and an important limitation (read first)

I was asked to work "from the Prior Art section of this page." I have to be candid about what I could and could not retrieve:

• The full text supplied to me does not contain the "References Cited," "Similar Documents," or "Cited By" listings of the Google Patents page. It is truncated immediately after the claim-summary material and the paragraph beginning "The central processing uni…".
• My searches did not return the verbatim face-of-patent reference list for the '890. The only "prior art" metadata visible in the supplied page is Google's auto-generated keyword string: "microprocessor, stack, register, instruction, memory," and the "Prior art date 1989-08-03."
• Therefore the reference list below is reconstructed from four groundable sources, not from the patent's own citation list:

1. Admitted prior art in the '890 specification's BACKGROUND OF THE INVENTION (these are admissions usable as prior art under MPEP § 2144.03 / In re Fout).
2. The reexamination record of this patent (Reexam 90/009,388, Certificate C1), which I did recover — specifically the May reference, U.S. Pat. No. 4,758,948.
3. The sibling-patent reexamination (US 5,809,336, same 1989-08-03 parent family), whose request names Ledzius, Mostek, Guttag, Thaden, Hitachi, Boney and Brenig.
4. Well-known art as of the August 3, 1989 priority date, which I flag as "general knowledge" rather than "of record."

I state plainly: I could not verify the exhaustive list of references actually cited on the '890. Any practitioner relying on this should re-pull the citation list and the 90/009,388 file wrapper.

Flagged contradiction with the prior generated section: that section listed among the "(confirmed)" claim subject matter the "ring-counter, process-tracking variable-speed system clock paired with an independent crystal clock." That subject matter is the stated title and core of the sibling patent US 5,809,336 — "High Performance Microprocessor Having Variable Speed System Clock" (confirmed in the PubPat reexamination request, which describes the '336 as "directed to methods for clocking microcomputers"). Both the '890 and '336 are divisions of 07/389,334. It is therefore likely that the variable-speed-clock claims live in the '336, not in the '890's claims 5–10. The '890 discloses the dual-clock scheme (its SUMMARY OF THE INVENTION has a "ring counter variable speed system clock" aspect), but disclosure ≠ claimed subject matter. Treat the prior section's clock-claim inference as unverified and probably misattributed.

Otherwise the prior section's bibliographic and reexamination facts (claims 1–4 cancelled; 5–10 confirmed; 11–20 added; expiration 2013-06-25) are consistent with everything I retrieved and I adopt them.

1. Governing law

• Pre-AIA § 103 applies. Priority is August 3, 1989, well before the AIA (March 16, 2013). The obviousness inquiry is the classic one.
• Graham v. John Deere Co., 383 U.S. 1 (1966): (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) secondary considerations.
• KSR Int'l Co. v. Teleflex Inc., 551 U.S. 398 (2007): a combination is obvious where the elements were known in the art and combined to yield predictable results; the "motivation to combine" may come from "the knowledge of a person of ordinary skill," market demand, design incentives, and the "finite number of identified, predictable solutions" facing the designer.
• Claim set to be tested: the live set is claims 5–20 (5–10 confirmed; 11–20 added in reexamination; 1–4 cancelled). Under § 282 the reexamined claims carry a presumption of validity, but Applied Materials v. ASM and progeny hold that reexamination does not strengthen that presumption — relevant because the "confirmed" claims here survived only a patents-and-printed-publications search in reexam, which is a materially narrower inquiry than a full § 103 trial record.

2. Level of ordinary skill in the art (POSITA), as of Aug. 1989

A POSITA would be a microprocessor/microcomputer architect with a B.S. in EE/CS plus ~2–4 years (or an M.S. plus ~1–2 years) of chip-level CPU design, conversant with: datapath/ALU design; stack-machine and register-window architectures; DRAM row/column (RAS/CAS) timing and memory controllers; DMA and I/O-processor design; RISC design (e.g., SPARC, i960); variable-length instruction encoding; and standard arithmetic circuits (shift-add multipliers, LFSRs). This is a high skill level — which cuts against patentability, because most of the '890's constituent pieces are textbook at that level and only the assemblage is new.

3. Scope and content of the prior art

3(a) Admitted prior art (from the '890's own BACKGROUND — strongest, unimpeachable)

3(b) Art of record in the reexamination of this patent

3(c) Sibling-family reexamination art (US 5,809,336 request)

Ledzius; Mostek; Guttag; Thaden; Hitachi; Boney; Brenig — each applied in "X in view of Y" obviousness combinations against the same family's stack/processor architecture. I did not retrieve their bibliographic details, so I cite them as family-relevant art only, with that caveat.

3(d) General knowledge as of Aug. 1989 (flagged as such)

• Intel 8089 I/O Processor (1979) — a dedicated, on-chip I/O processor with its own instruction set that performs DMA and shares the system bus with an 8086/8088. This is arguably the single most damaging non-admitted reference against claim 11's "separate direct memory access central processing unit… providing inputs to said memory controller."
• Novix NC4000 (1985–86) and Harris RTX 2000 (1988) — the inventor Moore's own Forth stack processors, with on-chip data stack and return stack, single-cycle stack operations, and direct execution of high-level primitives.
• IBM System/360 Model 91 instruction stack / loop buffer (and the general instruction-prefetch/queue art) — fetching ahead and executing short loops from a buffer.
• LFSR / CRC polynomial generators — polynomial generation by iteration of shift + conditional XOR against feedback terms.
• Bit-serial (shift-add) multipliers — Booth and bit-serial multiply; LSB-first accumulation.
• Auto-increment / auto-decrement index registers — PDP-11, 68000, etc.
• Register windows / stack caches — Berkeley RISC, Lisp-machine memory hierarchies.

4. Claim-by-claim differences and rejection theories

4.1 Independent claim 11 (verbatim from Certificate C1) — the FIG. 2 architecture

Claim 11 is a structural recitation of the FIG. 2 block diagram: two CPUs on one die; ALU fed by the top two stack entries; top-of-stack on the internal data bus; that bus tied to a loop counter + decrementer, stack pointer, return-stack pointer, mode register, instruction register, memory controller, and X/Y/program-counter registers; an internal address bus with an incrementer; the DMA CPU feeding the same memory controller.

Element-by-element, every element is separately known:

• Two CPUs / CPU + DMA engine on one die — admitted in the '890's own background ("DMA controllers… may be located on the microprocessor integrated circuit"); generalized by the Intel 8089 (a full I/O processor with its own ISA).
• ALU fed by the top two items of a push-down stack; result to top-of-stack — the defining datapath of a stack machine; May '948 teaches the push-down stack; NC4000/RTX 2000 teach the data-stack/return-stack pair.
• Loop counter + decrementer — ubiquitous; the '890 itself admits skip/loop control in the PDP-8/NOVA.
• Stack pointer "pointing into said first push down stack" — this phrase is the entire point of novelty that saved the claim. But pointing into the stack is the inherent, definitional function of a stack pointer. Under KSR's "a court must ask whether the improvement is more than the predictable use of prior-art elements according to their established functions," the amendment adds nothing inventive. The examiner's objection to claim 1 was a definiteness objection dressed as a § 102 point — not evidence of nonobviousness.
• X, Y, program counter → internal address bus → memory controller + incrementer — standard index-register / address-generation-unit structure with auto-increment (PDP-11, 68000).
• Memory controller with address/data bus and control lines to RAM — the ordinary definition of a memory controller.

§ 103 conclusion (claim 11): highly likely obvious as a combination of May '948 (push-down stack + ALU) in view of an I/O-processor-on-chip reference (8089-type, or the admitted on-chip DMA controllers) and a conventional address-generation/memory-controller reference. Motivation: the '890's own stated object — "a microprocessor with a reduced pin count and cost," and "DMA [that] does not require use of the main CPU." Result: predictable.

4.2 Claims 5–10 (confirmed) — inferred groupings

Because they survived reexamination and cannot have depended on the cancelled claims 1–4, claims 5–10 are most plausibly independent claims. The SUMMARY OF THE INVENTION supports these likely groupings, each of which is addressed by a distinct prior-art combination below (all hedged pending verbatim claim text):

(A) CPU + DRAM + bus with multiplexing means placing row addresses, column addresses AND data on the bus. → Ground B.
(B) Means for fetching multiple sequential instructions in a single memory cycle (with assembling instructions from PROM into DRAM). → Ground C.
(C) DMA unit fetching both main-CPU instructions and its own instructions on the shared bus. → Ground A.
(D) ALU + first push-down stack + register file / second push-down stack (return stack). → Ground D.
(E) Output-enable sense + driver feedback to adapt memory bus timing. → Ground H.
(F) Multi-level stack: on-chip latches + on-chip RAM + off-chip RAM with separate pointers. → Ground E.

4.3 Claims 12–20 (added) — most likely dependent on claim 11

These are consistent with the ALU mode descriptions in the specification:

• Polynomial-generation mode (A register, C feedback-terms register, B starting-polynomial register, down counter) → Ground F (LFSR art).
• Fast/serial multiply mode (A result register, C multiplicand, B bit-reversed multiplier, down counter) → Ground F (bit-serial multiply art).
• SKIP / MICROLOOP / variable-width operands → Ground G.

5. The combinations, with motivation (KSR rationales)

Ground A — Claim 11, and claim (C): May '948 + on-chip DMA/I/O processor art (Intel 8089-type; or the admitted on-chip DMA controllers).

Rationale (KSR factor 1 & 3): Combining prior-art elements to yield a predictable result — a known stack/ALU coprocessor architecture (May) with a known technique (a second, dedicated on-chip processor that fetches its own instructions to perform I/O) to improve a known device (a microprocessor) in the same way. Motivation is explicit in the patent's own stated objects (offload I/O from the main CPU; reduce main-CPU involvement in DMA). Result is predictable.

Ground B — Claims 5–10 group (A): Admitted 68000/8086 multiplexed-bus art + standard DRAM RAS/CAS addressing (general knowledge).

Rationale (KSR factor 5 — "finite number of identified, predictable solutions"): DRAM inherently multiplexes addressing (row address, then column address, on the same pins); multiplexed address/data buses were standard in the admitted 68000/8086 art. To place row address, column address, and data on one bus is simply the union of two known multiplexing techniques, chosen to reach the patent's stated goal of reduced pin count and cost (44 pins vs. ~200). Predictable, and motivated by the admitted cost pressure of using DRAM instead of SRAM.

Ground C — Claims 5–10 group (B): Wide-bus instruction fetch (a function of bus width) + IBM 360/91 instruction-stack/loop-buffer prefetch art + ROM-to-RAM boot-loaders (general knowledge).

Rationale (KSR factors 3 & 6): Fetching 4 bytes per cycle from a 32-bit bus is a natural use of the bus width; prefetch/loop-buffer to hide fetch latency was known (360/91). Assembling PROM bytes and writing 32-bit words to DRAM is a routine boot/shadow-load. Motivation is the very problem the specification names — "the Von Neumann bottleneck of the speed of getting the next instruction." Predictable result.

Ground D — Claims 5–10 group (D): May '948 + Novix NC4000 / Harris RTX 2000 (on-chip data stack + return stack) + register-window art (Berkeley RISC / SPARC).

Rationale (KSR factors 1 & 4): May supplies a push-down stack ALU; the NC4000/RTX 2000 (the inventor's own earlier chips, public 1985–88 and thus § 102(b)-type art against a 1989 priority) supplies the paired data/return stacks and single-cycle stack ops; register-window art supplies on-chip register files. The claimed combination is a predictable assembly of known stack-machine and register-file elements.

Ground E — Claims 5–10 group (F): Memory-hierarchy / cache art + stack-cache art + register spilling.

Rationale (KSR factors 3 & 7): Placing the fastest memory nearest the ALU and spilling to slower memory is the defining principle of a memory hierarchy and of register windows. The patent's own admission ("latch stack is the fastest… on-chip RAM is next… off-chip RAM is slowest") is the known hierarchy rule. Three pointers for three levels is the ordinary consequence of three storage levels.

Ground F — Claims 12–20 (polynomial & fast-multiply ALU modes): LFSR/CRC generator art + bit-serial shift-add multiplier art.

Rationale (KSR factors 1 & 3): Generating a polynomial by iterating shift-right with a conditional XOR against feedback terms is textbook LFSR/CRC construction; the '890 adds only a down counter to bound the iterations. The "fast multiply" is a standard shift-and-add serial multiplier with a bit-reversed (LSB-first) multiplier register. Both are "known technique[s] applied to a known device (the ALU) to yield predictable results" — an express KSR rationale. The '890's own justification ("generate polynomials at high speed without external hardware") is a classic design-efficiency motivation.

Ground G — Claims 12–20 (SKIP / MICROLOOP / variable width): Admitted PDP-8 / NOVA skip + 360/91 loop buffer + variable-length instruction art (x86/68000, admitted).

Rationale (KSR factors 3 & 5): Up to three skips within a 4-byte group is a predictable extension of the admitted single-instruction skip, once the fetch width is 4 bytes. A "microloop" entirely within the fetched instruction group is a loop buffer by another name (360/91). Sharing one opcode across 8/16/24-bit operands is variable-length encoding (x86/68000). Predictable, and motivated by the patent's repeated theme of "very fast code."

Ground H — Claims 5–10 group (E) — the hardest claim to invalidate: Output-enable sense/driver feedback to adapt memory-bus timing to load. No reference in my retrieved material squarely teaches measuring OE rise time to generate an internal READY. The closest general art is self-timed/adaptive buses and wait-state generation. I would not predict success on this ground on the record available to me, and I flag it as the most likely candidate for surviving § 103.

6. Secondary considerations / rebuttals the patent owner will assert

1. Presumption of validity + reexamination survival. Claims 5–10 were confirmed and 11–20 allowed over the May reference. Rebuttal: reexam is limited to patents/printed publications and to the examiner's search; survival is not an obviousness holding on a full trial record, and Applied Materials v. ASM prevents the certificate from strengthening the presumption.
2. Unexpected performance ("20 MIPS for $20"; 44-pin package). Rebuttal: the specification attributes the speed to reduced gate count and parallelism, both of which are the expected consequences of simplification and wide fetch — i.e., a predictable result of the claimed combination, not an unpredictable one.
3. Copying / industry praise / licensing success. The MMP licensing campaign is evidence of value; but the patents were ultimately held "no longer enforceable" per Patriot Scientific's filings, which undercuts nexus arguments if the licensing reflected enforcement leverage rather than technical merit. (I have not verified the ground of unenforceability; do not assume it was § 103.)
4. Teaching away. A party could argue the art taught against a stack machine for high performance (HP vs. TI framing) — but the '890's own admission that the combined stack/register architecture was avoided only "due to inadequate understanding by computer designers," not due to technical impossibility, neutralizes a teaching-away defense. The applicant effectively admitted the combination was available and merely unrecognized.

7. Bottom line

• Claim 11 is the most vulnerable. Its sole post-reexam addition — "said stack pointer pointing into said first push down stack" — recites the definitional function of a stack pointer. Combined with May '948 (push-down stack + ALU) and an I/O-processor-on-chip reference (Intel 8089-type, or the '890's own admitted on-chip DMA controllers) plus conventional address-generation/memory-controller art, claim 11 is a strong § 103 candidate under KSR's "predictable use of prior-art elements according to their established functions."
• The multiplexed-bus, multi-instruction-fetch, and multi-level-stack groupings are the next most vulnerable, each reachable by pairing admitted art (68000/8086 multiplexing; 360/91 prefetch/loop buffer; cache hierarchy) with the patent's own stated cost/pin-count and von-Neumann-bottleneck motivations.
• The polynomial and fast-multiply dependent claims are weak, sitting squarely on textbook LFSR and bit-serial-multiplier art.
• The output-enable feedback claim (Ground H) is the strongest nonobviousness position and the one I would expect to survive on the record I could retrieve.

Confidence and caveats:

• High confidence in the legal framework, the admitted prior art, the May '948 ground, and the general-knowledge references (8089, NC4000/RTX 2000, 360/91, LFSR, bit-serial multiply) — though the general-knowledge items need to be reduced to specific, dated, authenticated references before use in a real proceeding.
• Low confidence in my inference of claim groupings 5–10 and 12–20, because the authoritative claim text was not in the material I received and I could not retrieve the patent's own reference list. Do not rely on these groupings without pulling the certificate and the 90/009,388 file wrapper.
• I re-flag the clock-claim misattribution in the earlier section (likely US 5,809,336, not the '890).