US 5440749

I'll search for current information on this patent, including any 2026 CAFC docket activity.

Let me run more targeted searches for 2026 litigation/docket activity.

Search scope and results

Important caveat up front: I could not retrieve the verbatim, numbered claim set for US 5,440,749 from the authoritative full text supplied to me (it contains the Abstract, Summary of the Invention, and Specification, but the claims section is not included). The claim overview below is therefore built from the Summary of the Invention aspects, which in this patent are the paragraphs that the independent claims were drafted from. I flag this as an inference rather than a verbatim reading.

CAFC 2026 dockets: I found no 2026 Court of Appeals for the Federal Circuit docket activity for US 5,440,749. The 2026 CAFC/SCOTUS material returned by search involved unrelated patents (e.g., Headwater Research v. Verizon, USCA No. 26-1884; the '637 patent appeal decided January 22, 2026; a 2026 cert. petition concerning US 7,679,637). None of these involve 5,440,749. I state this as a negative finding from the searches performed, not a guarantee of exhaustive coverage.

Identifier confusion warning: several search hits use "the '549 patent" to refer to US 7,162,549 (MCM Portfolio v. Hewlett-Packard, IPR2013-00278, Fed. Cir. 2015-1091). That is a different patent. I have not mixed it into the data below.

Bibliographic data — US 5,440,749 A

Family (relevant members): WO 1991002311 A1; AU 6067290 A; EP 0497772 A1/A4; JP H05502125 A / JP 2966085 B2; EP 0786730 A1/B1; DE 69033568 T2; US 5,530,890; US 5,604,915; US 5,659,703; US 5,784,584; US 6,598,148 B1; and US 5,809,336 (a division of application 07/389,334, issued September 15, 1998).

Known litigation history (Google Patents "family has litigation" listing): numerous N.D. Cal. cases (e.g., 5:08-cv-00884, 5:08-cv-00882, 5:08-cv-05398, 3:10-cv-00816, 4:12-cv-03879, 3:12-cv-03880 among others), E.D. Tex. (2:08-cv-00177, 2:08-cv-00172), E.D. Cal., S.D.N.Y. (1:09-cv-04083), and Federal Circuit appeals 14-1317, 16-1306, 16-1307, 16-1309, 16-1311, 18-1439, 18-1440, 18-1441, 18-1444, 18-1445, plus U.S. Supreme Court No. 19-324. The most commonly cited asserting vehicle was Technology Properties Limited LLC v. LG Electronics, Inc., 3:12-cv-03880 (N.D. Cal., filed July 24, 2012), which asserted 5,440,749 along with 5,530,890 and 5,809,336.

Abstract (verbatim, as published)

A microprocessor (50) includes a main central processing unit (CPU) (70) and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making up the microprocessor (50). The main CPU (70) has a first 16 deep push down stack (74) [sic "tack"], which has a top item register (76) and a next item register (78), respectively connected to provide inputs to an arithmetic logic unit (ALU) (80) by lines (82) and (84). An output of the ALU (80) is connected to the top item register at (82) is also connected by line (88) to an internal data bus (90). CPU (70) is pipeline free. The simplified CPU (70) requires fewer transistors to implement than pipelined architectures, yet produces performance which matches or exceeds existing techniques. The DMA CPU (72) provides inputs to the memory controller (118) on line (148). The memory controller (118) is connected to a RAM by address/data bus (150) and control lines (152). The DMA CPU (72) enables the CPU (70) to execute instructions four times faster than the RAM speed by fetching four instructions in a single memory cycle.

Plain-language overview of the disclosed independent aspects (claim-level summary)

The patent's Summary of the Invention is written as a series of numbered aspects, each of which corresponds to an independent claim family. In plain language:

1. CPU + DRAM + triple-multiplexed bus. A microprocessor system with a CPU, a DRAM, and a bus between them, where multiplexing circuitry puts row addresses, column addresses, and data onto the same physical bus lines. This is the pin-count reduction idea — the same I/O circuits serve three functions, which is why the part fits a 44-pin package.

2. Multiple-instruction fetch per memory cycle. Circuitry on the bus fetches several sequential instructions for the CPU in a single memory cycle (the patent describes four 8-bit instructions per 32-bit fetch). A variant covers the boot path: a PROM holds instructions, and fetch logic assembles multiple instructions from the PROM and writes them into the DRAM (the "PROM LOAD" / mode-0 DMA startup sequence). The point is to break the von Neumann bottleneck of fetching one instruction at a time.

3. Dedicated DMA processor on the bus. The system has a main CPU, a direct memory access processing unit, and a memory on a shared bus, where the DMA unit itself fetches instructions — both instructions for the main CPU and instructions for the DMA unit. This is the "CPU that does DMA" idea: DMA runs without consuming main-CPU cycles, with predictable response time.

4. Single-chip CPU + DRAM with a column latch as instruction cache. The memory is brought on-die, and the multiple-instruction fetch uses a DRAM column latch to hold the fetched instructions. Since selecting data already in the column latch is roughly six times faster than a random access, the column latch is repurposed as an instruction cache (128 × 8-bit instructions in the described embodiment).

5. Instruction register, sequencing counter, decoder, and SKIP / MICROLOOP. An instruction register holds the multi-instruction group; a counter drives a multiplexer that feeds the instructions out one at a time to a decoder. The decoder sends increment/reset control back to the counter. Two dependent behaviors are claimed: (a) in response to a SKIP instruction, the decoder resets the counter and signals the fetch logic to load the next group (discarding the remaining 1–3 instructions in the current group); and (b) with a loop counter present, in response to a MICROLOOP instruction the decoder resets the instruction counter and decrements the loop counter, re-executing the earlier instructions in the same group. A further variant covers variable-width operands (8/16/24-bit) where the decoder controls the counter and the counter's state selects which bytes of the operand are driven onto the address or data bus.

6. ALU with a push-down stack feeding a register file. An ALU whose two inputs are the top and next items of a push-down stack, with the ALU output written back to the top-of-stack location; the top-of-stack location also feeds (and is bidirectionally connected to) a register file, desirably itself implemented as a second push-down stack. This is the "implied addressing" idea — source and destination are implicit in stack position rather than encoded as explicit register addresses.

7. Adaptive memory timing via the output-enable line. A data processing system in which the microprocessor has a sensing circuit and a driver circuit on the OUTPUT ENABLE line shared with the memory. The sense circuit asserts an internal READY signal once the OE line reaches a predetermined electrical level (i.e., once it has risen far enough given the capacitive load of however many memory chips are attached), and the driver then issues the enable signal. Effectively the processor measures its own bus load and self-tunes memory cycle timing instead of using a fixed worst-case margin — fast with a small load, slower with a large one, with no designer intervention.

8. Ring-oscillator variable-speed system clock with a separate I/O clock. A CPU clocked by an on-die ring oscillator whose frequency tracks process, voltage, and temperature — so the CPU always runs at the fastest speed that particular die can support, never faster. An I/O interface is clocked by a second, independent clock (crystal-referenced) so that the external world stays synchronized, with handshake signals recoupling the two asynchronous domains. (Note: this aspect was pursued to issuance in divisional US 5,809,336, "High performance microprocessor having variable speed system clock."

9. Three-tier stack cache with cascaded stack pointers. A push-down stack built from a first plurality of elements as on-chip latches (fastest), a second plurality as on-chip RAM (intermediate), and a third plurality as off-chip RAM (slowest), with a separate pointer per tier. As items are popped and a tier empties, the pointers cooperate to move a block of items up from the next tier. The described embodiment: 4 latch locations, 16 on-chip RAM locations, then off-chip.

10. Polynomial generator in the ALU datapath. A result register (A) fed by a shifter from the ALU output, a starting-polynomial register (B) feeding a right shifter with its least-significant bit into the ALU, a feedback-terms register (C) into the ALU, and a down counter. On a polynomial instruction the ALU XORs A with C when the LSB of B is one and passes A unaltered when it is zero, iterating until the down counter completes — producing the polynomial in A. Intended for error correction, encryption, data compression, and fractal generation without external hardware.

11. Fast multiply in the ALU datapath. Structurally the same datapath: multiplier loaded bit-reversed into B, multiplicand into C, zero into A, and (multiplier width − 1) into the down counter. Each iteration adds A to C if the LSB of B is one, otherwise passes A through, then shifts A left and B right. The product lands in A. The emphasis is that scaling a 32-bit value by a small multiplier costs proportionally few cycles (8× faster for a 4-bit multiplier than 32×32).

Uncertainty / verification notes

• Claims: the exact independent-claim numbering and wording is not in the material I was given; the eleven aspects above are the Summary-of-Invention items and may or may not map 1:1 onto issued independent claims. Anyone relying on this for claim-charting should pull the issued claims from the USPTO PatentCenter or the patent PDF.
• Assignee chain of title is genuinely messy. The record shows transfers among Nanotronics Corp., the Fish Family Trust, Charles H. Moore, ITV Corporation, Patriot Scientific Corporation, Technology Properties Limited, and (for the trust interest, March 24, 2009) Moore as trustee of The Equinox Trust — with security interests to Swartz Private Equity, Lincoln Ventures, and Knobbe Martens. The 2004–2005 press record describes contemporaneous ownership and inventorship disputes between Patriot Scientific and TPL/Moore, including a Patriot claim that Russell H. Fish, III was the sole inventor of sibling patent 5,809,336 (EE Times, Nov. 23, 2004). Treat any single "assignee" field as a snapshot, not a title opinion.
• Expiry: the patent is recorded as Expired – Lifetime with an anticipated expiration of 2012-08-08. Note this is later than a bare 20-years-from-1989-08-03 term would give, consistent with term extension (35 U.S.C. § 154(b)) for the unusually long pendency. I have not independently verified the PTA calculation.
• Literal reading preserved: the specification as printed refers to the "Intel 8960" RISC microprocessor and the "SPARC" chip; I have reproduced those identifiers as they appear rather than substituting what I believe the intended part numbers were.

Bottom line on the 2026 docket question: no live 2026 Federal Circuit appeal docket for US 5,440,749 was located. The patent's last significant appellate and Supreme Court activity in the public record appears to be the 2014–2019 window (Fed. Cir. 14-1317, 16-1306/1307/1309/1311, 18-1439–1445; Supreme Court 19-324), and the patent itself is expired.

I'll research the litigation history for US patent 5440749 (the "High performance, low cost microprocessor architecture" patent). Let me search multiple sources.

Let me dig deeper into the specific cases and the appellate history.

Litigation Involving U.S. Patent No. 5,440,749

Important scope note first: U.S. 5,440,749 ("High performance, low cost microprocessor architecture," inventors Charles H. Moore and Russell H. Fish III; filed Aug. 3, 1989 as App. 07/389,334; issued Aug. 8, 1995; original assignee Nanotronics Corp.) is one of the patents in the so‑called Moore Microprocessor Portfolio ("MMP"). Google Patents lists the anticipated expiration as 2012‑08‑08. That date matters enormously below: the ’749 patent expired just after the 2012 offensive suits were filed, so most of the litigation activity attributed to the portfolio (and reflected in the Google Patents "family litigation" list) ultimately turned on sibling patents — principally U.S. 5,809,336, 5,530,890 and 5,784,584 — not on the ’749 patent itself. I flag each item where I can and cannot confirm that the ’749 patent was actually asserted.

1. Ownership / declaratory controversy (2004–2005)

• EE Times (11/11/2004, 11/13/2004, 11/23/2004) reported that Patriot "is the plaintiff in a lawsuit against TPL, Daniel Leckrone and Charles Moore," and that the dispute concerned "US5809336, 6598148, 5440749, 5604915, 5530890, 5784584 and 5659703."
• Patriot also sued Relational Advisors LLC (an investment bank), a separate 2004 action referenced in the same press reports.
• Patriot separately announced infringement suits against Intel, Sony, Fujitsu, Toshiba, NEC and Matsushita in this period; I could not confirm which specific patents (and whether ’749) were asserted in those suits.

2. Declaratory‑judgment actions by accused infringers (N.D. Cal., 2008)

These are the clearest cases in which the ’749 patent itself was at issue.

A. Acer, Inc., Acer America Corp. & Gateway, Inc. v. Technology Properties Ltd., Patriot Scientific Corp. & Alliacense Ltd.

• Jurisdiction: U.S. District Court, N.D. Cal. (San Jose Division), Judge Jeremy Fogel; later Judge Paul S. Grewal
• Case No.: 5:08-cv-00877-JF/HRL
• Filed: February 8, 2008
• Nature: Declaratory judgment of non‑infringement/invalidity of the MMP patents; the ’749 patent was expressly pleaded (Plaintiffs' Third Claim for Declaratory Judgment Regarding the ’749 Patent). Defendants counterclaimed for infringement.
• Status/outcome: Stayed pending USPTO reexaminations (11 reexaminations filed against the five MMP patents as of April 2009); docket shows the case ultimately closed/disposed. Note the case was actively litigated into 2013 (motions in limine, summary‑judgment practice).

B. HTC Corp. & HTC America, Inc. v. Technology Properties Ltd., Patriot Scientific Corp. & Alliacense Ltd.

• Jurisdiction: N.D. Cal., Judge Jeremy Fogel/Paul S. Grewal
• Case No.: 5:08-cv-00882-JF/HRL
• Filed: February 2008 (related to and considered with the Acer case)
• Nature: Declaratory judgment of non‑infringement/invalidity
• Outcome: Following reexamination, HTC went to trial on the ’336 patent and was found to infringe (jury awarded TPL a one‑time lump‑sum royalty of $958,560). That verdict relates to the ’336 patent, not ’749.

C. ASUSTek Computer, Inc. & ASUS Computer International v. Technology Properties Ltd., Patriot Scientific Corp., MCM Portfolio LLC & Alliacense Ltd.

• Jurisdiction: N.D. Cal., Judge Edward M. Chen (initially)
• Case No.: 5:08-cv-00884-EMC (listed on Google Patents as 5:08-cv-00884)
• Filed: 2008
• Nature: Related DJ action; related to the Acer and HTC cases.

D. Barco N.V. v. Technology Properties Ltd., Patriot Scientific Corp. & Alliacense Ltd.

• Jurisdiction: N.D. Cal., Judge Jeremy D. Fogel
• Case No.: 5:08-cv-05398-JF/HRL
• Filed: December 1, 2008
• Nature: DJ that the ’584, ’749 and ’890 patents are invalid and not infringed by Barco products. The court's order (Oct. 23, 2009) confirms "the MMP patents include United States Patent Nos. 5,784,584; 5,440,749; 5,530,890; and 5,809,336."
• Outcome: Judgment entered with respect to the ’584 patent; plaintiff's motion for attorneys' fees denied without prejudice at that time; the ’749 and ’890 aspects remained pending.

3. Offensive suits by TPL / Phoenix Digital Solutions / Patriot (N.D. Cal. and elsewhere, 2012)

E. Technology Properties Limited LLC, Phoenix Digital Solutions LLC & Patriot Scientific Corp. v. LG Electronics, Inc. et al.

• Jurisdiction: N.D. Cal.
• Case No.: 3:12-cv-03880-VC (N.D. Cal.; also shown as 3:12-cv-03880)
• Filed: July 24, 2012
• Patents asserted (per Stanford NPE database): US 5,440,749; 5,530,890; 5,809,336
• Status: Consolidated for claim construction with companion cases; claim‑construction/tutorial hearing held September 18, 2015 before Magistrate Judge Paul S. Grewal; claim‑construction Report and Recommendation issued; case stayed pending resolution of objections to that report.

Companion 2012 cases (filed July 24, 2012; consolidated for the Sept. 18, 2015 Markman/tutorial hearing — the ’749 patent may or may not have been asserted in each; I could confirm ’749 only for the LG case, 3:12-cv-03880):

• TPL v. [[Huawei Technologies Co.](/litigations/by-plaintiff/Huawei%20Technologies%20Co.), Ltd.](/litigations/by-plaintiff/Huawei%20Technologies%20Co.%2C%20Ltd.) et al. — 3:12-cv-03865-VC (N.D. Cal.)
• TPL v. ZTE Corporation et al. — 3:12-cv-03876-VC (N.D. Cal.)
• TPL v. Samsung Electronics Co., Ltd. et al. — 3:12-cv-03877-VC (N.D. Cal.)
• TPL v. [Nintendo Co., Ltd.](/litigations/by-plaintiff/Nintendo%20Co.%2C%20Ltd.) et al. — 3:12-cv-03881-VC (N.D. Cal.)
• Additional related 2012 case numbers listed on Google Patents: 3:12-cv-03861, 3:12-cv-03863, 3:12-cv-03878; 4:12-cv-03860, 4:12-cv-03861, 4:12-cv-03865, 4:12-cv-03870, 4:12-cv-03879; and E.D. Cal. 3:12-cv-03870, 3:12-cv-03879.

Caveat: Because the ’749 patent expired August 8, 2012 — roughly two weeks after these complaints were filed — it is highly likely the ’749 claims dropped out of the 2012 litigation early and the cases proceeded on the ’336 and ’890 patents. I could not confirm a judgment specifically adjudicating ’749 in these actions.

4. Federal Circuit and Supreme Court activity

Google Patents lists the following appellate/Supreme Court matters as family litigation:

• Fed. Cir. No. 14-1317
• Fed. Cir. Nos. 16-1306, 16-1307, 16-1309, 16-1311
• Fed. Cir. Nos. 18-1439, 18-1440, 18-1441, 18-1444, 18-1445
• U.S. Supreme Court No. 19-324
• (Earlier) Fed. Cir. No. 2008-1020, Technology Properties Ltd. v. ARM, Ltd. — affirmed the Texas non‑infringement judgment in a Rule 36 opinion (May 9, 2008); this concerned the ’584 patent, not ’749.

I cannot confirm that any of the 2014–2018 Federal Circuit appeals or the 2019 Supreme Court petition (No. 19-324) actually involved the ’749 patent — given the ’749 expiration date, those appeals most plausibly concern siblings such as the ’336 and ’890 patents. I am flagging this rather than asserting it.

5. Eastern District of Texas (2005 / 2008)

• 2005: TPL and Patriot sued a number of consumer‑electronics manufacturers in Texas alleging infringement of claim 29 of the ’584 patent by "ARM" processors — not the ’749 patent. TPL stipulated to non‑infringement in Dec. 2007 after claim construction; affirmed by the Federal Circuit (2008‑1020).
• Google Patents also lists E.D. Tex. 2:08-cv-00172 and 2:08-cv-00177; I could not confirm whether ’749 was asserted in those.

6. Matters that are NOT ’749 litigation (to avoid confusion)

• ITC Inv. No. 337‑TA‑807 (digital photo frames, complainant Technology Properties Limited, LLC) asserted U.S. 6,976,623; 7,162,549; 7,295,443; and 7,522,424 — not the ’749 patent.
• Numerous reexaminations of the MMP patents were filed; the USPTO granted reexamination of the ’749 and ’890 patents (per the 2009 N.D. Cal. stay order) and TPL substituted replacement claim 59 for claim 9 of the ’749 patent, and amended claim 1 during reexamination (Acer v. TPL, May 13, 2011, No. 5:08-cv-00877).

Summary of what I can confirm with confidence

1. Patriot Scientific v. TPL / Leckrone / Moore (2004) — ownership dispute expressly naming the ’749 patent; settled June 2005.
2. Acer/Gateway v. TPL et al., N.D. Cal. 5:08-cv-00877, filed Feb. 8, 2008 — ’749 expressly pleaded; stayed for reexamination; disposed.
3. HTC v. TPL et al., N.D. Cal. 5:08-cv-00882 (filed Feb. 2008) — related DJ action.
4. ASUSTek v. TPL et al., N.D. Cal. 5:08-cv-00884 — related DJ action.
5. Barco N.V. v. TPL et al., N.D. Cal. 5:08-cv-05398, filed Dec. 1, 2008 — ’749 expressly named.
6. TPL/Phoenix Digital/Patriot v. LG Electronics et al., N.D. Cal. 3:12-cv-03880, filed July 24, 2012 — ’749 among the asserted patents.

If you need exact PTAB/CAFC docket‑level confirmation of which appeals touched ’749, that requires direct PACER/CM‑ECF and CAFC docket pulls; I have flagged every place where my sources do not let me state that with confidence rather than guessing.

I'll start by verifying the structured PTAB list against what web sources show for this patent — the "Moore Microprocessor Patent" family is heavily litigated, so I want to be careful not to conflate proceedings on sibling patents (5,530,890 / 5,809,336 / 5,784,584 / 6,598,148) with proceedings on 5,440,749 itself.

The search results are contaminated by an unrelated later "'749 patent" (a flashlight/touch-sensor patent). Let me search with tighter terms.

Proceedings overview

Total AIA trial proceedings on US 5,440,749: 0 — 0 active, 0 claims-invalidated, 0 claims-sustained, 0 settled, 0 institution-denied. The canonical USPTO Open Data Portal list reproduced in this prompt is empty, and independent web searching surfaced no IPR, PGR, or CBM naming this patent; the bottom-line defensive posture is therefore not "the patent has been hardened by surviving the PTAB" but something better for a defendant: the '749 patent is expired (anticipated expiration 2012-08-08 per the ODP record) and was never adjudicated at the PTAB, so there is no PTAB estoppel benefiting anyone, no PTAB claim construction to rely on, and no live validity fight — a demand letter citing this patent has to clear the § 286 damages bar before validity even matters.

⚠️ False-positive warning. Searching "'749 patent IPR" returns at least two different, unrelated patents also informally called "the '749 patent": (a) a microchip-controlled touch-sensor flashlight patent in a chain of continuations with 1998-era priority, pending in PTAB E2E under petition IDs 1459449 and 1462072 (art: Beard, Jahagirdar, Schultz; "energy consuming load"); and (b) a Truesight Communications SD-card patent asserted in Truesight Commc'ns LLC v. Samsung, E.D. Tex. 2:23-cv-00643. Neither is US 5,440,749 (Moore/Fish, microprocessors, 1989 priority). Do not import those results.

Proceedings list

There are no AIA trial proceedings to list for US 5,440,749. No entries exist for this patent in the structured PTAB file, and none were found in web sources. Accordingly I am not providing per-proceeding blocks — inventing proceeding numbers, panels, or claim-level dispositions for a proceeding that does not exist is exactly the failure mode this exercise is testing for.

Two structural notes on why the docket is empty, both of which matter for a defendant:

• PGR is categorically unavailable. PGR reaches only patents with an effective filing date on or after 2018-03-16 (originally 2013-03-16). The '749 patent's priority date is 1989-08-03 (filed 1989-08-03, granted 1995-08-08), over two decades too early.
• CBM was effectively unavailable too. A microprocessor-architecture patent does not claim "a method or corresponding apparatus for performing data processing or other operations used in the practice, administration, or management of a financial product or service" (AIA § 18(d)(1)), and the CBM program sunset in 2020-09. So IPR was the only viable vehicle — and the '749's window was narrow: the patent expired 2012-08-08, roughly six weeks before IPR/CBM practice began on 2012-09-16.

Adjacent record (Article III and family activity — not PTAB proceedings)

The '749 patent has a very heavy litigation record, all in district courts and the Federal Circuit. Summarizing it is useful because defendants routinely mistake these appeals for PTAB outcomes.

Federal Circuit Nos. 2018-1439, -1440, -1441, -1444, -1445 — Technology Properties Ltd. LLC v. [Huawei Technologies Co.](/litigations/by-plaintiff/Huawei%20Technologies%20Co.)

• Type: Article III appeal (not an AIA trial), from N.D. Cal. Nos. 3:12-cv-03865-VC, -03876-VC, -03877-VC, -03880-VC, -03881-VC (Judge Vince Chhabria)
• Judgment: 2019-02-06 — AFFIRMED under Fed. Cir. R. 36 (summary affirmance, no opinion). Mandate issued 2019-04-17.
• Panel: Moore, Taranto, Chen.
• Issues: review of a district court final judgment granting defendants' motion for summary judgment of non-infringement of U.S. Patent No. 5,809,336 (the '749 patent's continuation sibling — same specification, different claims).
• Appeal source: Technology Properties Appendix E, Supreme Court No. 19-324
• Defensive value: Confirms the MMP family's core asserted claims were losing propositions by 2019 — but note this was about the '336, not the '749.

Federal Circuit Nos. 2016-1306, -1307, -1309, -1310, -1311 — Technology Properties Ltd. v. Huawei Technologies Co., 849 F.3d 1349

• Type: Article III appeal (claim construction, then stipulated non-infringement)
• Decided: 2017-03-03; panel Moore (author), Wallach, Chen (per Lexology; FindLaw lists Judge Moore)
• Holding: On "an entire oscillator disposed upon said integrated circuit substrate" (representative claim 6 of the '336 patent): affirmed the prosecution-disclaimer-based construction of "whose frequency is not fixed by any external crystal" (Magar-based disclaimer); vacated the "does not require a control signal" limitation because the patentee only disclaimed a command input to change the clock frequency (Sheets-based disclaimer), construing it as "does not require a command input to change the clock frequency." Remanded.
• Full text: Midpage, 849 F.3d 1349; analysis: McDermott, Knobbe Martens
• Note: Google Patents' family litigation table lists 16-1306, -1307, -1309 and -1311 but omits 16-1310, which appears in the Federal Circuit caption. Treat the family table as incomplete.
• Defensive value: The '749 and '336 share a specification, so the ring-oscillator/dual-clock disclosure described here is the same text — but the disclaimer attaches to the '336's claim language. Do not assume it limits the '749's claims, which the Federal Circuit has never construed.

Supreme Court No. 19-324 — Technology Properties Ltd. v. Huawei Technologies Co.

• Certiorari denied 2019-11-04 (per Patriot Scientific/Mosaic ImmunoEngineering disclosure: "On November 4, 2019, we announced that the Supreme Court of the United States denied our petition for a writ of certiorari… alleging infringement of the '336 patent"). This is the entry shown as "U.S. Supreme Court case 19-324" in the structured family data.

HTC Corp. v. Technology Properties Ltd., N.D. Cal. 5:08-cv-00882 — the one place the '749 was actually pressed

• Filed: 2008-02-08 (HTC declaratory-judgment action on the '336, '584, '749, and '148 patents)
• Counterclaim: 2008-11-21 — TPL counterclaimed for infringement of the '336, '749, '148, and '890 patents
• '749 disposition: On 2013-07-17 the court accepted the parties' stipulation dismissing the '148 and '749 patents from the litigation. (Doc. 707)
• Defensive value: This is the strongest single fact in the record. The only case in which TPL was affirmatively pressing the '749 ended with the '749 being dropped by stipulation, with no claim construction, no invalidity ruling, and no infringement finding.

Other family-level filings in the structured data (not necessarily '749-specific)

The Google Patents family record lists numerous N.D. Cal., E.D. Cal., E.D. Tex., and S.D.N.Y. filings from 2008–2012 (e.g., 3:10-cv-00816; 3:12-cv-03860/-03870/-03876/-03877/-03879/-03880/-03881; 4:12-cv-03860/-03861/-03865; 5:08-cv-00882/-00884/-05398; 5:12-cv-03870; 2:08-cv-00172/-00177; 1:09-cv-04083), plus CAFC Nos. 14-1317 and 16-1306/-1307/-1309/-1311. These are keyed to the family (Darts-ip family 23537828), not to the '749 alone, and are district court/appellate matters — not AIA trials. I did not verify claim-level outcomes in each, and I will not guess at dispositions I did not see.

Strategic summary

Claim status. No claim of US 5,440,749 has been canceled, confirmed, or even construed by the PTAB — there is no Final Written Decision of any kind. On the patent's face, all claims stand as issued by the USPTO, subject only to any ex parte or inter partes reexamination activity in the family (see the unverified note below). Conversely, no claim has been sustained by the PTAB either: this is an untested patent, not a hardened one. I found no merits ruling on the '749's claims in any forum — the one case where they were asserted settled out by stipulation on 2013-07-17. The far more consequential status fact is temporal: the ODP record shows anticipated expiration 2012-08-08, and contemporaneous reporting confirms the '749 lapsed in August 2012, meaning "the plaintiffs can no longer seek an injunction, but can still claim damages for the past six years" (heise.de). That six-year lookback window (§ 286) closed in 2018 — a complaint filed today against an accused product would recover nothing.

Estoppel landscape. § 315(e)(2) estoppel is triggered only by a petitioner who obtains a final written decision in an IPR/PGR. Because there are zero PTAB proceedings, no party anywhere is estopped as to this patent. Every § 102 and § 103 ground a defendant can develop is available in district court, in the ITC, or in a declaratory judgment action. The flip side: there is also no PTAB record to borrow — no institution decision finding a "reasonable likelihood" of unpatentability, no Board claim construction, and no FWD to point to. Any defense must be built from scratch. And note that § 315(b)'s one-year bar has long since run for essentially every party that was ever served; § 315(a)(1) similarly bars IPR by any party that previously filed a DJ action.

Pattern signals. The aggressor throughout was the patent owner side — Nanotronics Corp. → Patriot Scientific → ITV Corp. → Technology Properties Limited → Charles H. Moore's Equinox Trust, with Phoenix Digital Solutions in the licensing chain — not a defensive aggregator. I found no Unified Patents (or RPX) IPR against the '749 despite searching for one; Unified surfaces in these searches only as an amicus in unrelated 2025–2026 Supreme Court briefing (No. 25-1230) and as a petitioner in other matters. TPL's monetization effort concentrated on the '336, '890, '584, and '148 siblings and was litigated and appealed through 2019 (including a cert petition), while the '749 — the ancestor application — was quietly dropped from the litigation in 2013. The absence of any IPR on a patent that was asserted against a broad defendant set is a real signal, but read it correctly: the '749 expired in August 2012, six weeks before the AIA trial regime opened, and the patent owner abandoned it in litigation the next year. It was never worth challenging at the Board, rather than being a patent that survived attack.

Unverified adjacency (flagged, not asserted). Public documents reference inter partes reexamination activity in the MMP family — a "Decision on Appeal in Inter Partes Reexamination Control No. 95/001,247, dated March 18, 2013" appears in an IDS excerpt in my search results. I could not verify by search which patent that reexamination targeted, or whether it involved the '749. Reexaminations are not AIA trials in any event, so they do not affect the "0 proceedings" conclusion; but if you are building a defense, pull the '749's full file wrapper before relying on the "untested" characterization.

Recommended next steps

1. If a demand letter cites US 5,440,749, lead with expiration, not invalidity. Per the ODP record the patent expired 2012-08-08 (see Google Patents — "Anticipated expiration 2012-08-08"). No injunction is available; under 35 U.S.C. § 286, damages reach only six years back from filing, so a complaint filed after 2018-08-08 recovers nothing. Demand the accuser identify the specific accused product's acts and dates before engaging on the merits.
2. There is no FWD to link to. Because the PTAB docket is empty, I cannot quote a disposition — the honest answer is that none exists. For any conflicting assertion, verify directly at PTAB E2E and the PTAB Decisions page by patent number, and at Google Patents for the assignment/expiration chain. Also verify the ownership chain (Equinox Trust → TPL → Patriot Scientific → Phoenix Digital Solutions) and standing, since the record shows multiple security interests and releases (Swartz Private Equity, Lincoln Ventures, Knobbe Martens) in the 2001–2012 window.
3. Chase the siblings, not this patent. The live MMP assets historically were US 5,809,336, 5,530,890, 5,784,584, and 6,598,148 — and the '336 is the one that produced real appellate law (Tech. Props. v. Huawei, 849 F.3d 1349 (Fed. Cir. 2017); Rule 36 affirmance 2019-02-06; cert denied 2019-11-04). If a new assertion campaign appears, run the PTAB/CourtListener check against those numbers; check CourtListener's docket search for "Technology Properties" and the family at Darts-ip family 23537828.
4. If you nonetheless want an IPR on the '749 (e.g., to kill a nuisance demand), recognize the economics are poor: the patent is expired, there is nothing to enjoin, and no backward damages remain. Also note current PTO practice — the Director has retaken institution decisions (memoranda of 2025-03-26 and 2025-10-17, per USPTO/JPO briefing) and discretionary "settled expectations" denials have reportedly been applied to hundreds of petitions on old patents (Unified amicus brief, S. Ct. No. 25-1230, filed 2026-05-29) — a 1989-priority, 2012-expired patent is close to the paradigm case for discretionary denial.
5. Bottom line for a defendant today: the '749 is expired, was never tested at the PTAB, and was voluntarily dropped from the only case in which it was asserted. The absence of PTAB activity here is not the "well-asserted patents eventually attract IPRs" signal — it is the signal of an abandoned, expired patent. Any assertion built on it should be resisted on § 286 grounds first, and on § 102/§ 103 in district court second, with no PTAB estoppel constraining anyone.

I'll research the assignment chain using available sources. Let me run several searches in parallel.

Let me dig for the actual reel/frame records and additional chain entities.

Ownership-chain analysis — US 5,440,749 ("High performance, low cost microprocessor architecture")

Source limitation stated up front (per your constraints): I was unable to query the USPTO Assignment Center / assignment.uspto.gov record directly through the tools available to me, and the authoritative full text I was given (the Google Patents rendering) carries Google's legal-events reassignment list — which reproduces the recording date, assignor, assignee and conveyance type, but not the reel/frame number and not the correspondent of record. I will therefore present the chain that is grounded in the record above, and I will mark reel/frame and correspondent as not retrieved rather than supplying plausible-looking numbers. Anyone needing those two fields must pull them from https://assignmentcenter.uspto.gov/ (search by patent number 5440749) or via the same query at https://assignment.uspto.gov/patent/index.html.

Verify the chain at: https://assignmentcenter.uspto.gov/ → Patent Assignment Search → enter 5440749.

Inventors

Pattern notes — and where the standard "inventor exodus" tell does not fire:

• There is no evidence in the record of both inventors assigning to the original assignee at filing. Fish's interest moved through the Fish Family Trust (1991) and then to Nanotronics (1992). Moore's interest did not go to Nanotronics at all — it went to ITV Corporation (1997), a Moore-affiliated entity. That split is the structural cause of the 2004–2005 inventorship/ownership war (see below).
• Timing does not match the "all inventors depart within 12 months of filing" fire-sale precursor. Filing was 1989-08-03; Fish's transfer to the Fish Family Trust is recorded 1991-09-26 (~25 months) and Moore's to ITV Corporation 1997-09-08 (~8 years). So on the dates available, this is not the classic near-filing inventor-decampment pattern — it is a slow, disputed separation of two co-inventors' interests into two competing chains.
• Contested inventorship is a documented fact, not an inference. Patriot Scientific publicly asserted in November 2004 that discovery in its inventorship litigation "strongly suggests that Fish was the sole inventor" of sibling patent 5,809,336, and that Moore and his associates were marketing interests in the '336 patent with "inaccurate claims of ownership and inventorship." (EE Times, 2004-11-23). Treat the two-inventor listing on the face of the '749 patent as the record fact, and treat inventorship as litigated and unresolved in the public reporting.

Original assignee

• Nanotronics Corporation, an Oregon corporation ("NANOTRONICS CORPORATION A CORPORATION OF OR"), of Eagle Point, Oregon.
• Line of business: microprocessor development — the '749 disclosure is a complete 32-bit RISC CPU architecture (44-pin PLCC, dual CPU/DMA-CPU, quad-instruction fetch), so the entity was an operating chip-design venture, not a holding company.
• Did it ship a product embodying the claims? No evidence located. I found no Nanotronics-branded commercial 32-bit microprocessor in commerce, no product literature, and no corroborating datasheets. State this as "not evidenced," not as "proven absent."
• Current status: defunct as a going concern on the record. Nanotronics assigned its interest in this patent to Patriot Scientific Corporation in 1996 and does not appear in any later link of the chain. I cannot verify the precise corporate endpoint (dissolution vs. bare inactivity) — flagging as unverified.
• ⚠️ Name-collision warning: the modern "Nanotronics" (Nanotronics Imaging, Brooklyn, NY) is an unrelated company. Do not merge them.

Assignment timeline

Convention: the dates below are the dates shown on the Google Patents legal-events record and are believed to be USPTO recordation dates, not execution dates. I could not separate executed-date from recorded-date, and I could not obtain reel/frame or correspondent. Reel/frame: NOT RETRIEVED. Correspondent: NOT RETRIEVED.

• 1989-08-03 — Application 07/389,334 filed; Nanotronics Corporation shown as applicant/original assignee.

  • Conveyance: (inventor-to-original-assignee chain — no discrete assignment record surfaced in the source I was given)
  • Assignor: Charles H. Moore / Russell H. Fish, III (presumed)
  • Assignee: Nanotronics Corporation
  • Correspondent: not retrieved
  • Context: formation of the original ownership chain. Note the gap: no separate recorded instrument for Moore→Nanotronics appears, which is consistent with the later dispute over title.

• 1991-09-26 — recorded (date as shown)

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Fish, Russell H., III
  • Assignee: Fish, Janet Long, as Trustee of the Fish Family Trust
  • Correspondent: not retrieved
  • Context: estate/trust planning on the part of one co-inventor — moves inventorship interest off the individual and into a family trust.

• 1992-01-21 — recorded

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Fish, Janet Long, Trustee of the Fish Family Trust
  • Assignee: Nanotronics Corporation (a corporation of Oregon)
  • Correspondent: not retrieved
  • Context: internal consolidation — Fish's half is brought into Nanotronics.

• 1996-10-28 — recorded

  • Conveyance: Assignment of Assignors' Interest (see document for details)
  • Assignor: Nanotronics Corporation
  • Assignee: Patriot Scientific Corporation
  • Correspondent: not retrieved
  • Context: asset transfer to an IP-licensing-oriented public company. This is the point at which the patent's economic exploitation leaves the original operating venture.

• 1997-09-08 — recorded

  • Conveyance: Assignment of Assignors' Interest (see document for details)
  • Assignor: Moore, Charles H.
  • Assignee: ITV Corporation
  • Correspondent: not retrieved
  • Context: the other half of the split. Moore routes his co-inventor interest to his own vehicle rather than to Nanotronics or Patriot — this creates the co-ownership conflict litigated 2004–2005.

• 2001-11-20 — recorded

  • Conveyance: Security Interest
  • Assignor: Patriot Scientific Corporation
  • Assignee: Swartz Private Equity, LLC
  • Correspondent: not retrieved
  • Context: securitization / financing — the patent is pledged as collateral by a cash-poor licensor.

• 2002-05-23 — recorded

  • Conveyance: Convertible Debenture (Note Article IV)
  • Assignor: Patriot Scientific Corporation
  • Assignee: Lincoln Ventures, LLC
  • Correspondent: not retrieved
  • Context: securitization / convertible financing.

• 2002-08-05 — recorded

  • Conveyance: Convertible Debenture
  • Assignor: Patriot Scientific Corporation
  • Assignee: Lincoln Ventures, LLC
  • Correspondent: not retrieved
  • Context: second tranche of the same convertible financing — a repeat financier, which is a financial-distress indicator, not a litigation indicator.

• 2002-09-03 — recorded

  • Conveyance: Amended Secured Promissory Note and Addendum
  • Assignor: Patriot Scientific Corporation
  • Assignee: Swartz Private Equity, LLC
  • Correspondent: not retrieved
  • Context: amendment/restructuring of the 2001 secured note — confirms Patriot was cash-constrained.

• 2003-02-14 — recorded

  • Conveyance: Security Interest
  • Assignor: Patriot Scientific Corporation
  • Assignee: Knobbe, Martens, Olson & Bear, LLP
  • Correspondent: not retrieved — though note the irony that the assignee here is a law firm taking a security interest, so its own recording correspondent would be its own attorneys.
  • Context: fees-for-collateral — Patriot pledged the patent to outside patent counsel against unpaid legal fees. Strong distress signal.

• 2003-10-30 — recorded

  • Conveyance: Assignment of Assignors' Interest (see document for details)
  • Assignors: ITV Corporation and Moore, Charles H.
  • Assignee: Technology Properties Limited
  • Correspondent: not retrieved
  • Context: transfer-to-asserter. Moore's half is consolidated into the TPL licensing vehicle (TPL Group; licensing arm Alliacense Limited), setting up the eventually-unified MMP portfolio.

• 2003-12-08 — recorded

  • Conveyance: Assignment of Assignors' Interest (see document for details)
  • Assignor: Moore, Charles H.
  • Assignee: Technology Properties Limited
  • Correspondent: not retrieved
  • Context: cleanup/second instrument completing the Moore→TPL transfer. Two TPL recordings five weeks apart is a modest cascade signal within the Moore chain.

• 2005-08-08 — recorded

  • Conveyance: Termination of Security Interest
  • Assignor: Knobbe, Marten, Olson & Bear, LLP
  • Assignee: Patriot Scientific Corporation
  • Correspondent: not retrieved
  • Context: the 2003 fee lien was cleared — consistent with Patriot's improved cash position after the June 2005 Patriot/TPL portfolio-unification settlement.

• 2009-03-24 — recorded

  • Conveyance: Assignment of Assignors' Interest (see document for details)
  • Assignor: Moore, Charles H.
  • Assignee: Moore, Charles H., TTE, UTD 03/21/2006 The Equinox Trust
  • Correspondent: not retrieved
  • Context: estate-planning transfer to a revocable trust, mirroring the 1991 Fish Family Trust move. Not an arm's-length sale.

• 2012-02-10 — recorded (two instruments, same day)

  • Conveyance: Release by Secured Party
  • Assignor: Lincoln Ventures, LLC → Assignee: Patriot Scientific Corporation
  • Conveyance: Release by Secured Party
  • Assignor: Swartz Private Equity, LLC → Assignee: Patriot Scientific Corporation
  • Correspondent: not retrieved
  • Context: the 2001–2002 financing liens discharged — this is the last recorded event before the noted 2012-08-08 anticipated expiration.

A material gap you should close: the record above contains no assignment to Phoenix Digital Solutions, LLC, Patriot's MMP licensing subsidiary, and no assignment to any RPX/AST/Unified-type aggregator. Loyalty-licensing of the MMP portfolio post-2012 appears to have run through services/novation agreements (see the Amended Alliacense Services and Novation Agreement between Alliacense LLC and Phoenix Digital Solutions, LLC, dated 2014-07-23, filed as an exhibit to Patriot Scientific's SEC filings), not through recorded assignments. That distinction matters for standing analysis and it is not something you can read off the assignment record — flagging it as a finding in the negative.

Timeline diagram

timeline
    title Ownership of US 5440749
    1989 : Filed Aug 3 by Nanotronics Corp
    1991 : Fish interest to Fish Family Trust
    1992 : Fish Family Trust to Nanotronics
    1996 : Nanotronics assigns to Patriot Scientific
    1997 : Moore interest to ITV Corporation
    2001 : Security interest to Swartz Private Equity
    2002 : Convertible debentures to Lincoln Ventures
         : Amended note to Swartz Private Equity
    2003 : Security interest to Knobbe Martens
         : ITV and Moore assign to TPL
         : Moore assigns again to TPL
    2005 : Knobbe security interest terminated
    2009 : Moore interest to Equinox Trust
    2012 : Lincoln and Swartz liens released

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT (moderate)

The patent left the operating venture (Nanotronics, Oregon chip designer) and was consolidated into licensing vehicles: Patriot Scientific Corporation (rec. 1996-10-28) and Technology Properties Limited (rec. 2003-10-30 and 2003-12-08), the latter operating through its licensing brand Alliacense Limited. The concrete evidence is not the naming: it is that Patriot Scientific appears in the Stanford NPE Litigation Database classified as a non-practicing entity on case 3:12-cv-03880, and that TPL/Alliacense is documented as a portfolio-wide licensing/demand program (Alliacense ran demand-and-license campaigns against dozens of OEMs; see the plaintiffs' description in HTC Corp. v. Technology Properties Ltd., N.D. Cal. 5:08-cv-00882, and the Alliacense/Ford licensing announcements). I am not resting this on the LLC suffix; I am resting it on the licensing-only business model and the NPE-database classification.

2. Known asserter in the chain — PRESENT (strong)

Technology Properties Limited LLC / TPL Group and its licensing arm Alliacense Limited are a documented high-frequency patent assertion program against the MMP portfolio; Patriot Scientific Corporation is classified by the Stanford NPE Litigation Database as an NPE on the very case asserting this patent. Direct evidence:

• Stanford NPE Litigation Database, case 3:12-cv-03880 — Technology Properties Limited LLC et al v. LG Electronics, Inc. et al, filed 2012-07-24, asserting 5,440,749, 5,530,890 and 5,809,336; asserter Patriot Scientific Corporation.
• Stanford NPE Litigation Database, patent 5440749 page — TPL v. Garmin (3:12-cv-03870) among the listed assertions.
• Earlier assertion wave: TPL filed E.D. Tex. infringement actions in 2006 and again on 2008-04-25 (N.D. Cal. 5:08-cv-00882 order, Docket 49).

Note: TPM/TPL is not on the enumerated shortlist you supplied (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, DGC, Spangenberg), so I am sourcing this from the Stanford NPE database and the primary litigation record rather than by name-matching your list.

3. Repeat correspondent across the chain — UNRETRIEVED / unclear

I could not obtain the correspondent of record for any of the fifteen recorded instruments above, because the Google Patents legal-events rendering I was given does not expose that field and I could not reach the Assignment Center directly. There are at least three places where recurrence would be highly diagnostic and should be checked first:

• the two TPL recordings (2003-10-30 and 2003-12-08) — same counsel across a five-week window?
• the three Patriot financing instruments (Swartz 2001-11-20 and 2002-09-03; Lincoln 2002-05-23 and 2002-08-05) — a single lender's counsel?
• the two release instruments filed the same day (2012-02-10, Lincoln and Swartz) — near-certainly a single filer.

I will not name a correspondent I have not seen. Please pull the reel/frame + correspondent fields and I can complete this signal.

4. Cascading transfers — PRESENT (mild, but bounded)

Chained transfers within short windows:

• 1991-09-26 → 1992-01-21 (Fish → Trust → Nanotronics, ~4 months);
• 2003-10-30 → 2003-12-08 (ITV/Moore → TPL, then Moore → TPL again, ~5 weeks).
  This is a partial score. The overall chain is slow (1989→2012 spans 23 years), and the assignees do not share a common registered-agent address or a common principal in the record I have. The 2003 TPL double-recording is the closest thing to a cascade, and it is unremarkable as a corrective/second instrument.

5. Pre-litigation transfer — NOT PRESENT on the dates available

The intellectual-property transfer into the asserting entity (TPL, rec. 2003-10-30 / 2003-12-08) predates the first TPL assertion wave by roughly 2.5 years (2006 E.D. Tex.) and the main MMP campaign by ~4.5 years (2008). The 1996 Patriot acquisition predates the 2006 assertion wave by a decade. No instrument in the record executes within 6 months of a suit naming this patent. This signals the owner acquired the patent as a portfolio asset long before litigating it, not that a shell was spun up on the courthouse steps. (The 2009-03-24 Equinox Trust transfer postdates the 2008 suits entirely and is estate planning.)

6. Bankruptcy fire-sale — NOT PRESENT (but distress is documented)

No Chapter 7/11 filing by Nanotronics or Patriot is evidenced in the material reviewed, and there is no trustee's sale of this patent. However, the record contains four distinct collateral instruments in a 16-month window — Swartz Private Equity security interest (2001-11-20), Lincoln Ventures convertible debentures (2002-05-23 and 2002-08-05), Swartz amended note (2002-09-03) — followed by a security interest to outside counsel Knobbe, Martens, Olson & Bear (2003-02-14) to secure unpaid fees. That is a company pledging its crown-jewel patent to its lenders and to its lawyers. Call the bankruptcy prong not present, but record the financial-distress overlay as a documented fact from the reels themselves.

7. Privateering — UNCLEAR

The chain does not fit the textbook pattern (operating company → NPE asserting against that company's competitors). Nanotronics was not an ongoing operating company in the assert years; there is no evidence TPL/Alliacense asserted on Nanotronics' commercial behalf. What is documented is a three-way ownership fight: Patriot Scientific sued TPL, Daniel Leckrone and Charles Moore over these patents (public reporting 2004-11-11 through 2004-11-23), and Moore himself sued TPL Group and Alliacense in Santa Clara Superior Court in October 2010 alleging fraud, breach of fiduciary duty and breach of contract (EE Times, 2010-10-04). So the entity structure was contested internally — the opposite of a clean privateering arrangement. Mark unclear, leaning not present.

8. Defensive aggregator (anti-NPE) — NOT PRESENT

The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. The last recorded instruments are (a) the 2009-03-24 transfer to Charles H. Moore's own Equinox Trust (the inventor's estate vehicle, not a defensive aggregator) and (b) the 2012-02-10 lender releases restoring the liens to Patriot Scientific. The portfolio's assertion history confirms the opposite of neutralization.

Verdict

NPE — high confidence.

Three independent, concrete signals fire. (1) Known asserter: the record places the patent in the hands of Technology Properties Limited (rec. 2003-10-30, 2003-12-08) and Patriot Scientific Corporation (rec. 1996-10-28), and the Stanford NPE Litigation Database classifies Patriot Scientific as a non-practicing entity on case 3:12-cv-03880 (TPL v. LG Electronics, filed 2012-07-24), which asserts this patent alongside 5,530,890 and 5,809,336. (2) Shell/portfolio-vehicle transfer: the patent left the operating venture Nanotronics and passed into licensing-only vehicles, with the licensing function later running through Alliacense Limited under services/novation agreements rather than through any product business. (3) Cascading/consolidating transfers: the Fish chain (1991-09-26 → 1992-01-21 → 1996-10-28) and the Moore chain (1997-09-08 → 2003-10-30 → 2003-12-08) were both consolidated into asserting entities, and the inventor-side terminal event (2009-03-24) moves the remainder into the inventor's own trust.

Two signals that would strengthen a moderate finding are absent on the dates: there was no pre-litigation transfer within 6 months of any suit (the 2003 TPL transfer predates the 2008 campaign by years), and no bankruptcy proceeding — though the 2001–2003 collateral instruments show acute financial distress at the assignor. The repeat-correspondent signal is unretrieved, not negative, and is the single highest-value item left to verify.

Verify at: https://assignmentcenter.uspto.gov/ (Patent Assignment Search → 5440749). Pull the reel/frame and correspondent fields for the 2003-10-30 and 2003-12-08 TPL entries and the 2012-02-10 release pair; that will either confirm or rule out signal 3.

Cross-reference note vs. the earlier sections

This section is consistent with, and does not repeat, the earlier bibliographic table and aspect summary. One clarification to the earlier material: the earlier Uncertainty / verification notes referred to the chain as "genuinely messy" — the concrete form of that mess is now dated: two parallel inventor chains that were never merged at the original assignee, which is the specific root of the 2004–2005 Patriot/TPL ownership and inventorship litigation and the 2010 Moore v. TPL/Alliacense fraud suit. No contradiction found; this is an elaboration.

I'll research the prior-art citations for US 5,440,749. Let me run targeted searches.

Let me dig into the specific "References Cited" list for US 5,440,749.

Step 1 — USPTO lookup for US 5,440,749 (literal number match only)

The record returned for US 5,440,749 matches the bibliographic data already established: High performance, low cost microprocessor architecture, Moore & Fish, appl. 07/389,334 filed 1989‑08‑03, granted 1995‑08‑08, original assignee Nanotronics Corp., "Expired – Lifetime." No results for other numbers have been folded in (see the identifier-confusion flags in §7 — several appeared in the search stream and I have excluded them).

Refinement to the previously generated section (not a contradiction, a narrowing): I was able to recover the issued claim language from an Espacenet claims view. This corrects the earlier caveat that the claim set was unavailable. Key consequence: the issued independent claims are not 1:1 with the eleven Summary-of-Invention aspects — the DRAM + triple-multiplexer limitation is not in claim 1.

Claim 1 (verbatim): a CPU integrated circuit, a memory external to the CPU IC, a bus, and means for fetching multiple sequential instructions from said memory in parallel and supplying them to the CPU during a single memory cycle, "said bus having a width at least equal to a number of bits in each of the instructions times a number of the instructions fetched in parallel", the CPU including an ALU and a first push-down stack whose top item and next item feed the ALU's two inputs, with the ALU output written back to the top-of-stack storage and the stack remainder below the "next" location.

Claim 8: as claim 1, plus a second push-down stack fed from the top-of-stack storage through control means, doubling as a register file, bidirectionally connected.

Claim 9: as claim 1, but with the memory being a dynamic random access memory and multiplexing means providing row addresses, column addresses and data on the bus.

Dependent families (from the same specification text) cover: the instruction register/sequencing counter/decoder with SKIP and MICROLOOP; the loop counter; variable-width 8/16/24-bit operands selected by the counter; the PROM-load/DMA startup path; the ring-oscillator clock with separate I/O clock; the three-tier latch/RAM/off-chip stack with cascaded pointers; the OE-line adaptive timing circuit; and the polynomial / fast-multiply ALU datapaths.

Step 2 — Critical caveat on the (56) "References Cited" list

I could not retrieve the (56) box verbatim from an authoritative source. The full text supplied in the user message is the Google Patents rendering, and in that rendering the prosecution-citation block is absent (the fetched page jumps from "Classifications" → "Definitions" → specification, with no "References Cited" table). Google Patents does render this table in the browser, but it was not captured in the payload I was given, and my fetches returned only fragments.

What I have instead are two secondary-source streams that disagree on scope, plus one authoritative front page (from the sibling divisional) whose list is demonstrably not 749's. I present them with provenance attached, because conflating them is the single most likely error here.

Correction to a widespread conflation: a widely-circulated forum post (InvestorsHub, wolfpackvoltare profile) prints one reference list under the heading "United States Patent 5,440,749" and a second list under the heading "References Cited [Referenced By]." The first list (3,967,104 Brantingham → 5,414,862 Suzuki) is verifiably US 5,809,336's list, not 749's — it appears character-for-character on the front page of the US 5,809,336 PDF. Any analysis that assigns those references to 5,440,749 is wrong. This is exactly the kind of number-adjacency error the task instructions warn against.

Step 3 — Candidate (56) references attributed to US 5,440,749

Provenance: secondary source stream A (printout of a USPTO-style front page for "United States Patent 5,440,749 / Moore, et al." reproduced in the forum post; examiner "Eng" matches 749's Primary Examiner David Y. Eng, which is corroborating). Confidence: moderate on the membership of this list; low on the exact dates as OCR'd.

Two things I will not do: I will not silently "correct" 4,665,495 to 4,660,155 (the strict rule), and I will not invent descriptions for rows 1, 3, 5–9. Those rows need the front page pulled from USPTO PatentCenter before they can be relied on for claim-charting.

Step 4 — The list that is not 749's (US 5,809,336, the divisional)

Recorded here only so it does not get mis-assigned. Provenance: authoritative — front page of the US 5,809,336 PDF, corroborated by the forum post's first list.

Note the shape of this list: it is dominated by clock-generation, power-management and addressing art — which is precisely why the '336 divisional (variable-speed ring-oscillator clock) attracted those citations, and why they should not be mapped onto 749's claims.

Step 5 — § 102 mapping: what actually matters for 749's issued claims

Bearing in mind that I have not read the full texts of the listed references, the honest assessment is:

The single hardest limitation to meet under § 102 is claim 1's parallelism + bus-width element: "fetch multiple sequential instructions from said memory in parallel … during a single memory cycle," with "said bus having a width at least equal to a number of bits in each of the instructions times a number of the instructions fetched in parallel." Nothing in either candidate list is, on its face, a wide-bus multi-instruction-fetch reference. The listed art is stack-machine, microprogram-control, calculator-addressing and clock/power art. If 749 was ever invalidated or narrowed on this point, the art is more likely to be non-patent literature than any listed patent.

Claim 9 (DRAM + row/column/data multiplexing on one bus) is the claim most likely to have near-miss art in the DRAM-interface field — but again, neither candidate list is a multiplexed-DRAM-bus reference.

Claim 8 (second push-down stack doubling as a register file, bidirectional) has plausible analogues in Burroughs-style stack machine art — which is where Thaden becomes interesting.

Element-by-element status: not performed. A § 102 anticipation requires correspondence for every element; without the reference texts I will not assert it.

Step 6 — Reexamination / non-patent prior art (materially more probative than the (56) list)

Secondary source (forum post, citing a PUBPAT request) states a substantial new question of patentability was raised "by Ledzius in light of Thaden — U.S. Patent No. 4,660,155 to Thaden, et al." on family claims. If accurate, this means:

• Ledzius (a reference I have not identified with confidence) combined with Thaden was the combination a third party considered most damaging across the Moore/Fish family.
• The Thaden reference appears in 749's own citation stream as US 4,665,495 (per the secondary source) — with US 4,660,155 as its sibling. This number-adjacency is flagged rather than resolved.

Additional litigation exhibits surfaced in the record (from deposition exhibit lists, case No. 2‑05CV‑494 (TIW)) — these are not (56) references but are the real-world prior-art toolkit for this family:

• Mostek 1981 3870/F8 Microcomputer Data Book (Exhibit 8)
• IC Master 1980, pp. 2016–2040, Fairchild (Exhibit 9)
• Oki Japan MSH‑Boom 96000 schematic, Jul. 13, 1989 (Exhibit 13) — note this post-dates the 1989‑08‑03 filing/priority by only ~3 weeks; if it is being used as art it must be § 102(a)/(g)-era art, and its exact date will be dispositive.
• Correspondence of Sept. 11–30, 1992 (Fish↔Higgins re: "patent application for High Performance Low Cost Microprocessor") — relevant to derivation/inventorship, not § 102.

Also noted: the EE Times (Nov. 11, 2004) ownership dispute in which TPL/Leckrone/Moore sought US 5,809,336, 6,598,148, 5,440,749, 5,604,915, 5,530,890, 5,784,584 and 5,657,703 from Patriot — confirming all seven are one family and that the 5,809,336 divisional's citation list must never be merged into 749's.

Step 7 — Identifier-confusion flags (strict literal-reading compliance)

The search stream returned several documents that must not be substituted for the ones above:

1. JP 3967104 B2 — returned for a numeric search on "3967104." It is a Japanese plastics/metal-composite patent (Taisei Plas, 2007), not US 3,967,104 (Brantingham). Same digits, unrelated document, different jurisdiction and number space.
2. "the '549 patent" — in the literature this nearly always means US 7,162,549 (MCM Portfolio v. HP, IPR2013‑00278, Fed. Cir. 2015‑1091), not US 5,440,749. Excluded, as in the prior section.
3. US 4,660,155 vs. US 4,665,495 — both attributed to Thaden; the two are described in the source as siblings. Kept distinct.
4. US 4,761,763 Hicks — date printed as 8/1985 in one source, "August 1988" in another. Both preserved.
5. US 4,042,972 — appears with the inventor name spelled "Gruner" in one list and "Grunes" in another. Both preserved; treated as one reference.

Step 8 — Bottom line and confidence

Recommended next action to close the gap: pull the front page of US 5,440,749 from USPTO PatentCenter (or the patentimages PDF) and read the (56) box directly. That single document resolves the provenance dispute above definitively. I have not fabricated that list, and I would not stake a claim chart on rows 1, 3, 5–9 of §3 until it is produced.

I'll gather the prior-art citation record and any claim text I can verify before analyzing.

Good — I found verbatim issued claim text. Let me pull the rest of the claims and the front-page reference list.

Let me try to complete the claim set and locate the front-page reference list.

Obviousness analysis — US 5,440,749 under 35 U.S.C. § 103

0. Scope of the record — read this first

Before the analysis, three limits on what I can responsibly assert:

(a) The "Prior Art section of this page" is thinner than the task implies. The full text supplied for US 5,440,749 contains only the Description of the Prior Art / Background narrative, the Definitions section (Google's auto-extracted "the present invention relates to…" statements), the Prior art keywords field (instructions, stack, register, memory, processing unit), and the CPC classification tree. The front-page "References Cited" (U.S. Patent Documents / Foreign Documents / Other Publications) list is not present in that text, and my searches for it were exhausted without locating it. Everything below is therefore built from (i) the prior art the patent itself names, (ii) the art areas the USPTO classified these claims into, and (iii) named pre-August-1989 references that are common general knowledge in this field. Where a reference is one I name from general knowledge rather than from a located document, I say so.

(b) Claim text is partially verified. I located verbatim issued text for independent claims 1, 8 and 9 (Espacenet's claims view for US5440749A: https://worldwide.espacenet.com/publicationDetails/claims?locale=de_EP&date=19950808&CC=US&NR=5440749A). Claims 2–7 and anything above 9 were not retrieved; the total claim count is unverified. This matters — the strongest art I identify below attacks claims/embodiments I cannot confirm are claimed here.

(c) Same-family documents are not prior art. US 5,530,890, US 5,604,915, US 5,659,703, US 5,784,584, US 6,598,148, US 5,809,336, EP 0497772, EP 0786730 and JP 2966085 all share the 1989-08-03 priority and are not § 102/103 art against 5,440,749. I flag this because search results readily surface EP 0786730 B1's claims (which recite the DMA CPU, the multiplexing, the column latch and the OE-sensing circuit) and a naive analyst could mistakenly treat them as prior art.

Literal-reading note: the specification as printed says "Intel 8960" and "SPARC." I reproduce those identifiers exactly as published. I believe the intended part is the Intel 80960/i960 family, but per the operating rules I do not silently correct it.

1. Legal framework applied

I apply Graham v. John Deere as refined by KSR Int'l v. Teleflex, 550 U.S. 398 (2007): (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) secondary considerations. I place principal weight on the KSR rationales available here:

• Combination of familiar elements yielding predictable results ("the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results").
• Design incentive / market force — the patent's stated objects are lower pin count and lower cost, which are precisely the market forces driving the art.
• Finite number of identified, predictable solutions (the "obvious to try" rationale).
• Aggregation, not combination — where claim elements are recited side-by-side with no claimed functional interdependence, MPEP 2143.01(III) applies.

2. Level of ordinary skill (as of 1989-08-03)

A POSITA would hold a B.S. in EE or CS and have roughly 3–5 years of microprocessor or computer-architecture design experience, or an M.S. plus 1–2 years. That person would be conversant with: the RISC literature (Patterson & Sequin, A VLSI RISC, IEEE Computer, Sept. 1982; Patterson & Hennessy, Computer Architecture: A Quantitative Approach, 1990 ed. — the latter post-dates the filing but reflects pre-1989 work); stack-machine history (Burroughs B5000/B5500, English Electric KDF9, HP FOCUS); DRAM interfacing including RAS/CAS row-column address multiplexing; and the instruction-prefetch/instruction-buffer art.

3. The claims at issue, decomposed

Claim 1 (verbatim structure, OCR artifacts preserved): a CPU integrated circuit; a memory external to that CPU IC; a bus between them; means for fetching instructions configured to fetch multiple sequential instructions from said memory in parallel and supply them to the CPU during a single memory cycle; the bus "having a width at least equal to a number of bits in each of the instructions times a number of the instructions fetched in parallel"; the CPU including an ALU and a first push down stack, the stack having a top-item storage feeding a first ALU input and next-item storage feeding a second ALU input, the remainder of the stack connected to the next-item storage to receive items "when pushed down," and the ALU output connected to the top-item storage.

Claim 8 = claim 1 + a second push-down stack configured as a register file, the top-item storage providing an input to it through control means, and the top-item storage and register file being bidirectionally connected.

Claim 9 = claim 1 + the memory being a DRAM + multiplexing means on the bus configured to provide multiplexed row addresses, column addresses and data in both directions.

Two structural observations that shape the whole analysis:

1. Claims 1/8/9 do not claim the DMA CPU, the SKIP instruction, the MICROLOOP instruction, the column-latch instruction cache, the OE-sensing self-timed bus, the ring-oscillator clock, the three-level stack cache, the polynomial generator, or the fast-multiply datapath. Those are the features the specification touts as delivering "20 MIPS for 20 dollars." Claim 1 is broad and thin; its central limitation is the multi-instruction fetch.
2. Claim 1's "means for fetching … during a single memory cycle," coupled with the tautological bus-width clause, is close to a claim to reading a word. If the machine's memory bus is 32 bits wide and its instructions are 8 bits, then any single 32-bit DRAM access inherently delivers four sequential 8-bit instructions in parallel during one memory cycle, and the bus width necessarily equals 8 × 4. That makes the limitation largely inherent in the bus width, not in any new hardware.

4. The prior-art landscape (all pre-1989-08-03)

Group I — Stack-machine datapaths (attacks claims 1, 8's ALU/stack elements).
Burroughs B5000/B5500 (1961–64; Barton, A New Approach to the Functional Design of a Digital Computer, WJCC 1961); English Electric KDF9 (1963) "nesting store"; HP FOCUS/3000; the Forth-engine processors — Novix NC4016 (1985) and Harris RTX 2000 (1988) — which put the top-of-stack in a register feeding the ALU. Each discloses an ALU whose two operands are the top two stack elements and whose result is written back to the top-of-stack, with the remainder of the stack below. Caveat: the B5000/KDF9 material I am confident about; the exact stack depths and TOS-register implementation of the NC4016/RTX 2000 should be verified against their databooks before use in a petition.

Group II — Wide/multi-word instruction supply (attacks claim 1's fetch element).
IBM Stretch (1961) instruction lookahead; CDC 6600 (1964) "instruction stack" that fetches a 60-bit instruction word holding multiple instruction parcels at a time (Thornton, Design of a Computer: The Control Data 6600, 1970); IBM System/360 Model 85 (1968) — a cache line fill fetches a block of sequential instructions in a single main-memory access; Fisher, Very Long Instruction Word Architectures and the ELI-512, ISCA-10 (1983) — a fetch word intentionally widened to carry several operations per cycle. DRAM page-mode / static-column access, in which several sequential columns are read off one row access, is likewise pre-1989 and is the natural hardware vehicle for a multi-word fetch.

Group III — Register-stack architecture (attacks claim 8).
AMD Am29000 (1987, Am29000 User's Manual) — a 192-register file in which 128 registers form a push-down register stack that hardware spills/fills to memory on procedure entry/exit; Berkeley RISC I/II register windows (1981–83) — an overlapping window stack in the register file; Burroughs stack "display." The spill/fill control path is exactly claim 8's "control means … bidirectionally connected."

Group IV — Multiplexed buses and DRAM addressing (attacks claim 9).
RAS/CAS row/column address multiplexing is mandatory in DRAMs from the Mostek MK4096 (1974) and Intel 2116 (1976) onward, and is described in essentially every DRAM data book of the era. Sharing address and data on one set of pins is standard in the Intel 8086/8088 (1978, AD0–AD15) and is the express subject of the published document my search located: Microprocessor system having a multiplexed address/data bus which communicates with a plurality of memory and input/output devices including TTL output gates (Costantini, published 10 Oct 1985) — which describes demultiplexing a shared address/data bus and using the most-significant address bits for device selection.

Group V — Loop counters, skip and hardware repeat (attacks the unverified dependent claims).
IBM System/360 BCT / BXH / BXLE — branch-on-count instructions with a dedicated hardware loop counter; the spec's own admission that "the PDP-8 and Data General NOVA provide the ability to skip a single instruction"; and critically, the Intel 8086 REP prefix with MOVS/CMPS/SCAS (1978) and the Zilog Z80 LDIR/CPIR (1976), which repeat a move/search entirely in hardware, decrementing a counter, testing a condition and terminating — i.e., the specification's "microloop … useful for block move and search operations."

Group VI — The page's own classification evidence. The examiner placed these claims in art areas that were already densely populated: G06F 9/30069 (Instruction skipping instructions, e.g. SKIP), G06F 9/30065 and G06F 9/325 (Loop control instructions; loop counter), G06F 9/381 (Loop buffering), G06F 12/0875 (caches with dedicated cache, e.g. instruction or stack), G06F 7/785 (LIFO buffers; overflow or underflow handling therefor), G06F 7/582/584 (LFSR / Galois-field sequence generation), G06F 7/5272 (serial-parallel multiplication with row-wise addition of partial products). Classifications are not themselves prior art, but they are strong evidence that each claimed concept sat in a recognized, existing art area rather than in unexplored territory.

5. Combinations that render the claims obvious

Combination A — Claim 1 over a stack machine in view of a wide-instruction-fetch machine

Primary reference: a stack processor (Group I, e.g., Burroughs B5500 or KDF9) — discloses every datapath limitation of claim 1: ALU, first push-down stack, top-item storage → first ALU input, next-item storage → second ALU input, remainder of the stack below next-item storage, ALU output back to top-item storage.
Secondary reference: CDC 6600 instruction stack / S/360-85 cache line fill / ELI-512 (Group II) — discloses fetching a plurality of sequential instruction parcels in parallel out of one memory access, over a fetch path as wide as the instruction width times the number of parcels.

Motivation to combine (specific, articulable):

1. Same field, same problem. Both references are directed to getting instructions into an execution unit from a memory. The patent's own Background concedes the problem was known: "the bottleneck in most computer systems is the memory bus," and the bus "is used to fetch instructions and fetch and store data." Fetching wider directly addresses that stated bottleneck.
2. Known technique improving a known device in the same way. Widening the fetch word to amortize memory latency had been applied across the field (Stretch lookahead, 6600 instruction stack, 360/85 line fill, VLIW). KSR: where a technique has been used to improve one device and a POSITA would recognize it would improve similar devices the same way, the application is obvious absent something beyond ordinary skill.
3. The result is arithmetic, not inventive. Claim 1's bus-width clause is simply "bus width = instruction width × N." Once N instructions are to be delivered together, the bus is as wide as the product — the claim recites the consequence of its own premise.
4. Mere aggregation. Claim 1 recites the multi-fetch means and the stack-ALU side by side with no claimed functional cooperation between them. Two independently known subsystems, each performing its own known function in the combined device, is the definition of an aggregation that does not rise to patentability (MPEP 2143.01(III)). The specification's claim that the multi-fetch "mode of operation is possible because of the use of a push down stack and register array" is a design rationale, not a claimed structural interlock.

Combination B — Claim 1 as inherently met by any 32-bit-word machine executing packed 8-bit opcodes

Reference: a CPU IC with an external memory and a bus at least as wide as the packed instruction group (Group II, and the patent's own admitted prior art: the specification states "the INMOS transputer attempted a similar strategy"). If the transputer fetches a full memory word and executes the constituent instruction bytes sequentially, the "fetch multiple sequential instructions from said memory in parallel and supply … during a single memory cycle" and bus-width limitations read directly on it.

This is an anticipation-adjacent theory (§ 102(b)) as much as a § 103 one. I flag it as a high-value hypothesis rather than a conclusion: it depends on the T414/T800 instruction-buffer behavior, which I could not verify here, and on how a court construes "supply the multiple sequential instructions … during a single memory cycle" (all at once, versus one byte per cycle from a prefetched word).

Combination C — Claim 8 over Combination A in view of register-stack/register-window art

Secondary references: AMD Am29000 register stack (1987) and/or Berkeley RISC I/II register windows (1981–83); alternatively the Burroughs stack-with-display.

Motivation:

1. Both the Am29000 and the Berkeley RISCs built a push-down register resource with hardware spill/fill to memory for exactly the reason the patent gives — reducing procedure-call and local-variable overhead. Claim 8's "second push down stack … configured as a register file" plus "control means" is that structure.
2. The bidirectional connection is inherent in spill/fill. A register stack that overflow/underflows must write values down to memory and read them back; a bidirectional path between the top-of-stack storage and the register stack, governed by control logic, is the necessary and conventional implementation. A posited element that is the inherent byproduct of another recited element cannot supply patentability.
3. The patent's own statement supplies the KSR argument against it. The specification says "the combined stack 74/register 134 architecture has not been used previously due to inadequate understanding by computer designers of optimizing compilers and the mix of transfer versus math/logic instructions." That is an admission that the elements were known and available and that the inventors' contribution was recognising a use for them. Under In re Baxter Travenol / Titanium Metals v. Banner, discovery of a new property or advantage in a known combination does not confer patentability.
4. Instruction-bit economy provides an independent motivation: implied stack addressing spares explicit register-address fields, which is the same rationale underlying the 5-bit window fields in the Berkeley RISC register file.

Combination D — Claim 9 over Combination A in view of DRAM addressing and multiplexed-bus art

Secondary references: DRAM RAS/CAS row-column address multiplexing (Group IV, e.g., Mostek MK4096/Intel 2116 data books); multiplexed address/data bus practice (Intel 8086/8088; the Costantini 1985 document located in my search).

Motivation:

1. DRAM row/column multiplexing is not optional — it is how DRAM halves its address pin count. Anyone claiming "a dynamic random access memory" plus "multiplexed row addresses [and] column addresses" on a bus claims a routine DRAM design convention.
2. Adding data to the same pins is a one-step extension of the already-known address/data multiplexing of the 8086 and of the Costantini document, which expressly frames bus multiplexing as a pin-count/cost measure — the same object the patent states ("It is an object of this invention to provide a microprocessor with a reduced pin count and cost").
3. Predictable result, per the patent itself. The specification says the triple multiplexing "results in fewer buffers to expand, fewer interconnection lines, fewer I/O pins and fewer internal buffers, with a slight to non-existent speed penalty." A combination whose only claimed benefit is fewer pins and whose cost is conceded to be negligible produced no unexpected result.
4. The claim-9 combination is driven by the claimed constraint. Given a 32-bit bus that must carry a RAS address, a CAS address and data, multiplexing them on those same 32 lines is the design the pin budget dictates — the classic "finite number of identified, predictable solutions" situation.

Combination E — The likely dependent claims (SKIP, MICROLOOP/loop counter, variable-width operands)

Unverified as to claim scope, but if claims covering these constructs exist in 5,440,749 they face severe § 103 exposure:

• SKIP up to three instructions over PDP-8/NOVA single-instruction skip (admitted in the specification) and the 8086/8088 "skip on condition" opcodes — an obvious variation in the number skipped (a mere change in degree, In re Rose).
• MICROLOOP with a hardware loop counter, "useful for block move and search operations" — the 8086 REP MOVSW / REPNE SCASB prefix and the Z80 LDIR/CPIR already implement hardware-repeated block move and search with counter decrement and conditional termination, without re-fetching the instruction. IBM 360 BCT supplies the hardware loop counter. The specification's assertion that "such a hardware implementation of microloops is much faster than conventional software implementation" concedes the conventional implementation was the starting point.
• Variable-width 8/16/24-bit operands selected by a 2-bit counter — right-justified variable-length operands with length determined by opcode are textbook (e.g., variable-length instruction formats generally; the Transputer's variable-length instruction encoding).

Combination F — Likely dependent claims on the polynomial generator and fast multiply

G06F 7/582/7/584 (LFSR and Galois-field sequence generation) and G06F 7/5272 (serial-parallel multiplication with row-wise addition of partial products) are the examiner-assigned classifications. The specification itself concedes "a polynomial is generated by a sequence of shift and exclusive OR operations" and that the novelty is "slightly modifying how the ALU 80 works" — i.e., implementing a textbook LFSR/Galois multiply in an existing datapath. A shift-and-add serial-parallel multiplier driven by a down counter is the canonical hardware multiplier of the era.

The strongest non-obviousness candidate in the family

The output-enable feedback self-timing (sensing circuit 410 + driver 418 on the OE line, READY when OE reaches a predetermined level) and the dual-clock ring-oscillator/PLL-free scheme have no counterpart in the art groups above that I can name, and they are the features the specification actually credits with the price/performance result. They are not in claims 1, 8 or 9. If the commercial significance of this patent family rests on those features, the claims under analysis here are the wrong target — and are correspondingly easier to invalidate under § 103. (Note: those features appear as claim elements in family member EP 0786730 B1, claim 6, confirming they were claimed somewhere in the family.)

6. Cross-cutting motivation-to-combine summary

7. Counterarguments a patent owner would raise, and how they fare

1. "The whole is greater than the parts; the combination breaks the von Neumann bottleneck." The specifications' own arithmetic undercuts this: "System speed is therefore 4 times the memory bus bandwidth" is the trivial consequence of a 4:1 instruction-width-to-bus-width ratio. No synergy beyond the expected is identified in the claims, which recite no cooperation between the fetch means and the stack datapath.
2. Secondary considerations (commercial success, licensing, industry adoption). The family was widely licensed and heavily asserted (the Google Patents record lists dozens of N.D. Cal./E.D. Tex./E.D. Cal./S.D.N.Y. suits and Federal Circuit appeals 14-1317, 16-1306/1307/1309/1311, 18-1439–1445, plus Supreme Court No. 19-324). In re GPAC / WBIP require a nexus between the evidence and the claimed invention. Here the nexus is weak for claims 1/8/9, because (i) the accused value proposition rests on the DMA CPU, the self-timing OE feedback and the ring-oscillator clock, none of which appear in claims 1/8/9; and (ii) the industry-wide move to wide fetch and on-chip stack caches was already under way for independent reasons. I note that I could not verify the outcomes of any of the listed proceedings for 5,440,749 specifically; do not treat the litigation list as a validity determination either way.
3. Teaching away. I found none directed at the asserted combinations. The Background criticises the pipelining approach, but claim 1 has no pipeline limitation, so the criticism is legally irrelevant to claims 1/8/9. The specification's "pipeline-free" advocacy is a reason the inventors avoided one technique, not a reason a POSITA would not have widened the fetch.
4. Unexpected results. The only candidate is the pin-count/package result — which the patent attributes to multiplexing, a known pin-reduction technique, and which it describes as achieved "without speed penalty," i.e., with no trade-off to be surprised about.

8. Graham factor summary and bottom line

• Scope/content of the prior art: rich. Stack-machine ALUs (Group I), multi-instruction/wide-word fetch (Group II), register-stack files (Group III), DRAM row/column and address/data multiplexing (Group IV), hardware loop counters/skip/repeat (Group V), across long-predating references.
• Differences: essentially the co-location of these known elements in one low-pin-count 32-bit part. No claimed inter-element cooperation in claims 1/8/9 beyond claim 8's register-stack control path, which is the conventional spill/fill mechanism.
• Level of skill: high enough to know all of the above as of 1989.
• Secondary considerations: potentially powerful as a matter of economics, but the nexus to these claims is weak.

Assessment: Claims 1, 8 and 9 are, on the record available to me, more likely than not invalid under § 103, and claim 1 also faces a real § 102(b) risk to the extent the multi-instruction fetch limitation is treated as inherent in a wide memory bus. The strongest invalidity theories are (i) A for claim 1, (ii) A + Am29000/RISC-window art for claim 8, and (iii) A + DRAM RAS/CAS multiplexing + 8086/Costantini address/data multiplexing for claim 9. I rate the § 103 case on claim 1 as strong, on claim 8 as strong-to-moderate (it depends on how much the "control means" and bidirectional-connection limitations are read to require), and on claim 9 as moderate (the triple multiplexing of row address, column address and data on one set of CPU pins is the least routine element in these three claims, and the closest art I located multiplexes address/data only, or row/column only).

9. Verification gaps — what a real § 103 challenge still needs

1. The front-page "References Cited" list for US 5,440,749. I could not retrieve it; it is not in the supplied text. This is the single most important missing item — it tells us what the examiner actually saw and what the claims were allowed over.
2. The complete issued claim set. Claims 2–7 and any claims above 9 are unretrieved; the total claim count is unknown. Claim-scope assumptions for the SKIP/MICROLOOP/variable-width/polynomial/multiply content are inferences from the Summary of the Invention, not verified claim text.
3. The prosecution history / file wrapper. Needed to identify the examiner's stated reasons for allowance and to check for any arguments or amendments that would create prosecution-history estoppel or a teaching-away record.
4. Databook verification for the specific hardware references I named from general knowledge: transputer T414/T800 instruction buffer, Novix NC4016 and Harris RTX 2000 stack/ALU datapaths, AMD Am29000 register-stack spill/fill control, CDC 6600 instruction stack word structure, and the Mostek MK4096 / Intel 2116 RAS/CAS timing. Each should be confirmed against a dated primary document before being relied on.
5. The Costantini document located in my search (published 10 Oct 1985) should be pulled in full and its publication/patent number confirmed; only its abstract and title were returned.
6. Whether the accused commercial products ever practiced claims 1/8/9's specific combination, for nexus purposes in a secondary-considerations analysis.

Identifiers I did not alter: "Intel 8960," "SPARC," "MSM514258-10," "IDT39C828/39C822/39C823," "MAX12V," "27256," and the OCR forms "memory extend of said," "arithmetic, logic unit" — reproduced as published, with probable readings noted only as commentary.