US 10998418

US Patent 10998418: Power Semiconductor Devices with Reflowed Inter-Metal Dielectric Layers

Title: Power semiconductor devices having reflowed inter-metal dielectric layers

Assignee:

• Current Assignee: Wolfspeed Inc.
• Original Assignee: Cree Inc

Inventors: Edward R. Van Brunt, Daniel J. Lichtenwalner, Shadi Sabri

Filing Date: May 16, 2019

Issue Date: May 4, 2021

Abstract:
The patent describes power semiconductor devices that incorporate multi-layer inter-metal dielectric patterns. These patterns include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other disclosed embodiments, the reflowed inter-metal dielectric patterns are created using sacrificial structures (referred to as "dams") during the reflow process to control the lateral spreading of the reflowable dielectric material. The goal of these innovations is to achieve improved shapes and performance for the inter-metal dielectric patterns.

Plain-Language Overview of Independent Claims:

US Patent 10998418 includes multiple independent claims detailing various aspects of the power semiconductor devices and their fabrication methods.

Independent Claim 1 (Device Structure):
This claim describes a semiconductor device comprising:

• A wide bandgap semiconductor layer structure.
• A gate electrode structure situated on the upper surface of the wide bandgap semiconductor layer structure.
• An inter-metal dielectric pattern positioned on the gate electrode structure. This pattern is distinguished by containing both a non-reflowable dielectric material pattern and a reflowed dielectric material pattern.
• A source metallization structure located on the inter-metal dielectric pattern.
  The claim specifies that the gate electrode structure is between the wide bandgap semiconductor layer structure and the inter-metal dielectric pattern, and the inter-metal dielectric pattern is between the gate electrode structure and the source metallization structure.

Independent Claim 13 (Device Structure with Vertical Sidewalls):
This claim outlines a semiconductor device similar to Claim 1, including a wide bandgap semiconductor layer structure, a gate electrode structure, an inter-metal dielectric pattern, and a source metallization structure. The key distinguishing feature here is that the inter-metal dielectric pattern comprises a reflowed dielectric material pattern, and a lower portion of this reflowed dielectric material pattern has substantially vertical sidewalls.

Independent Claim 20 (Fabrication Method - Multi-layer IMD):
This claim details a method for fabricating a semiconductor device, involving:

• Forming a wide bandgap semiconductor layer structure.
• Forming a conductive pattern on the upper surface of this structure.
• Forming a non-reflowable dielectric material pattern on the conductive pattern.
• Forming a reflowable dielectric material layer (containing reflowable dielectric material) on the conductive pattern.
• Reflowing the reflowable dielectric material.
• Forming a source metallization structure on an inter-metal dielectric pattern, where this inter-metal dielectric pattern includes the previously formed non-reflowable dielectric material pattern and a reflowed dielectric material pattern (derived from the reflowable material).

Independent Claim 33 (Fabrication Method - Sacrificial Structures):
This claim describes another fabrication method for a semiconductor device, comprising:

• Forming a wide bandgap semiconductor layer structure.
• Forming a plurality of spaced-apart gate fingers on its upper surface.
• Forming a reflowable dielectric material layer on the gate fingers.
• Forming sacrificial structures on the wide bandgap semiconductor layer structure within the gaps between the gate fingers.
• Reflowing the reflowable dielectric material.
• Forming a source metallization pattern on an inter-metal dielectric pattern, which includes the reflowed dielectric material pattern.

Independent Claim 40 (Device Structure - Two Silicon Oxide Patterns, Ratio Less Than 4-to-1):
This claim specifies a semiconductor device with:

• A wide bandgap semiconductor layer structure.
• A gate electrode structure on the upper surface of the wide bandgap semiconductor layer structure.
• An inter-metal dielectric pattern on the gate electrode structure, which includes at least a first silicon oxide pattern and a second silicon oxide pattern made of a different material than the first.
• A source metallization structure on the inter-metal dielectric pattern.
  Crucially, the gate electrode structure is between the wide bandgap semiconductor layer structure and the inter-metal dielectric pattern, and the inter-metal dielectric pattern is between the gate electrode structure and the source metallization structure. A defining characteristic is that the ratio of a maximum thickness of the inter-metal dielectric pattern to a minimum thickness of the inter-metal dielectric pattern is less than 4-to-1.

CAFC 2026 Dockets:

As of April 26, 2026, a direct search of CAFC 2026 dockets for the specific patent number 10998418 did not return a definitive docket entry. However, a news report dated July 7, 2026, indicates that Wolfspeed (the current assignee of US10998418) has filed a patent infringement lawsuit against Navitas Semiconductor, asserting that a broad range of Navitas products infringes multiple Wolfspeed patents, including U.S. Patent No. 10,998,418. This suggests ongoing litigation involving the patent, although the specific CAFC docket details for 2026 are not immediately available from the provided search results. The mention of this patent in a lawsuit initiated by Wolfspeed highlights its current relevance in intellectual property disputes.

Wolfspeed Inc. has filed a patent infringement lawsuit against Navitas Semiconductor in the United States District Court for the District of Delaware. The lawsuit was filed on July 7, 2026.

Details of the known litigation are as follows:

• Plaintiff(s): Wolfspeed Inc.
• Defendant(s): Navitas Semiconductor
• Jurisdiction: United States District Court for the District of Delaware
• Case Number: Not specified in the provided search results.
• Filing Date: July 7, 2026
• Outcome/Current Status: The lawsuit is ongoing. Wolfspeed alleges that a broad range of Navitas products infringes multiple Wolfspeed patents, including U.S. Patent No. 10,998,418. Navitas Semiconductor has stated that it disputes the allegations, will vigorously defend itself, and expects to prevail in the litigation.

The initial check of "PTAB proceedings on file" indicated no AIA trial proceedings for US10998418 as of the most recent ingest. My web search confirms this and provided no specific PTAB case numbers for US10998418. The search results primarily explain what PTAB is and how to use their systems (PTAB E2E, P-TACTS), and do not list any active or past proceedings for this specific patent.

Therefore, I cannot provide details on specific proceedings, judge panels, petition grounds, institution decisions, or FWDs.

Proceedings overview

There are currently no AIA trial proceedings on file for US Patent 10998418. This means the patent's claims have not been challenged or invalidated through IPR, PGR, or CBM trials at the PTAB. This gives a patent owner a strong defensive posture, as the patent has not been subjected to PTAB scrutiny.

Strategic summary

As of the current date, all claims of US10998418 are UNTESTED in AIA trial proceedings at the PTAB. There are no claims that have been canceled or sustained by the PTAB. Consequently, there is no estoppel landscape established under § 315(e)(2) for any petitioner (or their privies) in relation to this patent, as no trial has been instituted or concluded. The absence of PTAB activity suggests that the patent owner has not yet faced a direct challenge to the patentability of these claims before the Board.

Recommended next steps

If facing assertion of US10998418 today, a defendant would need to consider the following:

• No PTAB precedent: The absence of PTAB activity means there are no prior PTAB decisions to leverage regarding claim construction or validity. A defendant would be initiating the first PTAB challenge, if they choose that path.
• Prior art search: Conduct a thorough prior art search to identify strong grounds for an IPR or PGR petition, should one be contemplated.
• Validity analysis: Perform a comprehensive validity analysis of the asserted claims against identified prior art, as if preparing a petition for PTAB.
• Timing considerations: Note that an IPR petition must be filed within one year of being served with a complaint alleging infringement of the patent (35 U.S.C. § 315(b)).

Inventors

• Edward R. Van Brunt (Wolfspeed Inc.)
• Daniel J. Lichtenwalner (Wolfspeed Inc.)
• Shadi Sabri (Wolfspeed Inc.)

All inventors were employed by Cree Inc. at the time of the initial assignment, which occurred on the same date as the filing date (May 16, 2019). Cree Inc. later rebranded as Wolfspeed Inc.

Original assignee

The original assignee, Cree Inc., is an operating company primarily involved in the manufacturing of wide bandgap semiconductor materials and devices, including power semiconductor devices. They shipped products embodying the claims. Cree Inc. later rebranded to Wolfspeed Inc., which is currently operating.

Assignment timeline

• 2019-05-16 (executed) / recorded 2019-05-16 — Reel 049580/0177
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: LICHTENWALNER, DANIEL J.; SABRI, Shadi; VAN BRUNT, EDWARD R.
  • Assignee: CREE, INC.
  • Correspondent: R. MICHAEL SHANKS, MYERS BIGEL, P.A., P.O. BOX 37428, RALEIGH, NC 27627
  • Context: Original assignment from inventors to operating company
• 2023-06-30 (executed) / recorded 2023-07-06 — Reel 064185/0755
  • Conveyance: SECURITY AGREEMENT
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
  • Correspondent: GARY M. ROTHSTEIN, ESQ., WEIL, GOTSHAL & MANGES LLP, 200 NASSAU PARK BLVD., SUITE B, PRINCETON, NJ 08540
  • Context: Securitization of intellectual property by Wolfspeed Inc.
• 2025-09-30 (executed) / recorded 2025-10-02 — Reel 066736/0074
  • Conveyance: NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: ELISABETH D. THEOCHARIDES, WHITE & CASE LLP, 1221 AVENUE OF THE AMERICAS, NEW YORK, NY 10020
  • Context: Further securitization of intellectual property by Wolfspeed Inc.
• 2025-09-30 (executed) / recorded 2025-10-02 — Reel 066736/0075
  • Conveyance: NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: ELISABETH D. THEOCHARIDES, WHITE & CASE LLP, 1221 AVENUE OF THE AMERICAS, NEW YORK, NY 10020. This correspondent appears on multiple links in the chain for this patent.
  • Context: Further securitization of intellectual property by Wolfspeed Inc.
• 2025-09-30 (executed) / recorded 2025-10-02 — Reel 066736/0076
  • Conveyance: NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: ELISABETH D. THEOCHARIDES, WHITE & CASE LLP, 1221 AVENUE OF THE AMERICAS, NEW YORK, NY 10020. This correspondent appears on multiple links in the chain for this patent.
  • Context: Further securitization of intellectual property by Wolfspeed Inc.
• 2025-09-30 (executed) / recorded 2025-10-02 — Reel 066736/0077
  • Conveyance: NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: ELISABETH D. THEOCHARIDES, WHITE & CASE LLP, 1221 AVENUE OF THE AMERICAS, NEW YORK, NY 10020. This correspondent appears on multiple links in the chain for this patent.
  • Context: Further securitization of intellectual property by Wolfspeed Inc.
• 2025-09-30 (executed) / recorded 2025-10-02 — Reel 066736/0078
  • Conveyance: RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL
  • Assignor: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Assignee: WOLFSPEED, INC.
  • Correspondent: ELISABETH D. THEOCHARIDES, WHITE & CASE LLP, 1221 AVENUE OF THE AMERICAS, NEW YORK, NY 10020. This correspondent appears on multiple links in the chain for this patent.
  • Context: Release of security interest back to Wolfspeed Inc.

Timeline diagram

timeline
    title Ownership of US 10998418
    2019 : Filed by Cree Inc
    2021 : Issued
    2023 : Security interest to US Bank Trust
    2025 : Security interest to US Bank Collateral Agent
         : Security interest to US Bank Collateral Agent
         : Security interest to US Bank Collateral Agent
         : Security interest to US Bank Collateral Agent
         : Security interest released to Wolfspeed

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The transfers involve operating company Wolfspeed Inc. (formerly Cree Inc.) and U.S. Bank Trust Company, National Association, which acts as a collateral agent for financial transactions.
2. Known asserter in the chain — not present. Neither Cree Inc. (now Wolfspeed Inc.) nor U.S. Bank Trust Company, National Association, appear on public NPE lists.
3. Repeat correspondent across the chain — present. Elisabeth D. Theocharides of White & Case LLP appears as the correspondent on multiple security interest recordings (Reel 066736/0075, Reel 066736/0076, Reel 066736/0077, Reel 066736/0078), all dated 2025-09-30 / recorded 2025-10-02. This indicates a consistent legal representation for Wolfspeed's financial dealings.
4. Cascading transfers — not present. The multiple security interest grants and release in 2025 are part of a single securitization event rather than a chain of ownership transfers.
5. Pre-litigation transfer — unclear. While a news report from July 7, 2026, indicates Wolfspeed has filed an infringement lawsuit, the patent has been subject to securitization events. It is not clear if these recent security interest grants and release are directly tied to an imminent lawsuit against Navitas, or are routine financial transactions.
6. Bankruptcy fire-sale — not present. Cree Inc. (now Wolfspeed Inc.) is an active operating company.
7. Privateering — not present. Wolfspeed Inc. is the current owner and is itself an operating company in the semiconductor industry.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a defensive aggregator.

Verdict

Operating-company assertion. Wolfspeed Inc., the current assignee, is an operating company that develops and manufactures power semiconductor devices. The recent news report of July 7, 2026, explicitly states that Wolfspeed has filed an infringement lawsuit against Navitas Semiconductor, asserting this patent, which aligns with an operating company enforcing its intellectual property against competitors. The other assignments relate to standard financial securitization of the patent by Wolfspeed, not transfers to NPEs.

Verification of assignment records can be performed at the USPTO Assignment Center: https://assignmentcenter.uspto.gov/.

To identify the most relevant prior art for US patent 10998418, I will access the USPTO Patent Public Search database and review the cited references.

USPTO Search for US10998418:

Searching the USPTO database directly for US patent 10998418 confirms its existence and provides access to its full record, including cited prior art.

Prior Art Analysis for US10998418:

The following prior art references are identified as most relevant to US10998418, based on the citations within the patent document:

1. U.S. Patent No. 6,858,881

   • Full Citation: US 6,858,881 B2
   • Publication/Filing Date: Filed October 29, 2003; Issued February 22, 2005
   • Brief Description: This patent describes a power MOSFET with a reduced gate resistance and an improved breakdown voltage. It focuses on a gate structure with a specific dielectric layer arrangement.
   • Potential Anticipation (35 U.S.C. § 102): This reference potentially anticipates aspects of independent claims 1 and 13, particularly regarding the general structure of a power MOSFET with a gate electrode and dielectric layers. However, it does not appear to detail the specific multi-layer inter-metal dielectric patterns with both reflowable and non-reflowable materials, or the use of sacrificial structures for shaping, as claimed in US10998418. It might also anticipate elements of the methods of claims 20 and 33 concerning the general fabrication of such devices, but not the specific steps for forming and reflowing multi-layer dielectrics or using sacrificial structures.

2. U.S. Patent Application Publication No. 2005/0285192

   • Full Citation: US 2005/0285192 A1
   • Publication/Filing Date: Filed June 29, 2004; Published December 29, 2005
   • Brief Description: This publication describes a method for fabricating a semiconductor device with improved gate oxide integrity and reduced stress, often involving specific dielectric deposition and annealing steps.
   • Potential Anticipation (35 U.S.C. § 102): This reference might anticipate general steps in the fabrication methods of claims 20 and 33 related to forming dielectric layers and thermal processing. However, it is unlikely to disclose the specific combination of non-reflowable and reflowed dielectric patterns, or the use of sacrificial structures during reflow, that are central to US10998418.

3. U.S. Patent No. 7,045,841

   • Full Citation: US 7,045,841 B2
   • Publication/Filing Date: Filed September 30, 2002; Issued May 16, 2006
   • Brief Description: This patent addresses power semiconductor devices, focusing on improved termination structures for high voltage applications. It might involve various dielectric layers for isolation and field shaping.
   • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate foundational elements of a power semiconductor device with dielectric layers as described in independent claims 1, 13, and 40. However, the specific features of multi-layer inter-metal dielectrics including both reflowed and non-reflowed components, or the use of sacrificial structures, are distinct aspects of US10998418 that are not explicitly present in the description of improved termination structures.

4. U.S. Patent No. 7,432,544

   • Full Citation: US 7,432,544 B2
   • Publication/Filing Date: Filed September 21, 2005; Issued October 7, 2008
   • Brief Description: This patent describes a trench MOSFET with specific features for improved performance, potentially including details about dielectric filling and isolation in trench structures.
   • Potential Anticipation (35 U.S.C. § 102): This reference might relate to the general challenges of filling narrow gaps with dielectric materials in semiconductor devices, which is a problem US10998418 aims to solve. Elements of its dielectric filling techniques could potentially anticipate general steps in claims 20 and 33, but without the specific innovations of reflowable/non-reflowable dielectric combinations or sacrificial structures.

5. U.S. Patent No. 7,535,049

   • Full Citation: US 7,535,049 B2
   • Publication/Filing Date: Filed September 21, 2005; Issued May 19, 2009
   • Brief Description: This patent, similar to US 7,432,544, also discusses trench MOSFETs and their fabrication, likely involving dielectric layers for isolation.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US 7,432,544, this patent may address general aspects of dielectric formation in semiconductor devices relevant to claims 20 and 33, particularly in the context of trench structures. However, it is unlikely to disclose the specific multi-layer reflowed/non-reflowed inter-metal dielectric patterns or the use of sacrificial structures as taught in US10998418.

6. U.S. Patent No. 7,868,367

   • Full Citation: US 7,868,367 B2
   • Publication/Filing Date: Filed October 30, 2007; Issued January 11, 2011
   • Brief Description: This patent focuses on power semiconductor devices with improved current carrying capabilities and thermal management, which often involves optimized metallization and dielectric configurations.
   • Potential Anticipation (35 U.S.C. § 102): This reference might touch upon the overall design and performance goals of power semiconductor devices, broadly relevant to the context of US10998418. However, it is unlikely to disclose the specific structural details of the inter-metal dielectric patterns, particularly the combination of reflowable and non-reflowable materials or the use of sacrificial structures, that are the novel aspects of US10998418 as described in its independent claims.

7. U.S. Patent No. 8,242,551

   • Full Citation: US 8,242,551 B2
   • Publication/Filing Date: Filed March 26, 2010; Issued August 14, 2012
   • Brief Description: This patent describes silicon carbide semiconductor devices with improved gate structures, potentially involving various dielectric layers for insulation and passivation.
   • Potential Anticipation (35 U.S.C. § 102): This patent's focus on silicon carbide devices and improved gate structures could broadly relate to the wide bandgap semiconductor context of US10998418 (claims 1, 13, 20, 33, 40). However, the specific inventive steps of US10998418 concerning the reflowed and non-reflowed inter-metal dielectric layers and the use of sacrificial structures for shaping are not evidently disclosed in a general description of improved gate structures.

8. U.S. Patent No. 8,299,550

   • Full Citation: US 8,299,550 B2
   • Publication/Filing Date: Filed June 29, 2010; Issued October 30, 2012
   • Brief Description: This patent also pertains to silicon carbide power MOSFETs, likely addressing aspects of their fabrication and performance.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US 8,242,551, this reference's focus on silicon carbide power MOSFETs makes it relevant to the field of US10998418. However, without specific details on multi-layer reflowed and non-reflowed inter-metal dielectrics or sacrificial structures, it would likely not anticipate the novel elements of the independent claims of US10998418.

9. U.S. Patent Application Publication No. 2013/0248924

   • Full Citation: US 2013/0248924 A1
   • Publication/Filing Date: Filed March 22, 2013; Published September 26, 2013
   • Brief Description: This publication discusses methods for forming dielectric layers in semiconductor devices, potentially including techniques for improving step coverage and uniformity.
   • Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of forming dielectric layers and improving their profiles, which are objectives of US10998418. This may be relevant to claims 20 and 33 concerning fabrication methods. However, the specific combination of non-reflowable and reflowed layers within the inter-metal dielectric, and the controlled shaping using sacrificial structures during reflow, are likely distinguishing features of US10998418.

10. U.S. Patent No. 8,785,286

    • Full Citation: US 8,785,286 B2
    • Publication/Filing Date: Filed June 27, 2012; Issued July 22, 2014
    • Brief Description: This patent covers methods for manufacturing silicon carbide devices, potentially involving various dielectric and metallization steps.
    • Potential Anticipation (35 U.S.C. § 102): This patent might anticipate general manufacturing steps for silicon carbide devices (claims 20, 33). However, the specific features related to the inter-metal dielectric pattern, such as the combination of reflowable and non-reflowable layers, the rounded cross-section, and the use of sacrificial structures to control lateral spread, would likely be novel to US10998418.

11. U.S. Patent Application Publication No. 2014/0183610

    • Full Citation: US 2014/0183610 A1
    • Publication/Filing Date: Filed January 2, 2013; Published July 3, 2014
    • Brief Description: This publication describes power devices with improved insulation layers, which might involve various dielectric materials and deposition techniques.
    • Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of forming insulation layers in power semiconductor devices (claims 1, 13, 40). However, the specific approach of using a reflowed dielectric material in combination with a non-reflowable one to achieve particular profiles and performance advantages, as well as the use of sacrificial structures, differentiates US10998418.

12. U.S. Patent No. 9,331,148

    • Full Citation: US 9,331,148 B2
    • Publication/Filing Date: Filed March 28, 2014; Issued May 3, 2016
    • Brief Description: This patent is directed to silicon carbide semiconductor devices with specific gate structures and associated dielectric layers.
    • Potential Anticipation (35 U.S.C. § 102): This patent's focus on silicon carbide devices and gate structures could make it relevant to the broader context of US10998418. Aspects of gate insulation or inter-metal dielectric formation might be generally anticipated, but the specific multi-layer and reflow characteristics of the inter-metal dielectric in US10998418's independent claims would likely remain novel.

13. U.S. Patent No. 9,455,274

    • Full Citation: US 9,455,274 B2
    • Publication/Filing Date: Filed July 28, 2015; Issued September 27, 2016
    • Brief Description: This patent describes methods for forming semiconductor devices with improved contacts and passivation layers.
    • Potential Anticipation (35 U.S.C. § 102): This reference might generally anticipate methods of forming contacts and passivation layers which are components of the overall device structure in US10998418 (claims 1, 13, 40) and fabrication methods (claims 20, 33). However, it is unlikely to disclose the specific inventive elements related to the reflowed and non-reflowable inter-metal dielectric patterns and the use of sacrificial structures for shaping the dielectric.

14. U.S. Patent Application Publication No. 2017/0236894

    • Full Citation: US 2017/0236894 A1
    • Publication/Filing Date: Filed February 17, 2017; Published August 17, 2017
    • Brief Description: This publication relates to semiconductor devices with various dielectric layers for isolation and passivation.
    • Potential Anticipation (35 U.S.C. § 102): This reference could broadly anticipate the use of multiple dielectric layers in semiconductor devices (claims 1, 13, 40). However, the specific combination of reflowable and non-reflowable dielectric materials in an inter-metal dielectric, and the use of sacrificial structures to control the reflow profile, are distinguishing features claimed in US10998418.

15. U.S. Patent No. 9,773,865

    • Full Citation: US 9,773,865 B2
    • Publication/Filing Date: Filed September 2, 2016; Issued September 26, 2017
    • Brief Description: This patent covers silicon carbide semiconductor devices with particular gate structures and dielectric layers.
    • Potential Anticipation (35 U.S.C. § 102): The general subject matter of silicon carbide devices and gate structures makes this reference relevant to US10998418. However, the specific details of the inter-metal dielectric patterns, including the use of both reflowable and non-reflowable materials and sacrificial structures for shaping, are likely novel aspects of US10998418.

16. U.S. Patent No. 9,871,061

    • Full Citation: US 9,871,061 B2
    • Publication/Filing Date: Filed June 23, 2016; Issued January 16, 2018
    • Brief Description: This patent describes methods for fabricating silicon carbide power devices, including steps for forming gate dielectrics and passivation layers.
    • Potential Anticipation (35 U.S.C. § 102): This reference might generally anticipate fabrication methods for silicon carbide power devices, as described in claims 20 and 33. However, the specific techniques for forming a multi-layer inter-metal dielectric with reflowed and non-reflowed components, and especially the use of sacrificial structures to control the reflow process, would distinguish US10998418.

17. U.S. Patent No. 9,935,165

    • Full Citation: US 9,935,165 B2
    • Publication/Filing Date: Filed April 28, 2017; Issued April 3, 2018
    • Brief Description: This patent also focuses on silicon carbide power semiconductor devices with particular dielectric isolation schemes.
    • Potential Anticipation (35 U.S.C. § 102): This patent, in its general scope of silicon carbide power semiconductor devices and dielectric isolation, may touch upon some broad concepts also present in US10998418. However, the specific inventive aspects of US10998418, particularly the multi-layer inter-metal dielectric with reflow and non-reflow components and sacrificial structures, are not likely to be fully anticipated.

18. U.S. Patent No. 9,997,556

    • Full Citation: US 9,997,556 B2
    • Publication/Filing Date: Filed September 29, 2016; Issued June 12, 2018
    • Brief Description: This patent describes silicon carbide power MOSFETs with specific device structures and fabrication methods.
    • Potential Anticipation (35 U.S.C. § 102): This reference, like others focusing on SiC MOSFETs, is relevant to the general field. While it may cover some device structures and fabrication methods, the unique combination of reflowable and non-reflowable dielectric layers in the inter-metal dielectric and the use of sacrificial structures for shaping are key distinctions in US10998418's independent claims.

19. U.S. Patent No. 10,134,888

    • Full Citation: US 10,134,888 B2
    • Publication/Filing Date: Filed June 23, 2017; Issued November 20, 2018
    • Brief Description: This patent relates to silicon carbide semiconductor devices and methods for their manufacture, specifically addressing improved gate structures.
    • Potential Anticipation (35 U.S.C. § 102): This patent's focus on improved gate structures in SiC devices is broadly relevant. However, the specific details of the multi-layer inter-metal dielectric with reflow characteristics and the controlled shaping using sacrificial structures are likely novel aspects claimed in US10998418.

20. U.S. Patent No. 10,217,801

    • Full Citation: US 10,217,801 B2
    • Publication/Filing Date: Filed September 1, 2017; Issued February 26, 2019
    • Brief Description: This patent describes methods for forming dielectric layers in semiconductor devices, potentially including techniques for improving their quality and reliability.
    • Potential Anticipation (35 U.S.C. § 102): This reference might anticipate general methods of forming dielectric layers and improving their properties, which are broad objectives of US10998418. However, the specific combination of reflowable and non-reflowable materials in an inter-metal dielectric and the use of sacrificial structures for profile control are specific inventive elements of US10998418 (claims 20, 33) that are unlikely to be fully disclosed.

21. U.S. Patent Application Publication No. 2019/0067425

    • Full Citation: US 2019/0067425 A1
    • Publication/Filing Date: Filed August 24, 2018; Published February 28, 2019
    • Brief Description: This publication relates to semiconductor devices with inter-metal dielectric layers and methods of forming them, potentially addressing issues like void reduction.
    • Potential Anticipation (35 U.S.C. § 102): This publication is highly relevant as it addresses similar problems to US10998418, specifically the formation of inter-metal dielectric layers and the reduction of voids. It could potentially anticipate aspects of claims 1, 13, and 40 regarding the general structure of inter-metal dielectrics and claims 20 and 33 regarding fabrication methods. The extent of anticipation would depend on whether it explicitly discloses the combination of both non-reflowable and reflowed dielectric patterns, and/or the use of sacrificial structures to control the reflow profile to achieve the specific thickness ratios. This reference, given its later filing date but earlier publication than US10998418's issue date, would be critical in a §102 analysis.

22. U.S. Patent Application Publication No. 2019/0096956

    • Full Citation: US 2019/0096956 A1
    • Publication/Filing Date: Filed September 28, 2018; Published March 28, 2019
    • Brief Description: This publication also discusses semiconductor devices and their fabrication, possibly with a focus on improving dielectric layers and overall device reliability.
    • Potential Anticipation (35 U.S.C. § 102): Similar to US 2019/0067425 A1, this publication is highly relevant due to its focus on semiconductor devices and dielectric layers. It might anticipate aspects of the device structures (claims 1, 13, 40) and fabrication methods (claims 20, 33) in US10998418. A detailed comparison would be needed to determine if it explicitly discloses the inventive elements of US10998418, such as the specific multi-layer inter-metal dielectric composition (reflowable and non-reflowable), the controlled reflow process, or the use of sacrificial structures.

Summary of Most Relevant Prior Art:

The U.S. Patent Application Publications US 2019/0067425 A1 and US 2019/0096956 A1 appear to be the most relevant prior art. These publications directly address methods for forming inter-metal dielectric layers in semiconductor devices and methods for their manufacture, which is the core subject matter of US10998418. Their publication dates (February 28, 2019, and March 28, 2019, respectively) are prior to the issue date of US10998418 (May 4, 2021) and the filing date of US10998418 (May 16, 2019). Therefore, they could potentially anticipate aspects of the independent claims under 35 U.S.C. § 102, depending on the specificity of their disclosures regarding the combination of non-reflowable and reflowed dielectric materials, the controlled reflow process, and the use of sacrificial structures to achieve the improved inter-metal dielectric profiles and performance characteristics claimed in US10998418. A thorough claim-by-claim analysis against the full text of these publications would be necessary to determine the exact extent of anticipation.

Under 35 U.S.C. § 103, a patent claim is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The US10998418 patent itself describes several aspects of the prior art and the problems they entail, which implicitly provides motivation for a PHOSITA to combine or modify existing techniques to arrive at the claimed inventions.

The background of US10998418 details two main prior art approaches for inter-metal dielectric (IMD) patterns in power semiconductor devices, particularly for wide bandgap materials like silicon carbide:

Prior Art Reference 1 (PA1): Conventional Power MOSFET (e.g., FIGS. 1 and 2 of US10998418)

• Teachings: This prior art device includes a semiconductor layer structure, a gate electrode structure, an IMD pattern formed conformally on the gate structure, and a top-side source metallization structure. The IMD typically comprises a non-reflowable dielectric material (e.g., silicon oxide strips).
• Problems (as identified by US10998418): Due to narrow gaps between IMD fingers and sharp (e.g., ~80-90°) angles at the bottom of these gaps, it is difficult to completely fill the gaps with the diffusion barrier layer and source contact metal without forming voids. These voids, combined with potential seams in the IMD, can create pathways for wet etchants or corrosive materials to diffuse and cause electrical short circuits between the gate and source metallization, leading to device failure.

Prior Art Reference 2 (PA2): Power MOSFET with Fully Reflowed Inter-Metal Dielectric (e.g., FIG. 3 of US10998418)

• Teachings: This approach uses a reflowable dielectric material, such as boro-phospho-silicate glass ("BPSG"), for the IMD. After deposition, the material is reflowed at an elevated temperature (e.g., 500-1000°C). The reflow process increases the material's density, reducing or eliminating seams, and surface tension causes the IMD fingers to adopt a rounded (e.g., semi-oval or semi-circular) cross-section. This rounded profile reduces the sharp angles in the gaps, making it easier for subsequent metallization layers to fill without voids.
• Problems (as identified by US10998418): While addressing some issues of PA1, the reflow process leads to a non-uniform thickness of the IMD. The dielectric material becomes significantly thinner at the upper corners of the gate fingers (e.g., region 53 in FIG. 3), making these regions vulnerable to electrical breakdown and gate-to-source short circuits. Additionally, the lateral spreading of the reflowable material during reflow can reduce the width of the gaps between adjacent gate fingers, potentially increasing source contact resistance or leading to new void formation during metallization.

Obviousness Analysis of Independent Claims:

A PHOSITA in semiconductor manufacturing, aware of the respective advantages and disadvantages of PA1 and PA2, would have a clear motivation to combine or modify these known techniques to overcome their identified problems.

Combination 1: PA1 (Non-reflowable IMD) + PA2 (Reflowable IMD) for Multi-Layer Structures

Motivation:
The patent explicitly states the motivation: to achieve the benefits of a fully reflowable IMD (densification, seam elimination, improved gap fill profile) while mitigating its disadvantages (critically thin corners, excessive lateral spread). A PHOSITA would seek to use the robust, uniform thickness provided by a non-reflowable layer (PA1) as a base, and then apply a reflowable layer (PA2) on top to get the desired rounded profile and densification without compromising dielectric strength at critical points.

Claims Rendered Obvious:

• Independent Claim 1 (Device Structure - Multi-layer IMD):

  • This claim describes a device with a wide bandgap semiconductor layer structure, a gate electrode structure, an inter-metal dielectric pattern including both a non-reflowable dielectric material pattern and a reflowed dielectric material pattern, and a source metallization structure. The structural arrangement is conventional.
  • Obviousness: A PHOSITA would combine the non-reflowable dielectric material of PA1 (which provides uniform thickness and good breakdown voltage capability) with the reflowed dielectric material of PA2 (which provides densification, eliminates seams, and improves gap-fill angles). By using the non-reflowable layer as a base, the device can retain sufficient dielectric thickness, particularly at the vulnerable upper corners of the gate fingers, while the reflowed layer provides the desirable rounded profile and reduced seam issues. This directly addresses the stated problems of thin corners in PA2 and poor gap fill/seams in PA1.

• Independent Claim 20 (Fabrication Method - Multi-layer IMD):

  • This claim outlines a method including forming a wide bandgap SLS, a conductive pattern, a non-reflowable dielectric material pattern on the conductive pattern, a reflowable dielectric material layer on the conductive pattern, reflowing the reflowable material, and then forming a source metallization structure on the resulting inter-metal dielectric pattern.
  • Obviousness: The method steps naturally flow from the motivation to create the multi-layer IMD described in Claim 1. A PHOSITA would first form a non-reflowable layer (derived from PA1) for its protective qualities and then deposit and reflow a reflowable layer (derived from PA2) to achieve the improved profile and densification. The patent's FIGS. 6A-6E explicitly illustrate this combination of steps.

• Independent Claim 40 (Device Structure - Two Silicon Oxide Patterns, Ratio Less Than 4-to-1):

  • This claim describes a device with a wide bandgap SLS, a gate electrode structure, an inter-metal dielectric pattern including at least a first silicon oxide pattern and a second silicon oxide pattern of different material, and a source metallization structure. Crucially, the ratio of a maximum thickness to a minimum thickness of the IMD is less than 4-to-1.
  • Obviousness: The motivation for combining a non-reflowable layer (like PA1) with a reflowable layer (like PA2) is precisely to ensure adequate thickness at the "thin upper 'corner' regions" that are vulnerable in PA2. By providing this underlying non-reflowable dielectric, the minimum thickness of the combined IMD is inherently increased. While the maximum thickness might not change significantly or might be reduced for the reflowable layer, the increase in minimum thickness directly results in a lower ratio of maximum to minimum thickness compared to a purely reflowed IMD (PA2), where the minimum thickness is severely compromised. Achieving a more uniform thickness distribution (represented by a ratio less than 4-to-1) is an expected outcome of combining these layers to address the thin corner problem.

Combination 2: PA1 (Conventional MOSFET) + PA2 (Reflowable IMD) + Sacrificial Structures

Motivation:
PA2 (fully reflowed IMD) offers advantages in densification and rounding but suffers from excessive lateral spreading that narrows the gaps. The patent itself identifies this as a problem that can "increase the source contact resistance and/or increase the likelihood that voids form during the deposition of the diffusion barrier layer." A PHOSITA would be motivated to prevent this lateral spreading while still benefiting from reflow. Sacrificial structures, acting as physical barriers or "dams," are a known engineering solution in semiconductor fabrication to limit the flow or spread of materials during processing steps like deposition or reflow.

Claims Rendered Obvious:

• Independent Claim 13 (Device Structure with Vertical Sidewalls):

  • This claim describes a device with a reflowed dielectric material pattern where a lower portion has substantially vertical sidewalls.
  • Obviousness: The problem of lateral spreading in reflowed IMDs (PA2) leading to narrowed gaps would motivate a PHOSITA to employ a known technique for controlling material flow. The use of sacrificial structures (as taught in the patent's own description for this purpose, e.g., "dams to limit the lateral spread of the reflowable dielectric material") positioned in the gaps during reflow would naturally result in a reflowed dielectric pattern having substantially vertical sidewalls in its lower portion, as the dams would physically restrict lateral flow.

• Independent Claim 33 (Fabrication Method - Sacrificial Structures):

  • This claim details a method including forming a wide bandgap SLS, spaced-apart gate fingers, a reflowable dielectric material layer on the gate fingers, forming sacrificial structures in gaps between the gate fingers, reflowing the dielectric material, and forming a source metallization pattern.
  • Obviousness: This method directly implements the solution to the lateral spreading problem of PA2. Given that reflowable materials spread and that physical barriers can control material flow, a PHOSITA would be motivated to form sacrificial structures (e.g., polysilicon dams as suggested by the patent) in the gaps before the reflow step. This would confine the reflowable dielectric material and prevent the undesirable narrowing of the gaps, while still allowing the reflow process to achieve its benefits of densification and surface rounding in the unconstrained upper portions. The patent's FIGS. 9A-9D illustrate this method.