US 9275982

Here's a concise summary of US Patent 9275982:

US Patent 9275982: Method of forming interconnection structure of package structure

• Title: Method of forming interconnection structure of package structure
• Current Assignee: Mare Infinitus Technologies LLC [cite: Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Mare Infinitus Technologies LLC]
• Original Assignee: Delta Electronics Inc [cite: Original Assignee Delta Electronics Inc]
• Inventors: Chia-Yen Lee, Hsin-Chang Tsai, Peng-Hsin LEE
• Filing Date: January 7, 2015 [cite: Filing date 2015-01-07]
• Issue Date: March 1, 2016 [cite: Publication date 2016-03-01]
• Abstract: The patent describes a package structure comprising a first semiconductor device with a first semiconductor substrate and a first electronic device. This first device has a first side and an opposite second side, with at least part of the first electronic device adjacent to the first side. A via-hole passes through the first semiconductor device, having a first opening near the first side. An interconnection structure, including a via structure within the via-hole (not extending beyond the first opening) and a first pad on the first side covering the via-hole, is adjoined to the via structure and electrically connected to the first electronic device. A second semiconductor device is vertically integrated with the first, and includes a second electronic device electrically connected with the first electronic device. [cite: Abstract]

Plain-Language Overview of Independent Claims:

US Patent 9275982 contains only one independent claim, Claim 1.

• Claim 1: A method of forming a package structure comprising:
  This claim outlines a method for creating a semiconductor package with improved interconnections. The method involves several key steps:
  1. Providing a first semiconductor device: Start with a first semiconductor device that has a top (first) side and a bottom (second) side.
  2. Forming a via-hole: Create a hole that goes completely through this first semiconductor device, from the first side to the second side. This hole will have an opening on the first side and another on the second side.
  3. Forming a first pad: Place a conductive pad on the first side of the device, making sure it covers the opening of the via-hole on that side.
  4. Forming a via structure: After the first pad is formed, create a conductive structure inside the via-hole. This via structure is made of a conductive material and connects directly to the first pad.
  5. Vertically integrating with a second semiconductor device: Stack or combine this first semiconductor device (with its newly formed via structure and pad) with a second semiconductor device in a vertical arrangement.

CAFC 2026 Dockets:
As of April 26, 2026, a search of the CAFC 2026 dockets did not reveal any specific cases or litigation directly referencing US patent 9275982. The search results provided general information about CAFC activity in 2026, including summaries of other patent cases, but no mention of this particular patent. Therefore, there is no authoritative information about active litigation concerning this patent in the CAFC dockets for 2026 at this time.