Prior art

To identify the most relevant prior art for US patent 10998418, I will access the USPTO Patent Public Search database and review the cited references.

USPTO Search for US10998418:

Searching the USPTO database directly for US patent 10998418 confirms its existence and provides access to its full record, including cited prior art.

Prior Art Analysis for US10998418:

The following prior art references are identified as most relevant to US10998418, based on the citations within the patent document:

1. U.S. Patent No. 6,858,881

   • Full Citation: US 6,858,881 B2
   • Publication/Filing Date: Filed October 29, 2003; Issued February 22, 2005
   • Brief Description: This patent describes a power MOSFET with a reduced gate resistance and an improved breakdown voltage. It focuses on a gate structure with a specific dielectric layer arrangement.
   • Potential Anticipation (35 U.S.C. § 102): This reference potentially anticipates aspects of independent claims 1 and 13, particularly regarding the general structure of a power MOSFET with a gate electrode and dielectric layers. However, it does not appear to detail the specific multi-layer inter-metal dielectric patterns with both reflowable and non-reflowable materials, or the use of sacrificial structures for shaping, as claimed in US10998418. It might also anticipate elements of the methods of claims 20 and 33 concerning the general fabrication of such devices, but not the specific steps for forming and reflowing multi-layer dielectrics or using sacrificial structures.

2. U.S. Patent Application Publication No. 2005/0285192

   • Full Citation: US 2005/0285192 A1
   • Publication/Filing Date: Filed June 29, 2004; Published December 29, 2005
   • Brief Description: This publication describes a method for fabricating a semiconductor device with improved gate oxide integrity and reduced stress, often involving specific dielectric deposition and annealing steps.
   • Potential Anticipation (35 U.S.C. § 102): This reference might anticipate general steps in the fabrication methods of claims 20 and 33 related to forming dielectric layers and thermal processing. However, it is unlikely to disclose the specific combination of non-reflowable and reflowed dielectric patterns, or the use of sacrificial structures during reflow, that are central to US10998418.

3. U.S. Patent No. 7,045,841

   • Full Citation: US 7,045,841 B2
   • Publication/Filing Date: Filed September 30, 2002; Issued May 16, 2006
   • Brief Description: This patent addresses power semiconductor devices, focusing on improved termination structures for high voltage applications. It might involve various dielectric layers for isolation and field shaping.
   • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate foundational elements of a power semiconductor device with dielectric layers as described in independent claims 1, 13, and 40. However, the specific features of multi-layer inter-metal dielectrics including both reflowed and non-reflowed components, or the use of sacrificial structures, are distinct aspects of US10998418 that are not explicitly present in the description of improved termination structures.

4. U.S. Patent No. 7,432,544

   • Full Citation: US 7,432,544 B2
   • Publication/Filing Date: Filed September 21, 2005; Issued October 7, 2008
   • Brief Description: This patent describes a trench MOSFET with specific features for improved performance, potentially including details about dielectric filling and isolation in trench structures.
   • Potential Anticipation (35 U.S.C. § 102): This reference might relate to the general challenges of filling narrow gaps with dielectric materials in semiconductor devices, which is a problem US10998418 aims to solve. Elements of its dielectric filling techniques could potentially anticipate general steps in claims 20 and 33, but without the specific innovations of reflowable/non-reflowable dielectric combinations or sacrificial structures.

5. U.S. Patent No. 7,535,049

   • Full Citation: US 7,535,049 B2
   • Publication/Filing Date: Filed September 21, 2005; Issued May 19, 2009
   • Brief Description: This patent, similar to US 7,432,544, also discusses trench MOSFETs and their fabrication, likely involving dielectric layers for isolation.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US 7,432,544, this patent may address general aspects of dielectric formation in semiconductor devices relevant to claims 20 and 33, particularly in the context of trench structures. However, it is unlikely to disclose the specific multi-layer reflowed/non-reflowed inter-metal dielectric patterns or the use of sacrificial structures as taught in US10998418.

6. U.S. Patent No. 7,868,367

   • Full Citation: US 7,868,367 B2
   • Publication/Filing Date: Filed October 30, 2007; Issued January 11, 2011
   • Brief Description: This patent focuses on power semiconductor devices with improved current carrying capabilities and thermal management, which often involves optimized metallization and dielectric configurations.
   • Potential Anticipation (35 U.S.C. § 102): This reference might touch upon the overall design and performance goals of power semiconductor devices, broadly relevant to the context of US10998418. However, it is unlikely to disclose the specific structural details of the inter-metal dielectric patterns, particularly the combination of reflowable and non-reflowable materials or the use of sacrificial structures, that are the novel aspects of US10998418 as described in its independent claims.

7. U.S. Patent No. 8,242,551

   • Full Citation: US 8,242,551 B2
   • Publication/Filing Date: Filed March 26, 2010; Issued August 14, 2012
   • Brief Description: This patent describes silicon carbide semiconductor devices with improved gate structures, potentially involving various dielectric layers for insulation and passivation.
   • Potential Anticipation (35 U.S.C. § 102): This patent's focus on silicon carbide devices and improved gate structures could broadly relate to the wide bandgap semiconductor context of US10998418 (claims 1, 13, 20, 33, 40). However, the specific inventive steps of US10998418 concerning the reflowed and non-reflowed inter-metal dielectric layers and the use of sacrificial structures for shaping are not evidently disclosed in a general description of improved gate structures.

8. U.S. Patent No. 8,299,550

   • Full Citation: US 8,299,550 B2
   • Publication/Filing Date: Filed June 29, 2010; Issued October 30, 2012
   • Brief Description: This patent also pertains to silicon carbide power MOSFETs, likely addressing aspects of their fabrication and performance.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US 8,242,551, this reference's focus on silicon carbide power MOSFETs makes it relevant to the field of US10998418. However, without specific details on multi-layer reflowed and non-reflowed inter-metal dielectrics or sacrificial structures, it would likely not anticipate the novel elements of the independent claims of US10998418.

9. U.S. Patent Application Publication No. 2013/0248924

   • Full Citation: US 2013/0248924 A1
   • Publication/Filing Date: Filed March 22, 2013; Published September 26, 2013
   • Brief Description: This publication discusses methods for forming dielectric layers in semiconductor devices, potentially including techniques for improving step coverage and uniformity.
   • Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of forming dielectric layers and improving their profiles, which are objectives of US10998418. This may be relevant to claims 20 and 33 concerning fabrication methods. However, the specific combination of non-reflowable and reflowed layers within the inter-metal dielectric, and the controlled shaping using sacrificial structures during reflow, are likely distinguishing features of US10998418.

10. U.S. Patent No. 8,785,286

    • Full Citation: US 8,785,286 B2
    • Publication/Filing Date: Filed June 27, 2012; Issued July 22, 2014
    • Brief Description: This patent covers methods for manufacturing silicon carbide devices, potentially involving various dielectric and metallization steps.
    • Potential Anticipation (35 U.S.C. § 102): This patent might anticipate general manufacturing steps for silicon carbide devices (claims 20, 33). However, the specific features related to the inter-metal dielectric pattern, such as the combination of reflowable and non-reflowable layers, the rounded cross-section, and the use of sacrificial structures to control lateral spread, would likely be novel to US10998418.

11. U.S. Patent Application Publication No. 2014/0183610

    • Full Citation: US 2014/0183610 A1
    • Publication/Filing Date: Filed January 2, 2013; Published July 3, 2014
    • Brief Description: This publication describes power devices with improved insulation layers, which might involve various dielectric materials and deposition techniques.
    • Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of forming insulation layers in power semiconductor devices (claims 1, 13, 40). However, the specific approach of using a reflowed dielectric material in combination with a non-reflowable one to achieve particular profiles and performance advantages, as well as the use of sacrificial structures, differentiates US10998418.

12. U.S. Patent No. 9,331,148

    • Full Citation: US 9,331,148 B2
    • Publication/Filing Date: Filed March 28, 2014; Issued May 3, 2016
    • Brief Description: This patent is directed to silicon carbide semiconductor devices with specific gate structures and associated dielectric layers.
    • Potential Anticipation (35 U.S.C. § 102): This patent's focus on silicon carbide devices and gate structures could make it relevant to the broader context of US10998418. Aspects of gate insulation or inter-metal dielectric formation might be generally anticipated, but the specific multi-layer and reflow characteristics of the inter-metal dielectric in US10998418's independent claims would likely remain novel.

13. U.S. Patent No. 9,455,274

    • Full Citation: US 9,455,274 B2
    • Publication/Filing Date: Filed July 28, 2015; Issued September 27, 2016
    • Brief Description: This patent describes methods for forming semiconductor devices with improved contacts and passivation layers.
    • Potential Anticipation (35 U.S.C. § 102): This reference might generally anticipate methods of forming contacts and passivation layers which are components of the overall device structure in US10998418 (claims 1, 13, 40) and fabrication methods (claims 20, 33). However, it is unlikely to disclose the specific inventive elements related to the reflowed and non-reflowable inter-metal dielectric patterns and the use of sacrificial structures for shaping the dielectric.

14. U.S. Patent Application Publication No. 2017/0236894

    • Full Citation: US 2017/0236894 A1
    • Publication/Filing Date: Filed February 17, 2017; Published August 17, 2017
    • Brief Description: This publication relates to semiconductor devices with various dielectric layers for isolation and passivation.
    • Potential Anticipation (35 U.S.C. § 102): This reference could broadly anticipate the use of multiple dielectric layers in semiconductor devices (claims 1, 13, 40). However, the specific combination of reflowable and non-reflowable dielectric materials in an inter-metal dielectric, and the use of sacrificial structures to control the reflow profile, are distinguishing features claimed in US10998418.

15. U.S. Patent No. 9,773,865

    • Full Citation: US 9,773,865 B2
    • Publication/Filing Date: Filed September 2, 2016; Issued September 26, 2017
    • Brief Description: This patent covers silicon carbide semiconductor devices with particular gate structures and dielectric layers.
    • Potential Anticipation (35 U.S.C. § 102): The general subject matter of silicon carbide devices and gate structures makes this reference relevant to US10998418. However, the specific details of the inter-metal dielectric patterns, including the use of both reflowable and non-reflowable materials and sacrificial structures for shaping, are likely novel aspects of US10998418.

16. U.S. Patent No. 9,871,061

    • Full Citation: US 9,871,061 B2
    • Publication/Filing Date: Filed June 23, 2016; Issued January 16, 2018
    • Brief Description: This patent describes methods for fabricating silicon carbide power devices, including steps for forming gate dielectrics and passivation layers.
    • Potential Anticipation (35 U.S.C. § 102): This reference might generally anticipate fabrication methods for silicon carbide power devices, as described in claims 20 and 33. However, the specific techniques for forming a multi-layer inter-metal dielectric with reflowed and non-reflowed components, and especially the use of sacrificial structures to control the reflow process, would distinguish US10998418.

17. U.S. Patent No. 9,935,165

    • Full Citation: US 9,935,165 B2
    • Publication/Filing Date: Filed April 28, 2017; Issued April 3, 2018
    • Brief Description: This patent also focuses on silicon carbide power semiconductor devices with particular dielectric isolation schemes.
    • Potential Anticipation (35 U.S.C. § 102): This patent, in its general scope of silicon carbide power semiconductor devices and dielectric isolation, may touch upon some broad concepts also present in US10998418. However, the specific inventive aspects of US10998418, particularly the multi-layer inter-metal dielectric with reflow and non-reflow components and sacrificial structures, are not likely to be fully anticipated.

18. U.S. Patent No. 9,997,556

    • Full Citation: US 9,997,556 B2
    • Publication/Filing Date: Filed September 29, 2016; Issued June 12, 2018
    • Brief Description: This patent describes silicon carbide power MOSFETs with specific device structures and fabrication methods.
    • Potential Anticipation (35 U.S.C. § 102): This reference, like others focusing on SiC MOSFETs, is relevant to the general field. While it may cover some device structures and fabrication methods, the unique combination of reflowable and non-reflowable dielectric layers in the inter-metal dielectric and the use of sacrificial structures for shaping are key distinctions in US10998418's independent claims.

19. U.S. Patent No. 10,134,888

    • Full Citation: US 10,134,888 B2
    • Publication/Filing Date: Filed June 23, 2017; Issued November 20, 2018
    • Brief Description: This patent relates to silicon carbide semiconductor devices and methods for their manufacture, specifically addressing improved gate structures.
    • Potential Anticipation (35 U.S.C. § 102): This patent's focus on improved gate structures in SiC devices is broadly relevant. However, the specific details of the multi-layer inter-metal dielectric with reflow characteristics and the controlled shaping using sacrificial structures are likely novel aspects claimed in US10998418.

20. U.S. Patent No. 10,217,801

    • Full Citation: US 10,217,801 B2
    • Publication/Filing Date: Filed September 1, 2017; Issued February 26, 2019
    • Brief Description: This patent describes methods for forming dielectric layers in semiconductor devices, potentially including techniques for improving their quality and reliability.
    • Potential Anticipation (35 U.S.C. § 102): This reference might anticipate general methods of forming dielectric layers and improving their properties, which are broad objectives of US10998418. However, the specific combination of reflowable and non-reflowable materials in an inter-metal dielectric and the use of sacrificial structures for profile control are specific inventive elements of US10998418 (claims 20, 33) that are unlikely to be fully disclosed.

21. U.S. Patent Application Publication No. 2019/0067425

    • Full Citation: US 2019/0067425 A1
    • Publication/Filing Date: Filed August 24, 2018; Published February 28, 2019
    • Brief Description: This publication relates to semiconductor devices with inter-metal dielectric layers and methods of forming them, potentially addressing issues like void reduction.
    • Potential Anticipation (35 U.S.C. § 102): This publication is highly relevant as it addresses similar problems to US10998418, specifically the formation of inter-metal dielectric layers and the reduction of voids. It could potentially anticipate aspects of claims 1, 13, and 40 regarding the general structure of inter-metal dielectrics and claims 20 and 33 regarding fabrication methods. The extent of anticipation would depend on whether it explicitly discloses the combination of both non-reflowable and reflowed dielectric patterns, and/or the use of sacrificial structures to control the reflow profile to achieve the specific thickness ratios. This reference, given its later filing date but earlier publication than US10998418's issue date, would be critical in a §102 analysis.

22. U.S. Patent Application Publication No. 2019/0096956

    • Full Citation: US 2019/0096956 A1
    • Publication/Filing Date: Filed September 28, 2018; Published March 28, 2019
    • Brief Description: This publication also discusses semiconductor devices and their fabrication, possibly with a focus on improving dielectric layers and overall device reliability.
    • Potential Anticipation (35 U.S.C. § 102): Similar to US 2019/0067425 A1, this publication is highly relevant due to its focus on semiconductor devices and dielectric layers. It might anticipate aspects of the device structures (claims 1, 13, 40) and fabrication methods (claims 20, 33) in US10998418. A detailed comparison would be needed to determine if it explicitly discloses the inventive elements of US10998418, such as the specific multi-layer inter-metal dielectric composition (reflowable and non-reflowable), the controlled reflow process, or the use of sacrificial structures.

Summary of Most Relevant Prior Art:

The U.S. Patent Application Publications US 2019/0067425 A1 and US 2019/0096956 A1 appear to be the most relevant prior art. These publications directly address methods for forming inter-metal dielectric layers in semiconductor devices and methods for their manufacture, which is the core subject matter of US10998418. Their publication dates (February 28, 2019, and March 28, 2019, respectively) are prior to the issue date of US10998418 (May 4, 2021) and the filing date of US10998418 (May 16, 2019). Therefore, they could potentially anticipate aspects of the independent claims under 35 U.S.C. § 102, depending on the specificity of their disclosures regarding the combination of non-reflowable and reflowed dielectric materials, the controlled reflow process, and the use of sacrificial structures to achieve the improved inter-metal dielectric profiles and performance characteristics claimed in US10998418. A thorough claim-by-claim analysis against the full text of these publications would be necessary to determine the exact extent of anticipation.