US 9785572

I'll search for information on this specific patent number, including any 2026 litigation activity.

Let me search specifically for the claims text and any CAFC 2026 activity involving this patent.

Let me retrieve the actual claim text for this patent.

US Patent 9,785,572 — Analysis Summary

1. Bibliographic data (from the authoritative patent text and indexed records)

Continuity (an important nuance): The '572 patent is not a simple original filing. Per its own "Priority/Incorporation by Reference" section, it is a continuation of application Ser. No. 14/880,529, filed Oct. 12, 2015 ("Expositive Flash Memory Control"), which in turn claims benefit of provisionals 62/199,969 (Jul. 31, 2015), 62/194,172 (Jul. 17, 2015) and 62/063,357 (Oct. 13, 2014), and is also a continuation-in-part of Ser. No. 14/848,273, filed Sep. 8, 2015 (which claims benefit of provisional 62/048,162, Sep. 9, 2014). This explains the 2014-09-09 priority assumption and the membership in a very large Radian continuation family.

Litigation flag: The Google Patents record carries a "Family has litigation" marker pointing to a Darts-IP worldwide family litigation entry (family 57705973) — see the search results above.

2. Abstract (verbatim)

"This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client."

3. Plain-language overview

Core concept. The patent is about a flash memory controller that can operate in several different control "modes" toward the memory dies — hence "multimodal." The specification (FIG. 1) states the controller includes a mode register or other configuration circuit that, when programmed by the host or pre-programmed in production, lets the device operate in any one of at least four modes:

1. Physical access mode (112) — the controller does little on its own; the host knows the true flash geometry and issues physical block addresses (PBAs). Low latency, but the host must manage wear leveling, garbage collection, bad blocks, scrubbing, etc.
2. Linearly virtualized mode (114) — a conventional FTL/media-management engine hides all geometry behind a linear LBA range. Simple for the host but with unpredictable latency, overprovisioning losses, and large translation tables.
3. Cooperative management mode (116) — the controller exposes real geometry ("geometry export"), including known-defective erase units, and gathers statistics/notifies the host when maintenance is needed; the host schedules maintenance.
4. Hierarchically virtualized mode (118) — the controller exports an idealized "pseudo-physical" geometry, holding erase units (or dies, etc.) in reserve so defective/failing elements are remapped transparently within a die/plane boundary while the host sees a defect-free device.

Because the controller "exposes" hardware in the cooperative mode and "pseudo-exposes" it in the hierarchical mode, the patent refers to an "expositive" or "pseudo-expositive" memory controller.

Addressing mechanism. An incoming LBA is treated as a tuple of hierarchical sub-address fields (e.g., channel, die, erase-unit, page, page-offset). An Address Space Layout (ASL) defines the order and widths of those fields, so sequential LBAs can be spread narrowly/deeply (favoring endurance) or widely (favoring bandwidth). At least one field — typically the erase-unit field — is a virtual address translated to a physical address via a lookup table, guaranteeing the LBA still resolves to the correct physical die/channel while allowing defective or worn erase units to be swapped out. Translation can be done with logic gates and LUTs rather than processor cycles, giving predictable low latency. Block devices (BD0…BD4) are configurable regions with their own LBA ranges, ASLs, and feature settings (read/write caching, multi-page nPa, multi-plane nPl), programmed through block-device configuration registers by a block-device designer/allocator.

Independent claims (important caveat). I was not able to retrieve the verbatim, complete claim set of the '572 patent within this session — the authoritative text I was given is truncated before the claims, and the indexed source returned (Justia) did not include the claim listing. I therefore cannot give you a reliable, literal breakdown of each independent claim, and I will not reconstruct claim language from memory. Based on the title, the specification, and the "Info" metadata (claim-term frequencies: "storage," "maintenance," "translation," "block device," "virtual block," "address"), the independent claims appear to be directed to (a) a memory controller / memory controller IC operable in multiple selectable control modes relative to the memory dies, and/or (b) a configurable, hierarchical-address-virtualization scheme in which at least one hierarchical address field is virtualized and translated within a bounded superior structure. Treat this paragraph as inference only; verify the exact claims directly at the patent's claim section (Google Patents US9785572B1 or USPTO PatentCenter).

4. Litigation / docket status (including 2026)

• No Court of Appeals for the Federal Circuit (CAFC) 2026 docket or appeal was found that is specific to US 9,785,572. I searched CAFC/2026 docket material and found none naming this patent. If a CAFC appeal exists, I could not confirm it.
• The known litigation is Radian Memory Systems LLC v. Samsung Electronics Co., Ltd. and [[Samsung Electronics America](/litigations/by-defendant/Samsung%20Electronics%20America), Inc.](/litigations/by-plaintiff/Samsung%20Electronics%20America%2C%20Inc.), Case No. 2:24-cv-01073-JRG (E.D. Tex.). Notably, the asserted patents in that case are not the '572 patent — they are U.S. Pat. Nos. 11,307,995; 11,347,656; 11,347,657; 11,544,183; 11,681,614; 11,709,772; and 11,740,801. (These are later members of the same Radian family.)
• PTAB: Samsung filed a set of IPRs in 2025 (e.g., IPR2025-01266 on the '183 patent, plus IPR2025-01289, -01321, -01350, -01376, -01377, -01378, etc., all Radian-owned patents). Per the docket records, these were terminated by pre-institution settlement on Dec. 30, 2025, with refund requests/approvals in early January 2026. None of these is IPR against the '572 patent.
• District court posture: Radian moved to dismiss its own E.D. Tex. action (motions in 2025); the docket control order referenced an August 31, 2026 trial setting and claim-construction dates in late 2025/early 2026. A Korean trade report (Jan. 2, 2026) states Samsung notified the court of a final settlement with Radian in the SSD memory patent case.
• ITC: A related report indicates the U.S. International Trade Commission opened an investigation (late 2025) into Samsung (and customers Google and Super Micro) based on a different patent owner (Netlist) — not Radian and not the '572 patent.

5. Uncertainty / verification notes

• Claim text: Not verified (see §3). This is the main gap in this summary.
• "CAFC 2026 docket for 9785572": No such docket was located; absence of evidence here is not proof of non-existence.
• Assignee chain: Records show both "Radian Memory Systems, LLC" and "Radian Memory Systems, Inc." with reassignments (2016 name change; May 20, 2024 assignment back to RADIAN MEMORY SYSTEMS LLC). Confirm the current owner of record at USPTO Assignment.
• Identity caution (per your strict rule): I have interpreted the identifier strictly as US 9,785,572 B1. Do not conflate it with same-family Radian patents (e.g., 9,542,118; 9,588,904; 10,642,705; 10,642,748; 10,977,188; 11,321,237; the Radian patents actually asserted against Samsung), or with the unrelated patent whose abstract/search snippets referenced an "8,787,060"/"9,858,215" family (those belong to different owners/parties).

If you want the verbatim independent claims, the fastest authoritative source is the "Claims" section of Google Patents US9785572B1 or the USPTO PatentCenter full-text for application 15/074,778 — I can summarize them precisely once that text is supplied.

I'll search for litigation involving US patent 9785572.

Let me refine my searches to specifically target US 9,785,572 and any earlier Radian litigation.

Let me check the Unified Patents litigation portal and search specifically for the '572 patent.

Bottom line

Based on my searches, I could not confirm any litigation that specifically names US Patent No. 9,785,572 ("Memory controller with multimodal control over memory dies") as an asserted patent. I did not find a docket, complaint, PTAB petition, or news item identifying the '572 patent as a patent-in-suit in any case. I want to be explicit about this rather than stretch a "similar number" into a match, per your instruction.

A few important nuances and caveats:

What I did find (family-level, not patent-level)

The Google Patents page for US 9,785,572 carries a "Family has litigation" flag with a Darts-IP link labeled "First worldwide family litigation filed":

• https://patents.google.com/patent/US9785572/en

This signals that the patent family (i.e., the '572 patent's relatives/continuations sharing priority) has been litigated — but a family flag is not evidence that the '572 patent itself was asserted. US 9,785,572 is the parent of a very large continuation family (e.g., US 10,642,505; 10,642,748; 10,977,188; 11,321,237; 11,321,559; etc., all listed on the Google Patents page). The Darts-IP flag likely derives from activity in that extended family.

The closest actual litigation (same owner, same technology) — NOT confirmed to include '572

Radian Memory Systems LLC v. Samsung Electronics Co., Ltd. and [[Samsung Electronics America](/litigations/by-defendant/Samsung%20Electronics%20America), Inc.](/litigations/by-plaintiff/Samsung%20Electronics%20America%2C%20Inc.)

• Court/Jurisdiction: U.S. District Court for the Eastern District of Texas, Marshall Division (Judge Rodney Gilstrap)
• Case No.: 2:24-cv-01073-JRG
• Filed: December 23–24, 2024 (complaint filed 12/24/2024, 347 pages, asserting seven U.S. patents)
• Status: Radian moved for a preliminary injunction (later withdrawn 7/11/2025); Radian then filed an opposed motion to dismiss without prejudice (7/17/2025); Samsung asserted invalidity counterclaims. Case was still being litigated as of the most recent documents I saw.
• Sources: https://dockets.justia.com/docket/texas/txedce/2:2024cv01073/[235038](/patent/235038) ; https://www.mintz.com/sites/default/files/media/documents/2025-07-11/Radian_PI%20Motion_0.pdf

Which patents were actually in that case: The public documents I retrieved repeatedly identify the '183 patent (US 11,544,183), the '656 patent, and the '772 patent as asserted patents. I could not find US 9,785,572 named among the seven asserted patents in the materials I could retrieve. So while the litigation is by the same owner (Radian Memory Systems LLC) in the same technology space, I cannot honestly report the '572 patent as a patent-in-suit there.

Related PTAB proceeding (also not '572-specific to my knowledge):

• Samsung Electronics Co., Ltd. v. Radian Memory Systems LLC, IPR2025-01266 (P.T.A.B.)
  • Filed July 9, 2025; Terminated – Settled, Dec. 30, 2025
  • Source: https://www.docketalarm.com/cases/PTAB/IPR2025-01266/Samsung_Electronics_Co._Ltd._v._Radian_Memory_Systems_LLC/
  • Note: The record indicated this was "one of seven petitions challenging patents-at-issue in a co-pending district court action." I did not confirm which specific patent(s) each petition challenged, so I cannot tie IPR2025-01266 to the '572 patent.

Recommendation / how to verify definitively

Because search coverage of docket details is incomplete and the '572 patent may or may not be among the seven asserted patents:

1. Pull the full complaint (Dkt. 1) and the P.R. 3-1 infringement contentions in 2:24-cv-01073-JRG to see the complete list of asserted patents.
2. Check PACER / CourtListener for that docket and search the full text for "9,785,572."
3. Query the Unified Patents litigation portal by patent number: https://portal.unifiedpatents.com/litigation/caselist

If you can share the list of the seven asserted patents in Radian v. Samsung (or grant me access to the full complaint text), I can confirm whether '572 is among them. As of now, the accurate answer is: no litigation specifically involving US 9,785,572 is confirmed; only closely related family/same-owner litigation exists.

I'll research this. Let me start with targeted searches.

Let me verify whether 9,785,572 itself has ever been the subject of a PTAB challenge, and check for older Radian litigation.

Proceedings overview

Zero AIA trial proceedings on file for US 9,785,572. The USPTO Open Data Portal returns no IPR, PGR, or CBM petitions against this patent, and my independent web search found none — not in the Samsung v. Radian IPR wave of 2025, not in any earlier Radian-related filing. Bottom line for a defendant: there is no PTAB history to lean on. No claims have been canceled, no claim has been construed by the Board, no estoppel applies to anyone, and the patent's validity has never been tested in an AIA trial. That cuts both ways — you have a clean slate, but you also have no free win and no roadmap from a prior panel. The absence is itself a signal: the '572 has apparently never been asserted in litigation, which is why no one has bothered to petition against it.

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No proceedings to report

There is no ### {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry for this patent, because no such proceeding exists. I will not invent one.

Verification note: I confirmed this two ways. (1) The structured ODP block in this task states no AIA trial proceedings are indexed. (2) Targeted searches for "9785572" / "9,785,572" against PTAB, Docket Alarm, and the Samsung–Radian docket surfaced no petition, decision, or termination involving this patent number. The only "9,785,572"-adjacent hit was an unrelated Spanish administrative gazette entry (an expedient number collision), which I disregarded.

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Adjacent activity — same patent family, different patents (flag, don't conflate)

The '572 is not an orphan. It sits in Radian Memory Systems' Cooperative Flash Management family (it is a continuation of application Ser. No. 14/880,529, "Expositive Flash Memory Control," which itself continues-in-part from 14/848,273). Radian's later descendants of that family were asserted and were petitioned in 2025. If you are evaluating this portfolio, know that these exist — but none of them touches US 9,785,572:

Context that matters to a defendant:

• These are the "Asserted Patents" in Radian Memory Systems LLC v. Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc., No. 2:24-cv-01073-JRG (E.D. Tex., Judge Rodney Gilstrap), filed 2024-12-24. The full asserted set is 11,307,995; 11,347,656; 11,347,657; 11,544,183; 11,681,614; 11,709,772; and 11,740,801 — seven patents. The '572 is not among them.
• Seven petitions were filed challenging those seven asserted patents (Samsung's own briefing describes "one of seven petitions challenging patents-at-issue in a co-pending district court action"). I have only positively identified four proceeding numbers; I did not locate the other three docket numbers before my search budget ran out. I am not guessing at them.
• Every identified IPR terminated by pre-institution settlement. IPR2025-01266 is the cleanest record: Joint Motion to Terminate (2025-12-19), Board "DECISION Settlement Prior to Institution of Trial 37 C.F.R. § 42.74" (2025-12-30), fee refund approved (2026-01-09). That means no institution decision, no FWD, no estoppel attached, and no claim-level ruling on the '183. Radian had filed a robust POPR (2025-10-20) and a Discretionary Denial Brief (2025-09-18) invoking Fintiv, the March 26, 2025 PTAB workload memo, and "settled expectations" — Samsung's opposition is in the record (Paper 15/16). None of this produced a merits ruling.
• Reported panel member in the 2025 Samsung–Radian IPRs: APJ Kalyan K. Deshpande (per third-party PTAB trackers for IPR2025-01289 and IPR2025-01321). Petitioner counsel appears as Glass, James et al.; Patent Owner counsel as Weatherwax, Kenneth et al. Treat counsel/panel attributions as secondary-source and confirm on PTAB E2E before relying on them.

Why this matters for the '572: the 2025 IPR wave shows Samsung was willing to petition against Radian's Cooperative Flash Management family but settled the whole set quickly (and Radian, per its own filings, moved to dismiss the district court case on 2025-07-17 while Samsung pressed its invalidity counterclaims). It also shows the family's later claims were the commercially relevant targets. The '572 was left untouched.

• No defensive aggregator. I found no Unified Patents (or similar) filing against any Radian patent. The petitioner in every located proceeding is Samsung.

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Strategic summary

Claim status of US 9,785,572: entirely UNTESTED. There is no canceled claim and no sustained claim, because no tribunal has ruled. Every claim stands as issued, with the statutory presumption of validity, unweakened by any adverse PTAB decision. Contrast that with the sibling patents: even there, the 2025 IPRs all settled before institution, so nothing in the family has been invalidated at the Board either. The practical significance is that a defendant facing the '572 today has to build an invalidity case from scratch — there is no prior FWD to adopt, no Board claim construction to borrow, and no petitioner-funded expert work you can free-ride on.

Estoppel landscape: none exists. Because nothing was instituted against the '572, 35 U.S.C. § 315(e)(2) estoppel is not triggered against anyone. No petitioner or privy is barred from raising any ground. That is good news if you are the defendant — you face no residual estoppel risk and no "reasonably could have raised" trap. It also means there is no In re Verlander / SAS / Commil-style procedural posture to exploit. Caution for you, not against you: if you do petition, you must decide whether to also raise grounds in the district court case, because once an IPR is instituted and reaches FWD, § 315(e)(2) will bar you and your privies from asserting in the district court any ground you raised or reasonably could have raised. Given that Samsung's own petitions here settled pre-institution, a potential defendant should weigh whether a well-funded IPR is actually worth the estoppel cost — settlement before institution leaves you cleaner than a loss.

Pattern signals. (1) No serial petitioner on the '572 — the patent has never attracted a petition. (2) The patent owner (Radian) is engaged in active, aggressive enforcement, having sued Samsung in E.D. Tex. on a seven-patent campaign, then moved to dismiss its own case on 2025-07-17 (Samsung resisted in part to preserve invalidity counterclaims). Radian filed a preliminary-injunction motion (withdrawn 2025-07-11 after Samsung produced evidence undercutting irreparable harm), and the USPTO/DOJ filed a Statement of Interest (2025-06-24) on the irreparable-harm standard. This is a sophisticated, well-counseled NPE-style campaign — expect a future assertion of additional family members, including possibly the '572. (3) The 2025 IPRs all settled pre-institution, suggesting both sides preferred the district court (or a global resolution) over a Board merits fight.

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Recommended next steps

If you are a defendant and want to attack the '572:

• Confirm the negative on PTAB E2E first. Search PTAB E2E and Docket Alarm for "9,785,572" before you rely on the absence — I checked web sources and the ODP block, but a live E2E query is the authoritative confirm.
• You must build the invalidity case yourself. No FWD exists to cite, so there is nothing to quote. Do not link to an FWD for this patent — there isn't one. Any brief asserting "claims 1–5 were canceled" would be a fabrication.
• Use the sibling IPRs as a free lead-generation source. Samsung's petitions and Radian's POPRs in IPR2025-01266/01289/01321 identify the art the parties actually fought over — e.g., U.S. Pat. Pub. 2013/0205102 (Ellis), U.S. Pat. No. 7,739,444 and 7,984,233 (Sinclair), and U.S. Pat. Pub. 2008/0189485A1 (cited by Samsung as prior art disclosing "cooperative flash management"). Those references target sibling claims, not the '572's claims, so you must chart them against the '572's own limitations — but they are the obvious place to start, and Radian has already litigated their teachings.
• Watch the priority date. The '572 has a 2014-09-09 priority date (per Google Patents, assuming the '14/848,273 provisional chain) and a 2016-03-18 filing date, so it is a post-AIA patent. Expect the fight over whether the '572's claims get the earlier priority date or only their 2016 filing date — Samsung made exactly that § 112 written-description/priority attack against the asserted family members, and it will be equally available against the '572. A later effective date expands your prior-art window significantly.
• Vehicle guidance. PGR is time-barred; CBM is not available (this is a flash-memory architecture patent, not a "covered business method" financial-product patent). IPR is your vehicle.
• Note the § 315(b) one-year clock. If Radian ever serves the '572 on you, your petition deadline is one year from service — diarize it immediately.

If you are evaluating settlement or licensing:

• Because no proceeding exists, there is no PTAB leverage on either side for this patent. The '572's value is whatever the district court (or a jury) says it is. That argues for a strong, early invalidity record in litigation rather than a PTAB hedge, and it means a demand letter citing the '572 is backed by a clean, unadjudicated patent — you cannot yet tell the patent owner its claims are dead.

If proceedings later appear (monitoring): PTAB's statutory deadline is one year from institution to FWD (35 U.S.C. § 316(a)(11)), with the institution decision due six months from the petition's filing/accord date. Institutions/dates must be verified on PTAB E2E when they happen — none are pending now.

Explicit confidence note: I have high confidence that no AIA trial proceeding exists against US 9,785,572 as of 2026-10-01, based on the ODP block plus searches. I have lower confidence on the complete set of 2025 Samsung–Radian proceeding numbers (I positively identified four of the reported seven) and on the exact FWD-outcome claims for the sibling patents beyond what is quoted above — those settled pre-institution and produced no merits rulings. Where I could not verify, I have said so rather than fill the gap.

I'll research this patent's assignment record, litigation history, and corporate status. Let me run several searches in parallel.

Let me dig into the specific USPTO assignment records and correspondent details.

Ownership Analysis — US 9,785,572 B1 ("Memory controller with multimodal control over memory dies")

Data-access note (read first). I could retrieve the fact of this patent's post-issuance assignment events from the authoritative patent record (Google Patents legal-events section, which mirrors USPTO assignment data), but the reel/frame numbers and the correspondent-of-record for each recording could not be retrieved with the tools available in this session. I have deliberately left those fields marked [NOT RETRIEVED — VERIFY] rather than guess. Every date, conveyance type, assignor and assignee below is drawn from the patent record and litigation filings; the reel/frame and correspondent fields are the one part of the requested output I cannot substantiate, and I say so where they would appear.

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Inventors

The filing is a continuation of Ser. No. 14/880,529 ("Expositive Flash Memory Control"), itself a CIP-chain descendant of Ser. No. 14/848,273, with a 2014-09-09 priority date. All determinable inventors were Radian insiders — this is an employer-owned portfolio, not a group of independent inventors. (Radian's own marketing/litigation narrative and contemporaneous trade coverage — e.g. StorageNewsletter, June 2015 — confirm Lercari, Jadon, Kuzmin and Chen as Radian personnel.)

Unusual-pattern check — inventors departing within 12 months: NOT present. Lercari, Jadon and Kuzmin remained Radian principals for years (the litigation record shows Jadon still filing declarations in 2025). One early Radian co-founder/CTO — Richard M. Mathews — had departed before this filing, but he is not a named inventor here, so this is not a departure signal for this patent.

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Original assignee

Radian Memory Systems, LLC (per the patent record), which became Radian Memory Systems, Inc. by change of name recorded 2016-11-08, and (as of 2024) RADIAN MEMORY SYSTEMS LLC, a Texas LLC.

• Primary line of business: enterprise data-center flash storage / software-defined flash. Radian commercialized "Symphonic" Cooperative Flash Management (host/controller co-designed flash management that removes the conventional FTL) and shipped purpose-built SSD hardware (e.g. RMS-250 2.5" NVMe SSD; later RMS-325/RMS-350 with Zoned Namespaces). It won the Flash Memory Summit "Most Innovative Technology" award in 2015 and raised roughly $7.7M across angel/seed rounds (last round ~2017).
• Did it ship a product embodying the claims? Yes, historically. Radian sold Symphonic-based SSDs, and its own later litigation filings describe working system-level implementations of the patented technology. This matters directly to the verdict (see below).
• Current status: private; no funding since ~2017; the product business appears effectively dormant. The entity is actively enforcing its portfolio (see NPE signals). Low-confidence, non-English secondary reporting (ipdaily.co.kr) indicates Samsung notified the court of a settlement with Radian around Aug–Sep 2025; I could not independently verify that in a primary source. Not observed: any bankruptcy, dissolution, or assignment to a third-party NPE.

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Assignment timeline

The patent record shows three post-filing ownership events. Reel/frame and correspondent are not available to me and must be pulled from Assignment Center; I am not inventing them.

1. 2016-03-18 (event date per patent legal events; execution date not separately verified) / recorded ~2016-03-18 — Reel [NOT RETRIEVED — VERIFY]/****

   • Conveyance: Assignment of assignors' interest (inventor → company)
   • Assignor: Robert Lercari; Alan Chen; Mike Jadon; Craig Robertson; Andrey V. Kuzmin
   • Assignee: Radian Memory Systems, LLC
   • Correspondent: [NOT RETRIEVED — VERIFY]
   • Context: Internal — inventors assign their rights to the operating company that employed them (ordinary employer-owned portfolio).

2. 2016-11-08 / recorded 2016-11-08 — Reel [NOT RETRIEVED — VERIFY]/****

   • Conveyance: Change of Name (no change in beneficial ownership)
   • Assignor: Radian Memory Systems, LLC
   • Assignee: Radian Memory Systems, Inc.
   • Correspondent: [NOT RETRIEVED — VERIFY]
   • Context: Internal corporate formality — LLC converted/renamed to "Inc."; ownership unchanged.

3. 2024-05-20 / recorded 2024-05-20 — Reel [NOT RETRIEVED — VERIFY]/****

   • Conveyance: Assignment of assignors' interest
   • Assignor: Radian Memory Systems, Inc.
   • Assignee: RADIAN MEMORY SYSTEMS LLC
   • Correspondent: [NOT RETRIEVED — VERIFY]
   • Context: Internal restructuring / re-domiciliation — the same business assigns to a successor LLC. Court filings identify the assignee as "a Texas limited liability company having its place of business at 6275 West Plano Parkway, Suite 500, Plano, Texas 75093" — a real commercial office address, not a registered-agent mailbox. This is not an evident shell-entity transfer to a third-party licensing vehicle.

No other assignments are recorded. Notably, the chain contains no transfer to an outside acquirer, no security interest, no license-and-sue back, and no defensive aggregator. The chain terminates at the original operating company family.

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Timeline diagram

timeline
    title Ownership of US 9785572
    2014 : Priority application filed Sep 2014
    2016 : Application filed 18 Mar 2016
         : Inventors assign to Radian Memory Systems LLC
         : Name change to Radian Memory Systems Inc
    2017 : Patent granted 10 Oct 2017
    2024 : Assigned to Radian Memory Systems LLC
         : Samsung suit filed in East Texas Dec 2024

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NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. The only outbound-looking transfer (2024-05-20, Inc. → LLC) runs to a same-business successor with the identical corporate name stem, and the assignee litigates from a real office at 6275 West Plano Parkway, Suite 500, Plano, TX (stated in Samsung's counterclaims, E.D. Tex. 2:24-cv-01073). No "IP/Licensing/Ventures" suffix, no registered-agent service address, no third-party acquirer appears in the chain.

2. Known asserter in chain — NOT PRESENT on the named lists; UNclear as a category. No Acacia, Marathon, IV, Mosaid/Conversant, Vringo, Pendrell, Round Rock, etc. appears. However, Radian is a repeat patent plaintiff (seven asserted patents in the Dec 2024 Samsung action) and Unified Patents maintains a Radian Memory Systems LLC patent portal page, and Samsung has filed multiple IPRs against the family (e.g. IPR2025-01266). That is enforcement activity, but I found no RPX/Unified "high-frequency NPE plaintiff" listing naming Radian. Mark unclear on the list-match element.

3. Repeat correspondent across the chain — UNKNOWN / NOT RETRIEVED. This is the single most informative field requested and I could not retrieve any correspondent of record for any of the three recordings. The one chain-of-title signature my searches surfaced — "/Gregory M. Howison, Reg.," dated October 5, 2021, in USPTO PTAB petition materials — appeared in unrelated filing text and I could not tie it to Radian. Do not treat it as a Radian correspondent. Action item: pull the correspondent for all three recordings from Assignment Center; recurrence of one attorney across the 2016 LLC→Inc. and the 2024 Inc.→LLC links would be the key check.

4. Cascading transfers — NOT PRESENT. Three events over ~8 years, two of which are a name change (#2) and a same-family conversion (#3). No chained LLC-to-LLC-to-LLC hopscotch in <24 months.

5. Pre-litigation transfer — BORDERLINE / WEAK. The 2024-05-20 assignment to the Texas LLC precedes the first Samsung complaint (filed 2024-12-23/24, E.D. Tex. 2:24-cv-01073) by about 7 months — just outside the 6-month window, and the assignor and assignee share the same business and principals. Timing is consistent with re-domiciling the owning entity into the filing state, but a 7-month gap and an intra-family transfer make this a weak signal, not a clean pre-suit asset shell transfer. (Caveat: I could not confirm that US 9,785,572 specifically is among the seven patents asserted in that action.)

6. Bankruptcy fire-sale — NOT PRESENT. No Chapter 7/11 filing, no court-supervised sale, no stalking-horse purchaser in the record.

7. Privateering — NOT PRESENT. Radian is enforcing its own patents for its own account; there is no operating-company backer using it as a proxy. (If anything, Radian's narrative is the inverse — it claims the industry, including Samsung, adopted its technology and cut it out.)

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified or OIN. The patent remains assertable in Radian's hands.

Aggravating (contextual, not chain-based) facts worth recording: Radian's own litigation declaration admits "financial challenges," its Swiss/angel funding stopped after 2017, it moved to dismiss its Samsung case without prejudice on 2025-07-17 (Dkt. 69) and reportedly settled soon after. That trajectory — a genuine operating company whose product business failed and which increasingly monetizes patents — is the classic "failed operating company" end of the spectrum, which shades toward NPE behavior even without a shell-transfer chain.

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Verdict

Operating-company assertion.

The recorded chain is entirely internal: inventors → Radian Memory Systems, LLC (2016-03-18), a Change of Name to Radian Memory Systems, Inc. (2016-11-08), and a same-family conversion to RADIAN MEMORY SYSTEMS LLC (2024-05-20, a Texas LLC litigating from a real Plano office) — no third-party NPE, no shell LLC, no defensive aggregator ever takes title. The current assignee is the original operating company, which historically shipped products embodying the claims (Symphonic CFM software and RMS-series SSDs) and is now suing a direct competitor (Samsung) over the portfolio, which is the definition of operating-company assertion rather than NPE acquisition.

Caveat that could move this verdict: Radian is a distressed operating company — no disclosed funding since ~2017, an admitted "financial challenges" record, and a 2025 dismissal/settlement of its lead case. If follow-up work confirms Radian has ceased all product shipment and derives income solely from licensing/enforcement, the correct label shifts to "NPE — moderate confidence." That call turns on two facts I could not retrieve: (a) whether Radian currently ships any product, and (b) the correspondent of record on all three recordings (to test for repeat-player counsel), which is the specific field this analysis was asked to capture and which remains the open item.

Verification links

• USPTO Assignment Center (search by patent number): https://assignmentcenter.uspto.gov/
• Legacy USPTO assignment search: https://assignment.uspto.gov/patent/index.html
• Google Patents legal events for this patent: https://patents.google.com/patent/US9785572/en
• Assignee's own patent list: https://www.radianmemory.com/patents/
• Litigation docket (E.D. Tex. 2:24-cv-01073): https://dockets.justia.com/docket/texas/txedce/2:2024cv01073/[235038](/patent/235038)

I'll research US Patent 9785572 and its prior-art citations. Let me start with targeted searches.

Let me search for the specific citations section and USPTO records.

Let me access the Justia patent page which typically lists all citations.

Scope note on the tool run

I ran targeted searches against the patent record. Before giving results I must be precise about what I could and could not verify, because the strict rule here is to interpret identifiers literally and not fabricate. I was cut off by the tool limit before I could open the full "(56) References Cited" block on the face of US 9,785,572. I therefore will not invent citation entries. Below I separate (a) hard-verified facts, (b) references I actually saw associated with this patent's citation/citing data in search results, and (c) an explicit statement of what is still needed for a complete § 102 mapping.

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1. Patent identified (verified, matches the authoritative text supplied)

This is the correct patent; I did not substitute any neighbor number (e.g., it is not 9,785,570, 9,785,573, etc.).

Continuity (from the patent's own text): a continuation of US 14/880,529 ("Expositive Flash Memory Control," filed 2015-10-12), which claims benefit of provisionals 62/199,969, 62/194,172, 62/063,357, and is a CIP of US 14/848,273 ("Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation"), which claims benefit of provisional 62/048,162. The 2014-09-09 priority date flows through this chain — this date is the critical threshold for any § 102 analysis.

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2. References I could verify as linked to US 9,785,572

A. Documents expressly cited/incorporated by the patent (verified in the patent's own priority/incorporation section)

These are referenced in the "PRIORITY/INCORPORATION BY REFERENCE" paragraph of US 9,785,572 itself:

B. Reference seen in the search-result listing associated with this patent's citation data

C. Documents that cite US 9,785,572 (forward citations — NOT prior art)

These appeared as citing documents and are family/successor Radian filings, not prior art against 9,785,572:

• US 11,537,528 B1 — "Storage system with division based addressing and query based cooperative flash management"
• US 10,977,188 B1 — "Idealized nonvolatile or persistent memory based upon hierarchical address translation"
• US 10,642,748 B1; US 11,321,237 B1; US 11,321,238 B1; US 11,022,386/7 B1; and others in the Radian continuations list.
• US 8,572,311 ("Redundant data storage in multi-die memory systems") lists US 9,785,572 in its "Cited By" table — i.e., 9,785,572 is a citing document relative to it, so US 8,572,311 is a plausible candidate for the (56) list, but I could not verify that it appears on the face of 9,785,572.

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3. What a complete § 102 answer requires (and what is still missing)

A definitive "for each reference, which claim it anticipates" answer requires the literal (56) list printed on the granted patent's front page, plus the claim text of US 9,785,572. Neither was retrievable within this tool session. Concretely, I still need:

1. The (56) U.S. Patent Documents list (granted patent front page or USPTO PatentCenter "References Cited" for application 15/074,778).
2. The (56) Foreign Patent Documents / Non-Patent Literature entries.
3. The full enumerated claims (the abstract and the "dependent … claims 2" hint suggest a claim set in the high-teens/low-twenties; the search snippet references dependent claims, consistent with a claim-1-plus-dependents structure).

Once those are supplied, the § 102 mapping can be done mechanically, because the claim set is structurally narrow and decomposable. Based on the disclosure, the anticipation analysis would turn on these limitation clusters:

• Claim 1-type limitations: a memory controller that (i) subdivides an incoming address into discrete fields corresponding to hierarchical levels (channel/die/erase-unit/page), and (ii) resolves at least one field as a virtual address while preserving boundaries at higher levels. The closest § 102 candidates would be the cooperative-control publication (Ref 1) and multi-array operation art (Ref 2), plus bad-block-remap/FTL art that virtualizes erase units while preserving page ordering.
• Multimodal-control limitations (physical access / linearly virtualized / cooperative / hierarchically virtualized modes, selectable via a mode register): this is the distinguishing feature set. A single-reference § 102 case would require one reference disclosing all four selectable modes with a mode register — none of the verified references does this, so the multimodal claims would more likely be attacked under § 103 (combination), not § 102.
• Block-device-allocation / ASL / subspace limitations: likely to be met only by Radian's own earlier disclosures (Ref 1, Ref 2), which raises common-ownership/§ 102(b)(2)(C) considerations rather than pure anticipation.

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4. Explicit uncertainty statement

• I verified the patent's identity, bibliographic data, priority chain, and the references it incorporates (Refs 1–4 above).
• I did not verify the complete examiner/applicant (56) list, and I will not reconstruct it from memory. The Kim reference (US 2013/0166825 A1) is the only third-party item I actually saw linked to this patent's citation listing, and its classification (cited vs. similar) is unconfirmed.
• I made no assertion that any listed reference anticipates a specific claim; the claim-mapping above is a framework conditioned on obtaining the literal (56) list and claim text.
• If you can paste the (56) "References Cited" block and the claims, I will produce the reference-by-reference table with exact claim numbers and the specific claim elements each reference discloses.

I'll research the prior art landscape for this patent before building the obviousness analysis.

I now have the actual claim text. Let me research the key prior-art references to ground the combinations accurately.

Let me verify whether the claim text I found belongs to the '572 patent specifically (vs. its sibling '118), and check the examiner-cited art.

Obviousness Analysis — US 9,785,572 B1 under 35 U.S.C. § 103

0. Scope, caveats, and one important flag

Before the analysis, three things you should hold in mind, because they bound how much weight the conclusions below can bear:

1. Claim-text provenance (flag / possible contradiction with §3 of the prior summary). The earlier "Patent summary" section asserted that the verbatim claims "could not be retrieved." In this session I did retrieve a full 32-claim set reading on hierarchical sub-address generation via modulo/division. However, the sources I retrieved that set from (Justia, RPX/insight.rpxcorp, patents-review.com, companyprofiles.justatic) label it as the claims of US 9,542,118 B1 ("Expositive flash memory control," application 14/880,529) — the sibling patent, not '572. Because '572 is a continuation of 14/880,529 and shares the identical specification, the '572 claims are likely the same or substantially overlapping, but I could not independently confirm the '572 claim set. Treat the claim mapping below as an analysis of the family's claim set; verify against the '572 "Claims" section before relying on it. This is the single largest uncertainty in this report.

2. The "Prior Art section of this page" was not supplied to me as a discrete block. What I could reconstruct is the Referenced Cited art of record on the family's Google Patents/Justia pages (U.S. patents and publications, plus the NPL list), plus the "Prior art keywords" (block device, address, virtual block, memory controller, flash memory). I could not retrieve the examiner's actual §103 rejections from the 15/074,778 file history. The combinations below are therefore constructed analytically, not quoted from the record.

3. Interpretation rule honored. I treat "9785572" literally as US 9,785,572 B1 and do not conflate it with the sibling '118 or the other Radian family members.

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1. Claims under analysis (representative language)

Independent claim 1 — a flash memory device comprising:

• (a) flash storage whose storage locations sit in hierarchically arranged structural elements (each level above the lowest enables access to a subset of lower levels); and
• (b) a memory controller that, on receiving an incoming address value with a memory access command, generates a plurality of hierarchical sub-address values for the groups of structural elements at their respective levels, including generating at least one sub-address at least in part through a modulo operation returning a remainder of at least a portion of the incoming address divided by a quantity of access-enabled structural elements at that level, at least one of the sub-address values being a virtual address.

Independent claim 14 — as claim 1, but with the lowest level = independently programmable units (pages), a higher level = flash dies, one sub-address = a die address, and a page address generated in dependence on a remainder produced when generating the die address.

Independent claim 30 — as claim 1, but expressly reciting channel / die / erasable-unit / page sub-addresses.

Dependent-claim themes:

• Configurable counts: register-programmable number of dies (2, 18) or channels (3, 19) that sets the divisor for the modulo.
• Per-level translation tables + reserve sets (defect management): 4–6, 13, 15–17, 20–22, 29 — remainder indexes a translation table dedicated to a structural element; access-enabled set + reserve set; substitution for defective element.
• Configurable block devices with parameters in a register: 7–8, 23–24, 31.
• Mode register (the "multimodal" core): 9–11, 25–27 — a register-selectable first mode (successive writes → successive dies) vs. second mode (successive writes → successive programmable units within one die, or successive erasable units within one structural element).

Note the drafting signal: the "modulo operation returning a remainder … divided by a quantity of access-enabled structural elements" appears in all three independent claims. That phrasing is almost certainly the limitation added during prosecution to traverse the art (the file history lists a May 18, 2016 Office Action and a Sept. 16, 2016 supplemental response). That limitation is therefore the crux of any §103 attack.

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2. Effective filing date and level of ordinary skill

• Critical date. The modulo/hierarchical-sub-address disclosure appears in the 14/880,529/14/848,273-family specification (the FIG. 8 "ASL generation / address generation module"). For these claims the effective filing date is at the earliest Sep. 9, 2014 (provisional 62/048,162) and likely Oct. 12, 2015 (14/880,529) or the 2015 provisionals, depending on §112 support. Art published before mid-2015 is safely prior art.
• PHOSITA. A person with a bachelor's degree in EE/CS (or equivalent) and ~3–5 years of experience designing non-volatile-memory controllers, storage firmware, or memory-system address/decode logic, familiar with NAND flash organization (channels/dies/planes/erase units/pages), LBA-to-PBA mapping and spare-block management, and interleaving/address-decoding techniques. (This is the conventional level the art implies; treat as an assumption.)

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3. Prior art of record and closely related art (with reliability markers)

⚠️ Note: US 2014/0215129 and US 9,229,854 share inventors/assignee with '572. Under §102(b)(2)(C)/103(c), commonly owned §102(a)(2) art may be disqualified from use as prior art if the "inventive entity" differences and ownership rules are met. But US 2014/0215129 published 2014‑07‑31 — before the earliest possible critical date — so it is §102(a)(1) prior art regardless of common ownership. That makes it the cleanest primary/secondary reference on the page.

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4. Combinations rendering the claims obvious

Ground A — The core modulo/hierarchical/virtual limitation (claims 1, 12, 14, 28, 30, 32)

Primary: Modular-address-decomposition art (e.g., US 4,189,767's "divide external physical address by M → whole number + residue"; JP 4233213's division of a host address to yield chip index (quotient) and block-address (remainder); US 8,339,865's division/modular-arithmetic pointers).
Secondary: US 2014/0215129 (Kuzmin) — flash controller that maintains per-subdivision state, exposes hierarchical geometry, and lets the host directly specify addresses, with block/defect management.

Why the combination is obvious:

• Element (a) (hierarchy of channels→dies→EUs→pages) is the notorious, well-documented organization of NAND flash and is described in the background of every reference in the field — including '572's own incorporated Kuzmin references (US 9,229,854 expressly discusses dies/planes and addressing restrictions).
• Element (b) (split an incoming address into per-level sub-addresses) is the ordinary function of a memory decode/interleave unit.
• Element (c) (address / N_level, take the remainder) is textbook modular interleaving: rank(field) = (address ÷ stride) mod (count at that level). US 4,189,767 and JP 4233213 show the exact quotient/remainder decomposition to select a module/chip; JP 4233213 even couples the remainder to a logical block address, and US 8,339,865 applies modular arithmetic to a non-power-of-two array (directly anticipating '572's stated handling of non-power-of-two element counts via modulo).
• Element (d) (one sub-address is a virtual address) is the standard LBA→PBA spare/remap mechanism: US 2014/0215129 teaches the controller tracking and remapping physical subdivisions for defect management; classic SSD FTL art (e.g., the Sinclair and Shalvi references of record) does the same.

Motivation: Combining modular rank-decomposition (cheap, gate-level, no big tables) with the flash field's need for defect/wear remapping yields exactly the claimed device. The patent itself touts the benefit — "translation … using logic gates and lookup tables … without requiring processor clock cycles" — i.e., the combination produces the predictable, low-latency result one would expect from combining a divide/modulo decoder with a virtual-addressed flash pool. That is a classic KSR "predictable result / known-technique" rationale.

Ground B — Register-configurable element counts (claims 2, 3, 18, 19)

Primary: any reference teaching a programmable interleave width / number of active channels or banks (common in memory-controller art; the count is a control-register value).
Secondary: US 2014/0215129 / US 9,229,854 (geometry export + addressing restrictions the host/controller must observe).

Motivation: Because the divisor in a modulo-interleave is by definition the "quantity of access-enabled structural elements," making that count programmable (to support devices with different populating/geometry, or to take a die out of service) is an obvious incorporation of a known design variable into a known computation. Claim 2/3's "register, wherein a number … is configurable … such that the modulo … is performed in dependence on the number" is the natural implementation.

Ground C — Per-level translation tables + reserve sets + defect management (claims 4–6, 13, 15–17, 20–22, 29)

Primary: US 2014/0215129 (bad-block/defect management with geometry export; controller-owned remap) and/or US 9,229,854 (host-planned physical placement).
Secondary: the modular-decomposition art of Ground A (the remainder indexes the per-element table).

Motivation: Once the remainder of Ground A produces a logical index into a structural element, the well-known flash practice of keeping a per-die / per-EU spare (reserve) pool and substituting a spare for a defective unit (US 2014/0215129; standard SSD art) is a mere substitution of one known defect-management mechanism for another, with the predictable advantage of preserving the host's idealized, defect-free view. Claims 5/6/13/21/22/29 (substitution of a spare erase unit/page/die for a defective one) map directly onto this.

Ground D — Configurable block devices with stored parameters (claims 7–8, 23–24, 31)

Primary: NVM Express namespaces (NPL) and configurable-virtual-device art (e.g., US 2011/0296133 Flynn-type "present a customized virtual device" teachings — unverified this session).
Secondary: US 2014/0215129/US 9,229,854 (per-region parameters).

Motivation: Presenting multiple independent logical address ranges with per-range parameters is the express purpose of NVMe namespaces and virtual-device layers; adding a "register storing parameters per configurable block device" to the hierarchical-modulo controller is an obvious application of a known interface convention.

Ground E — The "multimodal" mode register (claims 9–11, 25–27)

Primary: multi-array/interleave art (US 9,229,854) teaching placement of successive writes across dies vs. within a die.
Secondary: configurable stripe/interleave-granularity practice (RAID stripe sizing; NAND interleave granularity).

Motivation: The patent itself frames the choice as a bandwidth-vs-endurance tradeoff (wide striping = bandwidth; narrow/deep striping = fewer EUs touched = endurance). A PHOSITA seeking either more bandwidth or more endurance would predictably expose a register bit selecting "spread across dies" vs. "pack within a die." Claims 9/10/11's two-mode register is the routine automation of that design choice. This is the strongest pure-obviousness theory against the "multimodal" concept.

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5. Why a PHOSITA would combine (unifying rationale)

• Same field, same problem, overlapping disclosures. All references are flash/SSD storage controllers addressing bandwidth, wear, and defect management; the '572 specification's own background recites this exact problem space.
• Reasonable expectation of success. Modular decomposition is deterministic, gate-level arithmetic (the patent concedes this); combining it with flash spare/remap and namespace config produces predictable, low-latency behavior — the stated goal of the art.
• Known-technique substitution. Divide/remainder interleaving, per-element spare pools, and configurable logical devices were each independently known; combining them requires no unexpected result.

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6. The strongest non-obviousness positions (what a patentee/valuer must weigh)

1. The "modulo, per hierarchical level, on the access-enabled element count" is arguably specific. The art of record may show division for a single level (chip select) but not a uniform, per-level modulo recursion applied to derive each of channel/die/EU/page sub-addresses from a single incoming value. If no single reference or combination teaches doing the modulo at every hierarchical level, claims 1/12/28/32 have a genuine gap.
2. Confinement of virtualization inside a superior boundary. '572 emphasizes that a virtualized erase-unit field is guaranteed to resolve within the LBA-specified die/channel. Prior art §102(e) references (US 2014/0215129) allow broader remap; the bounded virtualization (defect management without breaking intra-level boundaries) may be an argued distinction.
3. The combination of mode-register "wide vs. deep" writing with per-level hash-free modulo decomposition may not be squarely taught together.
4. Prosecution history estoppel / allowance signal. The claims apparently issued after adding the modulo limitation, implying the examiner found the art of record silent on it. That is meaningful — but only as to that art; §103 can still be met by art the examiner did not cite (e.g., US 4,189,767, JP 4233213, US 8,339,865, which are not on the page but are squarely in the field).

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7. Verification gaps and recommended next steps

1. Confirm the '572 claim set directly (Google Patents "Claims" for US9785572B1 / USPTO PatentCenter for 15/074,778). This report cannot be finalized until the true '572 claims are confirmed — do not treat the mapping above as literal '572 claim language.
2. Pull the 15/074,778 file history (the May 18, 2016 and Sept. 16, 2016 papers) to learn the examiner's actual cited art and the applicant's arguments — the real §103 posture turns on that record, not on my reconstruction.
3. Verify the "unverified" cited references (US 7,815,489; 7,860,122; 8,024,545; 8,572,331; 2011/0296133; 2013/0297852; 2014/0122781; 2009/0271562) before relying on any of them in a validity position — I did not confirm their disclosures this session and will not assert them.
4. Resolve the common-ownership/§103(c) question for the Kuzmin references (US 2014/0215129, US 9,229,854): the 2014 publication is §102(a)(1) art regardless, but the patent/§102(a)(2) route needs an ownership analysis.

Bottom line: On the record I could reconstruct, the strongest §103 case is Ground A (modular interleave art) + US 2014/0215129, with dependent-claim features supplied by the standard flash defect-management and NVMe-namespace art. The "multimodal" feature (Ground E) is the most vulnerable to a KSR-style obviousness attack as a routine bandwidth/endurance design choice. However, because the '572 claim text and the examiner's actual rejections are not yet verified, these conclusions are analytical hypotheses to be validated against the file history, not settled validity opinions.