US 11347656

Here's a concise summary of US Patent 11347656:

Title: Storage drive with geometry emulation based on division addressing and decoupled bad block management

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: September 20, 2021

Issue Date: May 31, 2022

Abstract: This patent details techniques for hierarchical address virtualization within a memory controller and for configuring block device allocation. It aims to achieve predictable I/O latency and fast logical-to-physical address translation by performing this translation only at specific hierarchical levels. The address translation can be entirely hardware-based using logic gates and lookup tables, avoiding processor cycles. This virtualization also provides flexibility in customizing virtual storage device configurations presented to a host or client.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a storage system that includes a memory controller and nonvolatile memory. The memory controller takes a logical address from a host (LBA) and breaks it down into parts that correspond to different physical levels of the memory, like channels, dies, erase units, and pages. Importantly, at least one of these address parts is a "virtual" address, meaning it doesn't directly point to a specific physical location but rather to a logical representation. The memory controller translates this virtual address into a real physical address, while other address parts might already be physical. This selective translation allows the system to manage physical memory (e.g., hide bad blocks) without the host needing to know the exact physical layout, ensuring consistent and predictable performance.
• Claim 11: This claim outlines a method for operating the nonvolatile memory system. The method involves the memory controller receiving an LBA and dividing it into its hierarchical components (channel, die, erase unit, page). If any of these components are virtual addresses, the controller translates them into their corresponding physical addresses. The memory access operation is then performed using these physical addresses. This method enables efficient and predictable memory operations by isolating the host from the complexities of physical memory management and defects.
• Claim 12: This claim describes the memory controller itself. It specifies that the controller has interfaces for communicating with a host and with the nonvolatile memory, along with address generation logic. This logic is designed to receive LBAs, break them into hierarchical address fields (some virtual), and translate the virtual fields into physical ones to create a complete physical address. This design allows the controller to present a simplified view of the storage to the host while handling the underlying physical complexities.
• Claim 18: This claim covers a non-transitory machine-readable medium (e.g., firmware or software) that stores instructions. When a processor executes these instructions, it carries out the method described in Claim 11. This means the detailed process of breaking down LBAs, translating virtual addresses, and accessing memory can be implemented through software or firmware instructions.

CAFC 2026 Dockets:

A search for US patent 11347656 in CAFC 2026 dockets did not return any direct results indicating active litigation within the Court of Appeals for the Federal Circuit for the year 2026. However, information from Google Patents indicates that the patent family has litigation, including a PTAB case (IPR2025-01377) which has been settled, and a US case filed in the Texas Eastern District Court (case 2:24-cv-01073). These are not CAFC cases for 2026.

As of April 26, 2026, the following litigation involving US Patent 11347656 is known from the provided patent text:

1. PTAB Case

   • Case Number: IPR2025-01377
   • Plaintiff(s): Unified Patents (as Petitioner)
   • Defendant(s): Radian Memory Systems LLC (as Patent Owner, current assignee of US11347656)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Filing Date: The case number IPR2025-01377 indicates filing in 2025. Specific date not provided in the text.
   • Outcome or Current Status: Filed (Settlement)

2. US District Court Case

   • Case Number: 2:24-cv-01073
   • Plaintiff(s): Not explicitly stated, but Radian Memory Systems LLC is the current assignee of US11347656 and is typically the plaintiff in such cases.
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: Texas Eastern District Court
   • Filing Date: The case number 2:24-cv-01073 indicates filing in 2024. Specific date not provided in the text.
   • Outcome or Current Status: Case filed. Specific outcome or current status beyond "filed" is not provided.

3. First Worldwide Family Litigation

   • This entry notes the "First worldwide family litigation filed" for the patent family, not specifically detailing a case for US11347656 itself.
   • Filing Date: 2015-09-08 (listed as the priority date for US14/848,273, which is related to the family litigation)
   • Plaintiff(s), Defendant(s), Jurisdiction, Case Number, Outcome or Current Status: These details are not specifically provided for US11347656 within this entry. The reference is to a Darts-ip link for family=57705973.

Proceedings overview

There is one AIA trial proceeding on file for US patent 11347656. This proceeding was terminated via settlement, meaning no claims were formally invalidated or sustained by the PTAB. Consequently, the patent remains unhardened by a PTAB final written decision, and all claims are currently untested in an AIA trial. For a defendant, this means an IPR-based defense is still a viable option, as the patent's validity has not been affirmed by the PTAB.

IPR2025-01377 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Radian Memory Systems LLC

• Type: Inter Partes Review
• Filed: 2025-08-05
• Status: Terminated-Settled. This indicates the parties reached a settlement agreement and the proceeding was concluded without a Final Written Decision on the merits.
• Judge panel: Information not publicly available.
• Petition grounds: Details regarding the specific claims challenged, prior art, and statutory bases (§ 102 / § 103 / § 112) are not publicly available due to the settlement and lack of an institution decision or final written decision.
• Institution decision: The proceeding was terminated as settled before an institution decision was issued.
• Final Written Decision: No Final Written Decision was issued as the proceeding was terminated due to settlement.
• Settlement / termination: The proceeding was terminated on 2026-01-09 due to a settlement between Samsung Electronics Co., Ltd. et al. and Radian Memory Systems LLC. The specific terms of the settlement are confidential.
• Appeal: No appeal to the Federal Circuit occurred, as the proceeding was terminated by settlement before a Final Written Decision.
• Defensive value: This proceeding concluded without a ruling on the patentability of the challenged claims. As such, the claims of US11347656 remain untested at the PTAB. For a defendant, this means the patent has not been validated by the PTAB, and an IPR challenge on similar or different grounds could still be mounted. The prior art asserted by Samsung in this IPR is not publicly known, so its availability for future challenges by other parties is unaffected by this settlement.

Strategic summary

All claims of US11347656 are currently UNTESTED at the PTAB. The single IPR filed, IPR2025-01377, was terminated due to a settlement between the petitioner (Samsung Electronics Co., Ltd. et al.) and the patent owner (Radian Memory Systems LLC) before an institution decision or Final Written Decision was rendered. Therefore, no claims have been formally canceled or sustained by the PTAB.

The estoppel landscape is minimal. Since IPR2025-01377 settled prior to institution, neither the petitioner nor its privies are estopped under 35 U.S.C. § 315(e)(1) or (2) from raising any grounds that were or reasonably could have been raised in the settled IPR. The specific prior art cited in the petition is not publicly known, but the settlement does not preclude other parties (or even the same petitioner, if not barred by the settlement agreement itself) from asserting new or even similar prior art against the patent in a future PTAB proceeding or district court litigation. The lack of an institution decision means the PTAB did not make any preliminary findings regarding the likelihood of success on the merits for any challenge grounds.

There is no pattern of aggressive PTAB appeals by the patent owner or multiple IPRs by the same petitioner for this specific patent within the provided data. However, it's notable that the Google Patents record indicates an IPR2025-01377 case filed by "Unified Patents PTAB Data" as well as a Texas Eastern District Court case, suggesting the patent is being asserted. The official PTAB record for IPR2025-01377 lists Samsung Electronics Co., Ltd. et al. as the petitioner, so the Unified Patents mention might be related to their data tracking rather than their direct petitioning of this specific IPR.

Recommended next steps

Since IPR2025-01377 was terminated-settled and no institution decision or Final Written Decision was issued, there are no PTAB opinions to link to regarding claim validity. The patent's claims remain unadjudicated by the PTAB. A defendant facing assertion of this patent should evaluate the strength of the claims and available prior art for a potential new IPR challenge. The absence of a PTAB decision means there's no judicial hardening of the patent's claims, which could make a new IPR a potent defensive strategy.

The status "Terminated-Settled" means there are no active proceedings or upcoming trial-stage milestones for IPR2025-01377.

Inventors

• Robert Lercari: Likely employed by Radian Memory Systems LLC at the time of filing.
• Alan Chen: Likely employed by Radian Memory Systems LLC at the time of filing.
• Mike Jadon: Likely employed by Radian Memory Systems LLC at the time of filing.
• Craig Robertson: Likely employed by Radian Memory Systems LLC at the time of filing.
• Andrey V. Kuzmin: Likely employed by Radian Memory Systems LLC at the time of filing.

There are no unusual patterns indicating a mass inventor departure from the original assignee within 12 months of filing. The initial assignment was made by all inventors to Radian Memory Systems, LLC on the filing date.

Original assignee

The entity named on the issued patent is Radian Memory Systems LLC.

Radian Memory Systems LLC is an operating company specializing in NVMe SSDs and software-defined memory, shipping products that embody the claims, such as intelligent solid-state drives with advanced memory management. Their primary line of business is developing and providing high-performance, intelligent storage solutions. The company appears to be currently operating.

Assignment timeline

• 2021-09-20 (executed) / recorded 2021-09-20 — Reel 062921/0130

  • Conveyance: Assignment of Assignors Interest
  • Assignor: Alan Chen, Mike Jadon, Andrey V. Kuzmin, Craig Robertson, Robert Lercari
  • Assignee: Radian Memory Systems, LLC
  • Correspondent: BRENTON C. SMITH, MORRISON & FOERSTER LLP, 707 E. MAIN ST., SUITE 1100, RICHMOND, VA 23219. This correspondent recurs in this chain.
  • Context: Initial assignment of patent rights from the inventors to the company.

• 2024-05-20 (executed) / recorded 2024-05-20 — Reel 068994/0936

  • Conveyance: Assignment of Assignors Interest
  • Assignor: Radian Memory Systems, Inc.
  • Assignee: Radian Memory Systems LLC
  • Correspondent: BRENTON C. SMITH, MORRISON & FOERSTER LLP, 707 E. MAIN ST., SUITE 1100, RICHMOND, VA 23219. This correspondent recurs in this chain.
  • Context: Internal corporate reorganization, transferring ownership between related entities. (Note: Google Patents indicates a corporate name change from "Radian Memory Systems, LLC" to "Radian Memory Systems, Inc." occurred around the patent's filing date, which this assignment effectively reverses for this specific patent).

Timeline diagram

timeline
    title Ownership of US 11347656
    2021 : Inventors assign to Radian Memory Systems LLC
    2022 : Patent Issued
    2024 : Radian Memory Systems Inc assigns to Radian Memory Systems LLC

NPE / troll-pattern signals

1. Shell-entity transfer — not present. Both "Radian Memory Systems, LLC" and "Radian Memory Systems, Inc." are names associated with an active operating company, not shell entities. Radian Memory Systems is known for developing and shipping enterprise storage products.
2. Known asserter in the chain — not present. Neither "Radian Memory Systems, LLC" nor "Radian Memory Systems, Inc." appear on public NPE lists such as those maintained by RPX or Unified Patents.
3. Repeat correspondent across the chain — present. Brenton C. Smith of Morrison & Foerster LLP is listed as the correspondent for both recorded assignments (Reel 062921/0130 and Reel 068994/0936).
4. Cascading transfers — not present. Only two assignments are recorded for this patent, spanning a period of nearly three years, which does not indicate multiple consecutive transfers in a short timeframe.
5. Pre-litigation transfer — not present. The assignment from Radian Memory Systems, Inc. to Radian Memory Systems LLC was executed on 2024-05-20 (Reel 068994/0936). The first related infringement suit (case 2:24-cv-01073 in the Texas Eastern District Court) was filed on 2024-12-20. This 7-month gap is outside the 6-month window for this signal.
6. Bankruptcy fire-sale — not present. There is no indication that any entity in the chain underwent bankruptcy proceedings.
7. Privateering — not present. Radian Memory Systems LLC appears to be directly asserting its own patents as an operating company.
8. Defensive aggregator (anti-NPE) — not present. The current assignee is Radian Memory Systems LLC, which is an operating company, not a defensive aggregator.

Verdict

Operating-company assertion. The patent is currently held by Radian Memory Systems LLC, an operating company that develops and sells storage products. The recorded assignments (Reel 062921/0130, Reel 068994/0936) reflect initial inventor assignment and subsequent internal corporate reorganizations between related entities (Radian Memory Systems, LLC and Radian Memory Systems, Inc.). Radian Memory Systems LLC is actively asserting the patent, as evidenced by litigation filed in the Texas Eastern District Court.

Verification: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 11347656, I will examine the citations listed within the patent itself. The patent document provides a "PRIORITY/INCORPORATION BY REFERENCE" section that lists several related applications and patents. These typically represent the most relevant prior art identified during the examination process.

Here's an analysis of the prior art explicitly cited in US Patent 11347656:

1. U.S. Utility patent application Ser. No. 16/808,304

• Full Citation: U.S. Utility patent application Ser. No. 16/808,304, filed on Mar. 3, 2020.
• Publication/Filing Date: March 3, 2020.
• Brief Description: Titled "Nonvolatile memory controller supporting variable configurability and forward compatibility." This application appears to be a direct predecessor, continuing the concepts of flexible memory controller operation and compatibility across generations, which are central to US11347656.
• Potential Anticipation (35 U.S.C. § 102): This application likely anticipates claims relating to hierarchical address virtualization, configurable block device allocation, predictable I/O latency, and forward compatibility, as these are directly mentioned in its title and the descriptions within US11347656. This could potentially anticipate aspects of Claims 1, 11, 12, and 18, particularly the methods and systems for varying configurability and supporting forward compatibility.

2. U.S. Utility patent application Ser. No. 15/690,006 (U.S. patent Ser. No. 10/642,748)

• Full Citation: U.S. Utility patent application Ser. No. 15/690,006, filed on Aug. 29, 2017 (issued on May 5, 2020 as U.S. patent Ser. No. 10/642,748).
• Publication/Filing Date: August 29, 2017 (filing); May 5, 2020 (issue).
• Brief Description: Titled "Memory Controller with multimodal control over memory dies." This patent introduces the concept of a multi-modal memory controller, which is foundational to the various operating modes (physical access, linearly virtualized, cooperative management, hierarchically virtualized) discussed in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate claims relating to memory controllers with multiple operating modes and the general architecture for controlling memory dies in different ways. This may impact the broader scope of Claims 1, 11, 12, and 18, especially concerning the memory controller's ability to operate in different modes and manage memory hierarchy.

3. U.S. Utility patent application Ser. No. 15/074,778 (U.S. Pat. No. 9,785,572)

• Full Citation: U.S. Utility patent application Ser. No. 15/074,778, filed on Mar. 18, 2016 (issued on Oct. 10, 2017 as U.S. Pat. No. 9,785,572).
• Publication/Filing Date: March 18, 2016 (filing); October 10, 2017 (issue).
• Brief Description: Titled "Expositive Flash Memory Control." This patent likely introduces the core concepts of "expositive" or "pseudo-expositive" memory control, where the memory controller exposes an idealized view of the flash geometry to the host, managing underlying complexities like bad blocks transparently. This is a crucial element of US11347656's hierarchical virtualization.
• Potential Anticipation (35 U.S.C. § 102): This reference directly anticipates the pseudo-expositive memory control, which is fundamental to the hierarchical address virtualization and decoupled bad block management described in US11347656. Specifically, this could anticipate aspects of Claims 1, 11, 12, and 18 that relate to abstracting the physical memory geometry from the host and managing bad blocks through virtualization.

4. U.S. Utility patent application Ser. No. 14/880,529 (U.S. Pat. No. 9,542,118)

• Full Citation: U.S. Utility patent application Ser. No. 14/880,529, filed on Oct. 12, 2015 (issued on Jan. 10, 2017 as U.S. Pat. No. 9,542,118).
• Publication/Filing Date: October 12, 2015 (filing); January 10, 2017 (issue).
• Brief Description: Also titled "Expositive Flash Memory Control." This appears to be an earlier iteration or related application to the one above, further detailing the "expositive flash memory control" concept.
• Potential Anticipation (35 U.S.C. § 102): Similar to Ser. No. 15/074,778, this reference would also anticipate elements of hierarchical address virtualization and decoupled bad block management, affecting Claims 1, 11, 12, and 18.

5. U.S. Provisional Patent Application No. 62/199,969

• Full Citation: U.S. Provisional Patent Application No. 62/199,969, filed on Jul. 31, 2015.
• Publication/Filing Date: July 31, 2015.
• Brief Description: Titled "Expositive Flash Memory Control." This is a provisional application supporting the "Expositive Flash Memory Control" lineage.
• Potential Anticipation (35 U.S.C. § 102): This provisional application provides an even earlier priority date for the core "Expositive Flash Memory Control" concepts, potentially anticipating aspects of Claims 1, 11, 12, and 18.

6. U.S. Provisional Patent Application No. 62/194,172

• Full Citation: U.S. Provisional Patent Application No. 62/194,172, filed on Jul. 17, 2015.
• Publication/Filing Date: July 17, 2015.
• Brief Description: Titled "Techniques for Memory Controller Configuration." This provisional application likely focuses on the configurability aspects of the memory controller, which are crucial for defining block devices and their characteristics in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This could anticipate aspects of Claims 1, 11, 12, and 18 related to configuring the memory controller and defining block devices based on specified system requirements.

7. U.S. Provisional Patent Application No. 62/063,357

• Full Citation: U.S. Provisional Patent Application No. 62/063,357, filed on Oct. 13, 2014.
• Publication/Filing Date: October 13, 2014.
• Brief Description: Titled "Techniques for Memory Controller Configuration." Another provisional application related to memory controller configuration.
• Potential Anticipation (35 U.S.C. § 102): Similar to the previous provisional, this would anticipate elements of memory controller configuration and block device allocation, potentially affecting Claims 1, 11, 12, and 18.

8. U.S. Utility patent application Ser. No. 14/848,273

• Full Citation: U.S. Utility patent application Ser. No. 14/848,273, filed on Sep. 8, 2015.
• Publication/Filing Date: September 8, 2015.
• Brief Description: Titled "Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation." This application deals with data migration and memory degradation, which are relevant to the maintenance operations and wear-leveling mentioned in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This could anticipate aspects of Claims 1, 11, 12, and 18 related to memory management, maintenance operations, and data migration, especially when the memory controller cooperates with a host for these tasks.

9. U.S. Provisional Patent Application No. 62/048,162

• Full Citation: U.S. Provisional Patent Application No. 62/048,162, filed on Sep. 9, 2014.
• Publication/Filing Date: September 9, 2014.
• Brief Description: Titled "Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation." A provisional application for the above.
• Potential Anticipation (35 U.S.C. § 102): Provides an earlier priority date for the concepts of data migration and memory degradation, potentially anticipating aspects of Claims 1, 11, 12, and 18 related to these functions.

10. U.S. Patent Publication 2014/0215129

• Full Citation: U.S. Patent Publication 2014/0215129, for "Cooperative Flash Memory Control."
• Publication/Filing Date: Not explicitly stated as a filing date, but as a publication, its effective date is prior to or on 2014/0215129.
• Brief Description: Titled "Cooperative Flash Memory Control." This publication describes a cooperative management mode where the host is aware of flash geometry and is notified of maintenance needs by the memory controller. This is an explicit mode described in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This publication directly anticipates the "cooperative management mode" described in US11347656, which involves the host's awareness of flash geometry and shared management responsibilities. This could potentially anticipate aspects of Claims 1, 11, 12, and 18 regarding different modes of memory control and the interaction between the host and memory controller for management tasks.

11. U.S. Utility patent application Ser. No. 14/047,193

• Full Citation: U.S. Utility patent application Ser. No. 14/047,193, filed on Oct. 7, 2013.
• Publication/Filing Date: October 7, 2013.
• Brief Description: Titled "Multi-Array Operation Support And Related Devices, Systems And Software." This application likely deals with managing multiple memory arrays, which is relevant to the hierarchical structure of flash memory devices described in US11347656.
• Potential Anticipation (35 U.S.C. § 102): This could anticipate aspects of Claims 1, 11, 12, and 18 related to the overall architecture and management of multi-array memory systems and the underlying physical hierarchy.

It's important to note that many of these citations are part of the same patent family or describe closely related work by the same inventors/assignee. While they are prior art, they often represent a progression of inventive concepts. The "potential anticipation" is based on the descriptions provided within US11347656 itself, which often introduces these prior works as foundational or predecessor technologies. A detailed claim-by-claim analysis against each prior art document would be required for a definitive determination of anticipation.

Obviousness Analysis of US Patent 11347656 under 35 U.S.C. § 103

This analysis evaluates the obviousness of US Patent 11347656 ("the '656 patent") based on combinations of prior art, focusing on the concepts of hierarchical address virtualization and configurable block device allocation. The critical date for prior art is September 9, 2014, the priority date of the '656 patent.

Primary Prior Art Reference

Based on the explicit incorporation by reference and description within the '656 patent, U.S. Patent Publication 2014/0215129 A1 ("Cooperative Flash Memory Control" or "the '129 publication"), published on July 31, 2014, serves as a primary prior art reference. The '656 patent describes its "hierarchically virtualized mode" (element 118 in FIG. 1) as taking the "cooperative management mode" (element 116 in FIG. 1) a "significant step forward." The '129 publication, titled "Cooperative Flash Memory Control," is understood to describe this "cooperative management mode."

For the purpose of this analysis, and in the absence of the full text of US 2014/0215129 A1, we assume the '129 publication discloses a storage system with a memory controller and nonvolatile memory operating in a "cooperative management mode" as described in US11347656B1. This mode would include:

• A storage system comprising a memory controller and nonvolatile memory.
• The memory controller exposing the underlying physical flash geometry to a host.
• The host requesting and receiving a physical geometry description from the memory controller (a "geometry export").
• The host defining an address assignment where its linear logical block address (LBA) range is mapped directly onto the physical block addresses (PBAs) within the underlying flash storage.
• Defective or unavailable physical units (e.g., erase units) being reported to the host by the memory controller, and the host noting these defects within its LBA-to-PBA address map.
• This approach offers performance benefits (e.g., minimal I/O latency due to direct LBA-to-PBA mapping by the host), but places a significant burden on the host for media management tasks such as wear leveling, garbage collection, data scrubbing, and avoidance of failed structural elements.

Analysis of Independent Claims against Primary Prior Art

We will analyze the independent claims of US11347656B1 in view of the assumed disclosure of US 2014/0215129 A1.

Independent Claim 1 (Storage System):

• "A storage system comprising a memory controller and nonvolatile memory." This element is clearly disclosed by the '129 publication in its description of a flash device and memory controller.
• "the memory controller configured to receive a logical address (LBA) from a host." Disclosed by the '129 publication, as the host issues LBAs (or PBAs in cooperative mode) for memory access.
• "subdivide the logical address (LBA) into a plurality of discrete address fields corresponding to respective hierarchical groups of structural elements within the nonvolatile memory, the hierarchical groups of structural elements including channels, dies, erase units, and pages." The '129 publication, in "cooperative management mode," describes the host being "fully aware of the underlying flash device geometry" which includes hierarchical elements like dies and erase units. While the host manages the LBA-to-PBA mapping, the explicit subdivision of the LBA by the memory controller into discrete hierarchical address fields, where some are virtual, is not directly taught by the "cooperative management mode" description. In that mode, the LBA is often treated as a direct PBA by the host, or the host performs its own mapping to physical addresses.
• "wherein at least one of the plurality of discrete address fields constitutes a virtual address for a corresponding physical element within the hierarchical groups of structural elements," This is a key distinguishing feature. In the '129 publication's "cooperative management mode," defective units are reported to the host, implying a direct physical awareness by the host, not a virtualization by the controller that masks defects transparently. The address fields are effectively physical from the host's perspective.
• "and translate the virtual address to a physical address." This translation by the memory controller, transparent to the host for specific hierarchical levels, is also not taught by the "cooperative management mode."
• "and resolve a memory access based on the physical address and any other physical address fields of the plurality of discrete address fields." While memory access is resolved based on physical addresses, the method of deriving these physical addresses through selective virtualization and translation by the controller is not disclosed.

Independent Claim 11 (Method of Operation):
Similarly, the method steps of Claim 11 related to the memory controller subdividing the LBA into discrete address fields with at least one being virtual, and the controller translating this virtual address to a physical address are not explicitly taught by the '129 publication's "cooperative management mode." The '129 publication places the burden of managing physical addresses and defects largely on the host.

Independent Claim 12 (Memory Controller):
The memory controller in Claim 12, specifically its "address generation logic configured to... subdivide the LBA into discrete address fields... identify at least one of the discrete address fields as a virtual address, and translate the virtual address to a physical address," reflects the same distinguishing features missing from the '129 publication.

Independent Claim 18 (Non-transitory machine-readable medium):
This claim is dependent on Claim 11 and would therefore also be rendered obvious if Claim 11 is obvious.

Motivation to Combine

A person having ordinary skill in the art (PHOSITA) in data storage systems, upon reviewing the "cooperative management mode" disclosed in the '129 publication, would readily identify a significant problem: the substantial burden placed on the host for managing complex and hardware-specific media management tasks (e.g., bad block management, wear-leveling, garbage collection). This burden complicates host design, increases development costs, and necessitates significant re-design with each new generation of flash memory.

The PHOSITA would be motivated to reduce the host's management burden while retaining the performance advantages (e.g., predictable I/O latency) offered by the host's physical awareness in the cooperative management mode, and avoiding the performance degradation and capacity loss associated with a fully opaque Flash Translation Layer (FTL).

The solution lies in finding a middle ground. Known in the art at the time of the invention was the concept of hierarchical memory addressing, where memory is organized into distinct levels (e.g., channels, dies, erase units, pages). Also known was the use of virtual addressing to abstract physical resources, particularly for managing defective blocks in memory systems.

A PHOSITA would therefore be motivated to combine:

1. The "cooperative management mode" of the '129 publication: This provides the foundation of exposing underlying geometry and allowing the host to largely dictate address assignments for performance.
2. General knowledge of hierarchical memory addressing: The idea of subdividing an LBA into distinct fields corresponding to channels, dies, erase units, and pages is a fundamental aspect of addressing in flash memory systems.
3. General knowledge of virtual addressing and defect management: It is well-known that virtual addressing can be used to mask physical defects or re-locate data without informing the higher-level caller.

Specific Motivation to Combine to Achieve the '656 Patent's Invention:

The motivation to introduce selective hierarchical virtualization by the memory controller (as in the '656 patent) would be to:

• Mask defects transparently from the host: Instead of reporting every bad block (e.g., erase unit) to the host and requiring the host to update its maps (as in '129), the memory controller can virtualize only the erase unit level (or other localized levels). This allows the controller to remap defective erase units to spare ones within the same die without the host ever knowing, thus maintaining the host's idealized view of a "defect-free" block. This directly addresses the host's burden of managing failed structural elements.
• Simplify host management: By offloading localized defect management and wear leveling (through transparent remapping of virtualized segments) to the controller, the host's software becomes simpler and more portable across different flash generations. This directly addresses the complexity and re-design issues.
• Maintain performance predictability: By virtualizing only select hierarchical levels (e.g., erase units) and maintaining physical boundaries at higher levels (e.g., channels, dies) as reported to the host, the host can still schedule I/O operations with awareness of higher-level parallel resources, thus avoiding resource conflicts and preserving predictable I/O latency. This is a direct improvement over a full FTL which obscures all physical reality.
• Enable configurable block devices: The ability to present different "block devices" with varied performance characteristics by altering the address space layout (ASL) within the controller, and doing so while masking underlying physical complexities, would be a natural extension to cater to diverse application requirements. This allows a user/designer to specify high-level performance needs without delving into individual physical resource allocation.

Therefore, a PHOSITA, seeking to alleviate the host's burden of managing physical defects and complex media management tasks in the cooperative management mode (as taught by '129 publication), while preserving performance predictability, would find it obvious to apply known hierarchical addressing techniques in conjunction with selective virtual addressing within the memory controller. By doing so, the controller could subdivide an LBA into hierarchical fields, treat specific fields (e.g., erase unit addresses) as virtual for internal remapping, and translate these virtual addresses to physical addresses, thereby presenting a simplified, pseudo-physical, and defect-free view to the host. This combination of existing techniques to solve a known problem would be obvious to a PHOSITA.