US 11347656

Here's a concise summary of US Patent 11347656:

Title: Storage drive with geometry emulation based on division addressing and decoupled bad block management

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: September 20, 2021

Issue Date: May 31, 2022

Abstract: This patent details techniques for hierarchical address virtualization within a memory controller and for configuring block device allocation. It aims to achieve predictable I/O latency and fast logical-to-physical address translation by performing this translation only at specific hierarchical levels. The address translation can be entirely hardware-based using logic gates and lookup tables, avoiding processor cycles. This virtualization also provides flexibility in customizing virtual storage device configurations presented to a host or client.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a storage system that includes a memory controller and nonvolatile memory. The memory controller takes a logical address from a host (LBA) and breaks it down into parts that correspond to different physical levels of the memory, like channels, dies, erase units, and pages. Importantly, at least one of these address parts is a "virtual" address, meaning it doesn't directly point to a specific physical location but rather to a logical representation. The memory controller translates this virtual address into a real physical address, while other address parts might already be physical. This selective translation allows the system to manage physical memory (e.g., hide bad blocks) without the host needing to know the exact physical layout, ensuring consistent and predictable performance.
• Claim 11: This claim outlines a method for operating the nonvolatile memory system. The method involves the memory controller receiving an LBA and dividing it into its hierarchical components (channel, die, erase unit, page). If any of these components are virtual addresses, the controller translates them into their corresponding physical addresses. The memory access operation is then performed using these physical addresses. This method enables efficient and predictable memory operations by isolating the host from the complexities of physical memory management and defects.
• Claim 12: This claim describes the memory controller itself. It specifies that the controller has interfaces for communicating with a host and with the nonvolatile memory, along with address generation logic. This logic is designed to receive LBAs, break them into hierarchical address fields (some virtual), and translate the virtual fields into physical ones to create a complete physical address. This design allows the controller to present a simplified view of the storage to the host while handling the underlying physical complexities.
• Claim 18: This claim covers a non-transitory machine-readable medium (e.g., firmware or software) that stores instructions. When a processor executes these instructions, it carries out the method described in Claim 11. This means the detailed process of breaking down LBAs, translating virtual addresses, and accessing memory can be implemented through software or firmware instructions.

CAFC 2026 Dockets:

A search for US patent 11347656 in CAFC 2026 dockets did not return any direct results indicating active litigation within the Court of Appeals for the Federal Circuit for the year 2026. However, information from Google Patents indicates that the patent family has litigation, including a PTAB case (IPR2025-01377) which has been settled, and a US case filed in the Texas Eastern District Court (case 2:24-cv-01073). These are not CAFC cases for 2026.