Invalidity dossier
US 11544183
Nonvolatile memory controller host-issued address delimited erasure and memory controller remapping of host-address space for bad blocks
Current assignee: Radian Memory Systems LLC
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Here's a concise summary of US patent 11544183:
Title: Nonvolatile memory controller host-issued address delimited erasure and memory controller remapping of host-address space for bad blocks
Assignee: Radian Memory Systems LLC
Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
Filing Date: 2020-08-19
Issue Date: 2023-01-03
Abstract: A memory controller for a nonvolatile memory stores specific information for multiple subdivisions of the memory, making this data available to a host to help manage the memory. The host uses this information to issue commands that directly specify physical addresses for operations like writing, thereby reducing the need for the memory controller to perform complex address translation. The memory controller can still handle remapping for bad blocks on a limited basis, and this remapping is transparently managed and eventually consolidated by the host through other operations like garbage collection, ensuring the host maintains direct physical addressing. This cooperative approach aims to improve control and data bandwidth, minimize write amplification, and lead to more consistent latency, making nonvolatile memory more suitable for various storage systems.
Independent Claims Overview:
- Claim 1 (Method Claim): This claim describes a method for a memory controller to cooperatively manage a nonvolatile memory with a host. The method involves the memory controller storing data about each physical subdivision of the memory (like an erase unit or page) and making this data accessible to the host. The host then uses this information to directly issue commands specifying physical addresses for memory operations. If a write error occurs, the memory controller can remap the data to an available memory space and update its internal metadata, ensuring the host is eventually informed to update its own translation tables and avoid the bad block in future writes. This remapping by the controller is limited and self-correcting over time as the host performs other memory management tasks.
- Claim 11 (Memory Controller Claim): This claim describes a memory controller that manages a nonvolatile memory. It includes storage to keep information for each physical subdivision of the memory and logic to provide this information to a host. The host then sends commands directly addressing physical memory locations. The memory controller's logic is also configured to detect write errors, remap data from bad physical locations to available ones, and update its internal metadata to reflect these changes. This remapping is designed to be self-limiting, eventually leading to the host updating its own address translations to exclude the bad blocks.
- Claim 16 (Non-transitory Computer Readable Medium Claim): This claim covers a non-transitory computer-readable medium (e.g., software or firmware) that contains instructions. When these instructions are executed by a host, they cause the host to interact with a memory controller and nonvolatile memory in a cooperative manner. This involves the host receiving information about memory subdivisions from the controller, using that information to directly address physical memory locations for operations, and processing notifications from the controller about remapped bad blocks. The host then updates its own address translations to account for these remapped blocks, ensuring future access avoids them.
USPTO and CAFC Docket Search:
- USPTO: US patent 11544183 was issued on January 3, 2023, and is currently active. Its application number is US16/997,471, filed on August 19, 2020. The current assignee is Radian Memory Systems LLC.
- CAFC 2026 Dockets: A review of CAFC dockets for 2026, specifically looking for patent 11544183, did not yield any direct results indicating scheduled cases or litigation involving this specific patent number in the provided search snippets. However, the Google Patents information for US11544183 does note that there is ongoing litigation related to this patent family, including a PTAB case IPR2025-01266 filed (Settlement) and a US case filed in the Texas Eastern District Court (case 2:24-cv-01073). These cases are not directly found in the CAFC 2026 May schedule.
Generated 5/19/2026, 12:49:09 PM