US 11544183

Here's a concise summary of US patent 11544183:

Title: Nonvolatile memory controller host-issued address delimited erasure and memory controller remapping of host-address space for bad blocks

Assignee: Radian Memory Systems LLC

Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews

Filing Date: 2020-08-19

Issue Date: 2023-01-03

Abstract: A memory controller for a nonvolatile memory stores specific information for multiple subdivisions of the memory, making this data available to a host to help manage the memory. The host uses this information to issue commands that directly specify physical addresses for operations like writing, thereby reducing the need for the memory controller to perform complex address translation. The memory controller can still handle remapping for bad blocks on a limited basis, and this remapping is transparently managed and eventually consolidated by the host through other operations like garbage collection, ensuring the host maintains direct physical addressing. This cooperative approach aims to improve control and data bandwidth, minimize write amplification, and lead to more consistent latency, making nonvolatile memory more suitable for various storage systems.

Independent Claims Overview:

• Claim 1 (Method Claim): This claim describes a method for a memory controller to cooperatively manage a nonvolatile memory with a host. The method involves the memory controller storing data about each physical subdivision of the memory (like an erase unit or page) and making this data accessible to the host. The host then uses this information to directly issue commands specifying physical addresses for memory operations. If a write error occurs, the memory controller can remap the data to an available memory space and update its internal metadata, ensuring the host is eventually informed to update its own translation tables and avoid the bad block in future writes. This remapping by the controller is limited and self-correcting over time as the host performs other memory management tasks.
• Claim 11 (Memory Controller Claim): This claim describes a memory controller that manages a nonvolatile memory. It includes storage to keep information for each physical subdivision of the memory and logic to provide this information to a host. The host then sends commands directly addressing physical memory locations. The memory controller's logic is also configured to detect write errors, remap data from bad physical locations to available ones, and update its internal metadata to reflect these changes. This remapping is designed to be self-limiting, eventually leading to the host updating its own address translations to exclude the bad blocks.
• Claim 16 (Non-transitory Computer Readable Medium Claim): This claim covers a non-transitory computer-readable medium (e.g., software or firmware) that contains instructions. When these instructions are executed by a host, they cause the host to interact with a memory controller and nonvolatile memory in a cooperative manner. This involves the host receiving information about memory subdivisions from the controller, using that information to directly address physical memory locations for operations, and processing notifications from the controller about remapped bad blocks. The host then updates its own address translations to account for these remapped blocks, ensuring future access avoids them.

USPTO and CAFC Docket Search:

• USPTO: US patent 11544183 was issued on January 3, 2023, and is currently active. Its application number is US16/997,471, filed on August 19, 2020. The current assignee is Radian Memory Systems LLC.
• CAFC 2026 Dockets: A review of CAFC dockets for 2026, specifically looking for patent 11544183, did not yield any direct results indicating scheduled cases or litigation involving this specific patent number in the provided search snippets. However, the Google Patents information for US11544183 does note that there is ongoing litigation related to this patent family, including a PTAB case IPR2025-01266 filed (Settlement) and a US case filed in the Texas Eastern District Court (case 2:24-cv-01073). These cases are not directly found in the CAFC 2026 May schedule.

Known litigation involving US patent 11544183 is as follows:

1. District Court Case (Texas Eastern District Court)

   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:24-cv-01073
   • Status: Litigation is ongoing
   • Plaintiff(s): Not explicitly stated in the provided snippet.
   • Defendant(s): Not explicitly stated in the provided snippet.
   • Filing Date: Not explicitly stated in the provided snippet.

2. PTAB Case

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01266
   • Status: Settlement
   • Plaintiff(s): Unified Patents
   • Defendant(s): Not explicitly stated in the provided snippet, but Radian Memory Systems LLC is the current assignee of the patent.
   • Filing Date: Not explicitly stated in the provided snippet.

Proceedings overview

There is one AIA trial proceeding on US patent 11544183, which has been terminated due to settlement. This offers a defendant limited immediate clarity regarding claim validity through PTAB, as no claims were formally invalidated or sustained by a Final Written Decision.

IPR2025-01266 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Radian Memory Systems LLC

• Type: Inter Partes Review
• Filed: 2025-07-09
• Status: Terminated-Settled – The proceeding concluded due to a settlement between the parties.
• Judge panel: Not publicly available in the provided snippets.
• Petition grounds: Not publicly available in the provided snippets. Given the nature of an IPR, it would typically involve challenges under 35 U.S.C. §§ 102 and/or 103 based on patents and printed publications.
• Institution decision: Not applicable as the case settled before a formal institution decision would have been issued or made public.
• Final Written Decision: Not issued, as the proceeding was terminated due to settlement.
• Settlement / termination: The proceeding was terminated as settled on 2026-01-09. The specific terms of the settlement are confidential.
• Appeal: No appeal to the Federal Circuit occurred, as no Final Written Decision was issued.
• Defensive value: This proceeding indicates that Samsung Electronics Co., Ltd. and Radian Memory Systems LLC reached a settlement. While it doesn't provide a judicial determination on the validity of any claims of US11544183, the termination via settlement suggests that the parties resolved their dispute outside of a full PTAB trial. For a new defendant, the claims remain untested by PTAB scrutiny, meaning the full range of prior art grounds under §§ 102 and 103 might still be available for a new IPR petition.

Strategic summary

The PTAB record for US patent 11544183 shows one Inter Partes Review, IPR2025-01266, which was initiated by Samsung Electronics Co., Ltd. et al. and subsequently terminated due to settlement on 2026-01-09. As a result, no claims of US11544183 have been formally canceled or sustained by a Final Written Decision from the PTAB. All claims of the patent remain untested in an AIA trial context.

The estoppel landscape for IPR2025-01266 is specific to the petitioner, Samsung Electronics Co., Ltd. et al., and their privies. Under 35 U.S.C. § 315(e)(2), they would be barred from raising any ground that they raised or reasonably could have raised during this IPR. However, for a new defendant facing assertion of this patent, this settlement does not create estoppel, and all prior-art grounds under 35 U.S.C. §§ 102 and 103 are still available for a potential IPR petition. The patent owner, Radian Memory Systems LLC, was involved in this proceeding, and the settlement suggests they preferred to resolve the matter rather than pursuing a full IPR trial. Unified Patents was mentioned as a petitioner in relation to this IPR case in the initial Google Patents data, but the "PTAB proceedings on file" section explicitly lists "Samsung Electronics Co., Ltd. et al." as the petitioner, which is the authoritative source for this task.

Recommended next steps

Given that IPR2025-01266 was terminated via settlement and no claims were invalidated, the patent claims of US11544183 remain patentable as far as the PTAB is concerned.

• If you are a defendant facing assertion of this patent, all claims (Claim 1, Claim 11, Claim 16, and their dependent claims) are currently considered valid by the USPTO. Any infringement theory built on these claims is still viable from a patent validity standpoint, as they have not been challenged to a final decision at the PTAB.
• Consider a new IPR petition if asserting entity is not Samsung or their privies, as the claims have not been substantively reviewed by the PTAB. The absence of a Final Written Decision means a new defendant is not estopped from raising prior art grounds.
• Perform a thorough prior art search, focusing on the cooperative memory management and bad block remapping aspects, to identify strong grounds for a new IPR petition if desired. This could potentially target independent claims 1, 11, and 16.

Inventors

• Andrey V. Kuzmin (Employer: Radian Memory Systems LLC, at the time of filing)
• Mike Jadon (Employer: Radian Memory Systems LLC, at the time of filing)
• Richard M. Mathews (Employer: Radian Memory Systems LLC, at the time of filing)

Original assignee

The original assignee on the issued patent is Radian Memory Systems LLC. The patent's subject matter relates to storage systems, specifically the architecture and management of flash memory and solid-state drives (SSDs). This suggests Radian Memory Systems LLC is an operating company that develops and potentially ships products embodying these claims, such as SSDs or memory controllers. The current legal status of the patent is "Active", and Radian Memory Systems LLC is also listed as the current assignee, indicating they are still operating.

Assignment timeline

• 2020-08-19 (executed) / recorded 2020-08-19 — Reel 053531/0861
  • Conveyance: Assignment
  • Assignor: JADON, MIKE; KUZMIN, ANDREY V.; MATHEWS, RICHARD M.
  • Assignee: Radian Memory Systems, LLC
  • Correspondent: Eric S. Hyman, Blanchard, Krasner & French, San Diego, CA. This correspondent recurs in this chain.
  • Context: Inventors assigned rights to the original assignee.
• 2020-08-19 (executed) / recorded 2020-08-19 — Reel 053531/0878
  • Conveyance: Change of Name
  • Assignor: Radian Memory Systems, LLC
  • Assignee: Radian Memory Systems, Inc.
  • Correspondent: Eric S. Hyman, Blanchard, Krasner & French, San Diego, CA. This correspondent recurs in this chain.
  • Context: Internal corporate reorganization/change of name.
• 2024-05-20 (executed) / recorded 2024-05-20 — Reel 063683/0369
  • Conveyance: Assignment
  • Assignor: Radian Memory Systems, Inc.
  • Assignee: RADIAN MEMORY SYSTEMS LLC
  • Correspondent: Eric S. Hyman, Blanchard, Krasner & French, San Diego, CA. This correspondent recurs in this chain.
  • Context: Internal corporate reorganization/assignment back to LLC structure.

Timeline diagram

timeline
    title Ownership of US 11544183
    2020 : Filed
         : Inventors assign to Radian Memory Systems LLC
         : Radian Memory Systems LLC changes to Inc
    2023 : Issued
    2024 : Radian Memory Systems Inc assigns to Radian Memory Systems LLC

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. All transfers are between variations of "Radian Memory Systems". The company is described as an operating company in the memory/storage sector.
2. Known asserter in the chain — Not present. None of the assignees (Radian Memory Systems LLC or Radian Memory Systems, Inc.) appear on common NPE lists.
3. Repeat correspondent across the chain — Present. Eric S. Hyman of Blanchard, Krasner & French, San Diego, CA, is listed as the correspondent for all three recorded assignments (Reel 053531/0861, Reel 053531/0878, and Reel 063683/0369).
4. Cascading transfers — Not present. While there are two assignments on the same day in 2020, they represent the initial inventor assignment and a corporate name change, not a rapid transfer through chained LLCs to new owners. The subsequent transfer is 4 years later.
5. Pre-litigation transfer — Unclear. The patent's Google Patents page indicates litigation (PTAB case IPR2025-01266 and US case 2:24-cv-01073 in Texas Eastern District Court). The earliest listed litigation filing date is not explicitly provided in the snippets, but the district court case number (2:24-cv-01073) suggests a filing in 2024. The last assignment occurred on 2024-05-20 (recorded 2024-05-20, Reel 063683/0369). Without the exact filing date of the district court case, it's unclear if this assignment falls within 6 months prior.
6. Bankruptcy fire-sale — Not present. There is no indication of bankruptcy proceedings for Radian Memory Systems LLC or Inc.
7. Privateering — Not present. There is no evidence of an operating company transferring the patent to an NPE to assert on their behalf.
8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at a known defensive aggregator.

Verdict

Operating-company assertion
The assignment records consistently show ownership by Radian Memory Systems LLC and its corporate variant, Radian Memory Systems, Inc., which is identified as an active entity in the memory/storage system sector. The consistent correspondent across all internal transfers further supports this being an operating company managing its intellectual property, rather than an NPE. The observed litigation is likely direct assertion by the operating company.

USPTO Assignment Center Search for US11544183

To identify the most relevant prior art for US patent 11544183, I need to perform a search within the USPTO database for the patent's cited references. Since direct access to the USPTO database for specific patent citations and their detailed descriptions isn't available through my current tools, I will outline the general process a patent analyst would follow.

A patent analyst would typically use the USPTO Patent Public Search tool or similar patent databases to access the full patent document for US11544183. Within the patent document, there's a section titled "References Cited" (or similar) that lists all prior art considered by the patent examiner and the applicant. This list includes both U.S. Patents and potentially foreign patents or non-patent literature.

For each reference listed in US11544183, the analyst would:

1. Obtain the full citation: This includes the patent number, inventor(s), issue/publication date, and assignee.
2. Determine publication/filing date: For a U.S. patent, this would be the issue date; for a U.S. patent application publication, it would be the publication date. The filing date is also important for determining 35 U.S.C. § 102 anticipation.
3. Read the abstract and relevant sections: A brief description of the reference's technology, focusing on aspects that relate to the claims of US11544183.
4. Analyze for potential anticipation under 35 U.S.C. § 102: This involves comparing the elements of each independent claim (Claim 1, Claim 11, and Claim 16) of US115444183 against the disclosure of the prior art reference. Anticipation under § 102 means that every element of a claim is found, either explicitly or inherently, in a single prior art reference.

Without direct access to the USPTO's complete "References Cited" list and the full text of each cited patent, I cannot provide a definitive list of the most relevant prior art and their anticipating claims.

However, based on the patent summary provided, the core innovations of US11544183 relate to:

• Cooperative memory management between a memory controller and a host.
• The memory controller storing subdivision-specific memory data and making it accessible to the host.
• The host using this data to directly issue commands with physical addresses.
• Limited, self-correcting remapping by the memory controller for bad blocks, with eventual host awareness and update of translation tables.

Therefore, prior art that would be highly relevant for potential anticipation would likely include patents disclosing:

• Memory systems with host-controlled physical addressing for nonvolatile memory.
• Memory controllers that provide detailed usage statistics or metadata to a host.
• Techniques for bad block management in nonvolatile memory, particularly those involving cooperation between a controller and a host, or remapping schemes.
• Flash translation layers (FTLs) that are significantly simplified or offloaded to the host.

To provide the specific prior art details and their potential anticipatory effect, I would need to perform the detailed analysis described above using the full patent document.

I cannot perform an obviousness analysis under 35 U.S.C. § 103 for US patent 11544183 at this time.

The "Prior Art" section of this analysis explicitly states: "Without direct access to the USPTO's complete 'References Cited' list and the full text of each cited patent, I cannot provide a definitive list of the most relevant prior art and their anticipating claims."

To perform an obviousness analysis, I would need access to the specific prior art references cited in US11544183 and their full disclosures. This would enable me to:

1. Identify the elements of the claims of US11544183.
2. Determine what each individual prior art reference teaches.
3. Identify combinations of two or more prior art references that, when combined, disclose all elements of the claims.
4. Articulate a motivation for a person having ordinary skill in the art (PHOSITA) to combine these specific references to arrive at the claimed invention, with a reasonable expectation of success.

Without the actual content of the cited prior art documents, I cannot identify specific combinations or provide a reasoned explanation for motivation to combine them.