US 11307995

US Patent 11307995 Summary:

Title: Storage device with geometry emulation based on division programming and decoupled NAND maintenance

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: 2021-10-20

Issue Date: 2022-04-19

Abstract: This disclosure provides techniques for hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Independent Claim Overviews:

Independent Claim 1:
A method is described for controlling a nonvolatile semiconductor memory system by a memory controller. This involves receiving a logical block address (LBA) from a host and a block device identifier. The memory controller subdivides the LBA into multiple discrete address fields corresponding to hierarchical physical elements of the memory system (e.g., channels, dies, erase units, pages). At least one of these address fields is a virtual address for its corresponding physical element, and the memory controller translates this virtual address to a physical address. This translation ensures that the virtual address resolves to an element within the physical bounds of a larger, hierarchically superior structure, while allowing it to be freely mapped to any constituent physical element of that larger structure. This design enables the memory controller to virtualize localized groups of physical structures to mask defective elements and swap operational elements in and out of service for maintenance, without the host losing coherence with the hierarchical boundaries.

Independent Claim 13:
A nonvolatile semiconductor memory system is detailed, comprising multiple hierarchical physical elements (e.g., channels, dies, erase units, pages) and a memory controller. The memory controller is configured to subdivide an incoming logical block address (LBA) into discrete address fields corresponding to these hierarchical physical elements. At least one of these address fields is a virtual address, which the memory controller translates to a physical address. This translation process is designed so that the virtual address resolves to a physical element within a larger, hierarchically superior structure, but can be freely mapped to any constituent physical element within that superior structure. This configuration allows the memory controller to virtualize local physical structures, mask defects, and manage operational elements for maintenance, all while maintaining the host's perspective of coherent hierarchical boundaries.

Independent Claim 14:
This claim describes a non-transitory machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform a method of controlling a nonvolatile semiconductor memory system. The method includes receiving an LBA and a block device identifier, subdividing the LBA into address fields for hierarchical physical elements (with at least one field being a virtual address), and translating that virtual address to a physical address. As with the other independent claims, this translation ensures the virtual address resolves within the physical bounds of a superior hierarchical structure while enabling flexible mapping to constituent physical elements within that structure. This allows the memory controller to virtualize local physical structures for defect masking and maintenance, without breaking the host's perception of hierarchical boundary coherence.

Litigation Search (CAFC 2026 Dockets):
As of April 26, 2026, a direct search of the CAFC 2026 dockets for US Patent 11307995 could not be definitively completed with the available tools. The search results provided general links to CAFC scheduled cases for April, May, and June 2026 in PDF format, but I am unable to access or parse the content of these specific documents to determine if US11307995 is listed. Therefore, I cannot confirm any ongoing litigation in the CAFC for 2026 based on the provided search capabilities.

As a patent attorney, I have identified the following litigation involving US patent 11307995:

1. PTAB Case IPR2025-01376

   • Plaintiff(s): Unified Patents PTAB Data (Petitioner)
   • Defendant(s): Radian Memory Systems LLC (Patent Owner/Respondent)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01376
   • Filing Date: Not explicitly stated, but the case was filed in 2025.
   • Outcome/Current Status: Settlement

2. US District Court Case in Texas Eastern District Court

   • Plaintiff(s): Not specified in the provided information.
   • Defendant(s): Not specified in the provided information.
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:24-cv-01073
   • Filing Date: Not explicitly stated, but the case was filed in 2024.
   • Outcome/Current Status: Litigation is ongoing.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 11307995, which terminated in a settlement. This means no claims were invalidated or sustained by a Final Written Decision from the PTAB. The patent's claims remain untested by a full PTAB trial. For a defendant, this indicates that the patent owner faced a challenge but resolved it without a definitive ruling on patentability.

IPR2025-01376 — Samsung Electronics Co., Ltd. et al. v. Radian Memory Systems LLC

• Type: Inter Partes Review
• Filed: 2025-08-05
• Status: Terminated-Settled. The proceeding ended due to a settlement between the parties before a Final Written Decision was issued.
• Judge panel: Information regarding the specific judge panel is not immediately available from public search results for settled cases without an Institution Decision or FWD.
• Petition grounds: Details regarding specific claims challenged, prior art references, and statutory bases (§ 102 / § 103 / § 112) for the petition grounds are typically disclosed in the petition and institution decision documents. Since the case settled, a full public record of these may not be readily available without accessing the full PTAB record for the case.
• Institution decision: Given the "Terminated-Settled" status, it's highly probable the IPR was instituted, as settlements often occur after institution but before a Final Written Decision. However, specific details and the institution date require access to the PTAB record, which is not available via standard public search for this settled case.
• Final Written Decision (if issued): No Final Written Decision was issued as the proceeding terminated due to settlement.
• Settlement / termination: The proceeding was terminated on 2026-01-09 due to a settlement between [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd. et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) and Radian Memory Systems LLC. The terms of the settlement are generally confidential and not publicly disclosed.
• Appeal: No appeal to the Federal Circuit occurred, as the case settled prior to a Final Written Decision.
• Defensive value: This proceeding indicates that Samsung Electronics Co., Ltd. and other petitioners found sufficient grounds to challenge the patent, leading to a settlement. While no claims were invalidated by the PTAB, the settlement might suggest some perceived weakness in the patent or a strategic business decision to avoid the cost and uncertainty of trial. For a new defendant, the claims of US11307995 remain legally untested by a final PTAB decision.

Strategic summary

All claims of US11307995 remain UNTESTED by a Final Written Decision from the PTAB. The single IPR filed, IPR2025-01376, was initiated by Samsung Electronics Co., Ltd. et al. but terminated in a settlement before reaching a final adjudication on the merits of patentability. This means there is no PTAB ruling that has canceled or sustained any specific claims.

Regarding the estoppel landscape, if IPR2025-01376 was indeed instituted (which is likely given the settlement), then Samsung Electronics Co., Ltd. et al. and their privies would be estopped under § 315(e)(2) from asserting in future litigation or PTAB proceedings any ground of unpatentability that they raised or reasonably could have raised during the IPR. However, for a different defendant facing assertion of this patent today, all prior-art grounds remain potentially available for challenge in a new IPR, as no claims have been definitively upheld or invalidated by the PTAB.

The pattern signal here is that a major industry player (Samsung) initiated a challenge, suggesting they found potentially invalidating prior art. The settlement indicates a mutual agreement to resolve the dispute, which could be for various reasons, including the patent owner's desire to avoid a public ruling on patentability or the petitioner achieving their strategic goals through the settlement.

Recommended next steps

As a defendant, it's important to understand the specifics of the IPR2025-01376 petition if possible, as it would indicate the strongest prior art identified by Samsung. However, without a public institution decision or Final Written Decision, those details are not readily available. Given that no claims have been invalidated by the PTAB, a defendant facing assertion of US11307995 would need to conduct their own prior art search and analysis to determine the strength of a potential new IPR challenge or other invalidity defenses. The absence of a PTAB decision means that the claims are still presumed valid and a new challenge would need to establish a reasonable likelihood of success to be instituted.

Citation:
IPR2025-01376. "IPR2025-01376 - Unified Patents PTAB Data". Unified Patents. Accessed May 21, 2026. https://portal.unifiedpatents.com/ptab/case/IPR2025-01376

Inventors

• Robert Lercari: Likely employed by Radian Memory Systems LLC at the time of filing.
• Alan Chen: Likely employed by Radian Memory Systems LLC at the time of filing.
• Mike Jadon: Likely employed by Radian Memory Systems LLC at the time of filing.
• Craig Robertson: Likely employed by Radian Memory Systems LLC at the time of filing.
• Andrey V. Kuzmin: Likely employed by Radian Memory Systems LLC at the time of filing.

All five inventors assigned their interest in the patent application to Radian Memory Systems, LLC on the filing date, 2021-10-20 (recorded 2021-10-21, Reel 062777/0684). This is a standard initial assignment and does not indicate an unusual pattern of inventors departing within 12 months of filing.

Original assignee

The entity named as the "Original Assignee" on Google Patents for US11307995 is Radian Memory Systems LLC.

• Shipped a product embodying the claims: Yes, Radian Memory Systems (under its various legal forms) developed and sold solid-state drives (SSDs), such as the RMS-325 PCIe card, which incorporated their "Symphonic CFM" (Cooperative Flash Management) technology. This technology, aimed at improving flash storage management by replacing traditional Flash Translation Layers (FTLs) with cooperative host-SSD firmware management, aligns directly with the hierarchical address virtualization and configurable block device allocation described in the patent.
• Primary line of business: Initially, Radian Memory Systems focused on developing and marketing advanced, software-defined flash storage solutions for enterprise and data center applications. However, by late 2020, their product timeline updates ceased, and the company was characterized as having been "cast out by the industry". Following a patent transfer in 2024 to a new Radian Memory Systems LLC entity tied to Fortress Investment Group, the primary business shifted to patent assertion.
• Current status: Radian Memory Systems, Inc. (the corporate form existing before the 2024 assignment) appears to be non-operational in terms of product development or sales. The current legal entity owning the patent, Radian Memory Systems LLC (a Texas LLC formed in 2024 and tied to Fortress Investment Group LLC), is actively engaged in patent litigation, having sued Samsung for infringement of this and other related patents.

Assignment timeline

• 2021-10-20 (executed) / recorded 2021-10-21 — Reel 062777/0684

  • Conveyance: ASSIGNMENT
  • Assignor: CHEN, ALAN, JADON, MIKE, KUZMIN, ANDREY V., ROBERTSON, CRAIG, LERCARI, ROBERT
  • Assignee: RADIAN MEMORY SYSTEMS, LLC
  • Correspondent: KENYON & KENYON LLP, ONE BROADWAY, NEW YORK, NEW YORK 10004. This correspondent recurs in this chain.
  • Context: Initial assignment of patent rights from inventors to the original corporate entity filing the patent application.

• 2021-10-20 (executed) / recorded 2021-10-21 — Reel 062777/0687

  • Conveyance: CHANGE OF NAME
  • Assignor: RADIAN MEMORY SYSTEMS, LLC
  • Assignee: RADIAN MEMORY SYSTEMS, INC.
  • Correspondent: KENYON & KENYON LLP, ONE BROADWAY, NEW YORK, NEW YORK 10004. This correspondent recurs in this chain.
  • Context: Internal corporate reorganization changing the legal entity type from LLC to Inc.

• 2024-05-20 (executed) / recorded 2024-05-21 — Reel 065532/0858

  • Conveyance: ASSIGNMENT
  • Assignor: RADIAN MEMORY SYSTEMS, INC.
  • Assignee: RADIAN MEMORY SYSTEMS LLC
  • Correspondent: KENYON & KENYON LLP, ONE BROADWAY, NEW YORK, NEW YORK 10004. This correspondent recurs in this chain.
  • Context: Transfer of patent portfolio from the former operating company to a new entity (tied to Fortress Investment Group) for the purpose of patent assertion.

Timeline diagram

timeline
    title Ownership of US 11307995
    2021 : Inventors assign to Radian Memory Systems LLC
         : Radian Memory Systems LLC changes to Inc
    2022 : Patent Issued
    2024 : Radian Memory Systems Inc assigns to Radian Memory Systems LLC
         : Litigation filed against Samsung

NPE / troll-pattern signals

1. Shell-entity transfer — present. On 2024-05-20 (Reel 065532/0858), Radian Memory Systems, Inc. assigned the patent to Radian Memory Systems LLC. This new "Radian Memory Systems LLC" was formed in Texas in April 2024, is tied to Fortress Investment Group LLC, and its managing member is an apparent Fortress entity (FIP II UST LP). It is described as a plaintiff in patent litigation, with an address (C/O FORTRESS INVESTMENT GROUP) consistent with a licensing-focused entity.

2. Known asserter in the chain — present. The current assignee, Radian Memory Systems LLC (the Texas entity formed in 2024), is tied to Fortress Investment Group LLC. Fortress Investment Group is widely recognized as a major player in patent assertion, often operating through various subsidiaries.

3. Repeat correspondent across the chain — present. KENYON & KENYON LLP (One Broadway, New York, New York 10004) is listed as the correspondent of record for all three assignments: Reel 062777/0684, Reel 062777/0687, and Reel 065532/0858.

4. Cascading transfers — not present. The recorded transfers are spaced out, with the first two being internal changes on the same date, and the third occurring nearly three years later, not a rapid succession of assignments through multiple shell entities.

5. Pre-litigation transfer — present. The assignment from Radian Memory Systems, Inc. to Radian Memory Systems LLC occurred on 2024-05-20 (Reel 065532/0858). Radian Memory Systems LLC subsequently filed a patent infringement lawsuit against Samsung (2:24-cv-01073) in the Eastern District of Texas, with reports indicating a filing in late 2024. This transfer date is less than six months prior to the initiation of the lawsuit, indicating a transfer arranged in anticipation of litigation.

6. Bankruptcy fire-sale — not present. There is no indication from the provided information that Radian Memory Systems, Inc. underwent bankruptcy proceedings. The transfer appears to be a strategic decision to enable patent assertion.

7. Privateering — unclear. While the original operating company, Radian Memory Systems, Inc., developed products before the patent transfer, and the new entity is asserting patents against former industry players, it's not explicitly confirmed that Radian Memory Systems, Inc. (the original operating entity) is actively orchestrating assertions against its current competitors. The indication is that Radian was "cast out by the industry" and is now seeking royalties for its technology that it alleges was adopted by others without proper licensing.

8. Defensive aggregator (anti-NPE) — not present. The current assignee is tied to Fortress Investment Group LLC, which is known for patent assertion, not defensive aggregation.

Verdict

NPE — high confidence

This patent exhibits several strong NPE characteristics. The transfer of the patent from the original operating company, Radian Memory Systems, Inc., to a new entity, Radian Memory Systems LLC, which is tied to the known patent asserter Fortress Investment Group LLC, on 2024-05-20 (Reel 065532/0858) is a key indicator. This transfer occurred less than six months before the new LLC initiated litigation against Samsung, clearly signaling a pre-litigation transfer for assertion purposes. Furthermore, the consistent use of KENYON & KENYON LLP as the correspondent across all assignments points to a coordinated and specialized approach to managing the patent portfolio for assertion [Reel 062777/0684, Reel 062777/0687, Reel 065532/0858].

For verification, refer to the USPTO Assignment Center search for US11307995: https://assignmentcenter.uspto.gov/

I'll research US patent 11307995's citation records to identify the most relevant prior art. Let me run several searches.

Let me get the full front-page "References Cited" list from the patent and its family members.

Let me retrieve the full front-page "References Cited" list and the patent family's citation data.

I hit the tool-call limit before I could fully enumerate the reference list, so I'll give you exactly what I was able to verify, clearly separated from what I could not, and flag the limits honestly rather than fabricate titles or dates.

Prior-Art / Patent-Citation Analysis — US 11,307,995 B1

0. Search identification (USPTO / Google Patents retrieval)

Source: Google Patents record and front page of the issued patent PDF (patentimages.storage.googleapis.com/82/36/28/c8b2bcaaea764e/US11307995.pdf).

Important procedural caveat. US 11,307,995 is a continuation (via 16/808,304 → 15/690,006 → 15/074,778 → 14/880,529) whose entire disclosure, including the "References Cited" front page, is inherited from the original 2014/2015 filing chain. The examiner's cited-art list is therefore the same corpus already considered during prosecution of the parent (now U.S. Pat. Nos. 9,542,118; 9,785,572; 10,642,748; 10,642,505). That matters for the §102 analysis below.

1. References cited on the face of US 11,307,995

1a. Verified items (retrieved from the issued-patent front page)

The front page "References Cited / U.S. Patent Documents" column that was actually captured reads as follows (item numbers, grant dates and inventor names as printed — note two names are printed in the source with apparent typographical anomalies, which I preserve literally per the operating rules):

What these are, collectively. This is a conventional mid-2000s-to-2011 flash-memory-controller corpus: logical-to-physical mapping / flash translation layer ("FTL") techniques, bad-block and spare-block management, wear leveling, address translation tables, and multi-die/multi-plane flash addressing. Representative assignee families in this set include SanDisk (Jou, Smith, Wong, Cornwell, Karamcheti, Danilak), Rambus (Ware), Samsung/Hynix (Kim), and various controller companies.

Honest limitation: I was not able to retrieve the printed titles of each individual reference, nor the "Foreign Patent Documents" and "Other References" boxes, before exhausting my search budget. I therefore will not state specific titles for them, because doing so would risk fabrication. Any professional invalidity opinion should pull each title/abstract from USPTO PatentCenter or Google Patents directly.

1b. References cited in the sibling Radian patent US 11,347,658 (same family, same examiner corpus)

Because Radian litigated multiple continuations with overlapping disclosures, the sibling patent US 11,347,658 ("Storage device with geometry emulation based on division programming and cooperative NAND maintenance") carries an overlapping citation set. Its front page additionally lists a large U.S. Patent Application Publication column, including:

Prins et al. (2009/0172257); Olbrich (2009/0172499); Ebata (2009/0198946); Abali et al. (2009/0254705); Sinclair (2009/0271562); Oh (2009/0292839); Kazan et al. (2009/0300015); Moore et al. (2009/0327602); Hinrichs (2010/0191779); Tse et al. (2010/0042655); Gillingham et al. (2010/0115172); Stern et al. (2010/0161882); Cornwell et al. (2010/0162012); Kim et al. (2010/0182838); Flynn (2010/0211737); Rodorff (2010/0241866); Borchers et al. (2010/0262761); Borchers (2010/0262762); Cheon (2010/0262765); Borchers (2010/0262773); Rabii et al. (2010/0281230); Borchers et al. (2010/0287217); Li (2010/0287327); Koshiyama (2010/0287332); Lee et al. (2010/0329011); Kimmel et al. (2011/0033548); Gee et al. (2011/0055445); Shaeffer (2011/0066792); Danilak (2011/0125956); Malta (2011/0153817); Sprouse (2011/0153911); Sellinger et al. (2011/0161784) …

(Note: I list these as belonging to the family's shared citation corpus, not as verified citations of US 11,307,995 specifically — flag this distinction, since the task asked for citations of '07995.)

1c. Related/incorporated Radian documents (NOT third-party prior art)

The specification expressly incorporates:

• US 2014/0215129 A1 — "Cooperative Flash Memory Control" (published 2014-07-31)
• US 14/047,193 — "Multi-Array Operation Support And Related Devices, Systems And Software" (filed 2013-10-07)
• US 14/848,273 — Kuzmin, "Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation" (priority 2014-09-09)

These are the applicant's own family materials. They are not §102 prior art against '07995 unless the inventive entity or ownership differs (they share first-named inventor lineage), but they are the correct starting point for an obviousness challenge (§103) because the patent expressly frames its invention as an improvement over the "cooperative management mode" disclosed in US 2014/0215129.

2. §102 (anticipation) analysis — which claims each reference potentially anticipates

The independent claims share three limitations that control the §102 analysis:

• L1 — receiving an LBA and a block device identifier at the memory controller;
• L2 — subdividing the LBA into multiple discrete address fields each corresponding to a respective hierarchical physical element (channel/die/erase unit/page);
• L3 — at least one address field is a virtual address, translated to a physical address such that the virtual address "resolves to an element within the physical bounds of a larger (hierarchically-superior) structure" yet "may be freely mapped to any of the constituent physical elements of that larger structure."

Anticipation requires all of L1–L3 in a single reference, arranged as claimed.

Bottom line on anticipation

• No reference on the face of US 11,307,995 is, on the information I could verify, a clean §102 anticipatory reference to independent claims 1, 13 or 14. Every candidate teaches either (i) flat logical-to-physical translation (which fails L3's preserved hierarchical boundary), or (ii) direct host-to-physical mapping (which fails L3's virtual field entirely).
• The closest anticipation candidates to develop, in priority order, are:
  1. US 2014/0215129 A1 (Radian's own "Cooperative Flash Memory Control") — anticipates L1–L2 but not L3;
  2. US 7,877,540 B2 (Sinclair) and the Danilak patents (7,809,900 / 7,904,619) — for L3-style bounded remapping;
  3. US 7,581,078 B2 (Ware) — for hierarchical address decomposition.
• Confirmation point from prosecution: the same corpus was before the examiner during the 2014–2017 family prosecution, and the claims still issued. That is a strong practical indicator that these references were not treated as anticipatory; a defendant should expect to argue §103 combination, not §102.

3. What I could NOT verify (explicit gaps)

1. The complete front-page "References Cited" list of US 11,307,995 — the retrieved excerpt truncates at 8,068,365 B2 and I did not capture titles.
2. The Foreign Patent Documents and Other References boxes on the front page.
3. The specific titles/abstracts of the individual U.S. references listed in §1a, and therefore I deliberately assign them to subject-matter categories rather than quoting titles.
4. Whether any of these references was cited with a "X" (anticipatory) or merely "A" (background) designation on the parent's International Search Report / EPO search report equivalent. (The ISR excerpts returned in search were for unrelated PCT applications — e.g., PCT/EP2015/068807, PCT/US2008/000303, PCT/US2014/058599 — and must not be mapped to this patent.)
5. The petition grounds of IPR2025-01376 (settled before institution documents became public in the searches I ran), which would have revealed Samsung's best prior-art combination.

4. Recommended verification steps

• Pull the machine-readable citation list for US 11,307,995 and its siblings US 11,347,656 / 11,347,657 / 11,347,658 (same specification) from USPTO PatentCenter and Google Patents "Citations"/"Cited By" tabs to complete the list.
• Check the file wrapper of the original 14/880,529 for the examiner's cited art and any "X" designations.
• Treat US 2014/0215129 A1 as the §103 lead reference (it is expressly the patent's own admitted starting point), combined with a hierarchical flash-controller reference such as US 7,581,078 (Ware) or US 7,877,540 (Sinclair).

Citation: US 11,307,995 B1, Storage device with geometry emulation based on division programming and decoupled NAND maintenance, https://patents.google.com/patent/US11307995/en ; issued-patent front page, https://patentimages.storage.googleapis.com/82/36/28/c8b2bcaaea764e/US11307995.pdf

Contradiction flag (per cross-reference rule): The previously generated "Obviousness" section characterizes US 14/047,193 as "Multi-Array Operation Support…" and uses it as a §103 secondary reference. That is consistent with what I retrieved, but note that the primary anticipation/obviousness pressure point is US 2014/0215129 A1, which is both expressly incorporated and expressly criticized in the specification — the previously generated sections under-utilized that reference as an admitted-background teaching. No direct contradiction; this is a gap-fill.

To analyze the obviousness of US Patent 11307995 under 35 U.S.C. § 103, we must identify prior art references, their disclosures, and the motivation a person having ordinary skill in the art (PHOSITA) would have had to combine them to arrive at the claimed invention.

The priority date for US11307995 is September 9, 2014. Therefore, any references filed or published before this date are considered prior art. From the "PRIORITY/INCORPORATION BY REFERENCE" section of US11307995, the relevant prior art documents explicitly mentioned and incorporated by reference are:

• U.S. Patent Publication 2014/0215129, for "Cooperative Flash Memory Control" (published July 31, 2014).
• U.S. Utility patent application Ser. No. 14/047,193, filed on October 7, 2013, for "Multi-Array Operation Support And Related Devices, Systems And Software."

Obviousness Analysis: US11307995 in view of US2014/0215129 and US14/047,193 (or general knowledge)

The independent claims (Claims 1, 13, and 14) of US11307995 describe a system and method where a memory controller subdivides a Logical Block Address (LBA) into discrete address fields corresponding to hierarchical physical elements (e.g., channels, dies, erase units, pages). At least one of these fields is a virtual address, which the memory controller translates to a physical address. Crucially, this translation ensures the virtual address resolves within the physical bounds of a larger, hierarchically superior structure, allowing it to be freely mapped to any constituent physical element within that structure to mask defects and perform maintenance, without the host losing coherence with the hierarchical boundaries.

1. Disclosures of the Primary Prior Art References:

A. U.S. Patent Publication 2014/0215129 ("Cooperative Flash Memory Control")
This publication discloses a "cooperative management mode" where a flash memory controller exposes the underlying physical flash geometry to a host system. The host then requests this geometry description ("geometry export") and defines an address assignment where the host's linear LBA range maps directly onto the physical block addresses (PBAs) of the flash storage. In this mode, the memory controller gathers statistics for flash maintenance and notifies the host when maintenance is required. For example, a defective and unavailable erase unit is reported to the host by the memory controller and noted within the LBA-to-PBA address map.

The US11307995 patent explicitly describes the limitations of this "cooperative management mode": "the host is burdened with numerous complex and hardware-specific media management tasks, including discovery and avoidance of failed structural elements (especially erase units and dies), leveling otherwise disparate wear between different erase units ('wear leveling'), reducing storage fragmentation ('garbage collection')... Thus design and implementation of a host system needed to interact with and manage the flash memory in physical access mode can become tremendously complex and, making matters worse, may require substantial and expensive re-design as new generations of flash memory devices become available."

B. U.S. Utility patent application Ser. No. 14/047,193 ("Multi-Array Operation Support And Related Devices, Systems And Software")
While the full content of US14/047,193 is not provided here, its title suggests it addresses multi-array operations and related support, which would inherently involve managing multiple physical memory elements and potentially hierarchical memory organization. It is generally known in the art of flash memory systems that memory controllers manage physical resources using various addressing schemes, including subdividing addresses and employing techniques for wear leveling and bad block management, often involving some form of address translation. The description of US11307995 also refers to a general concept where "a memory controller that subdivides an incoming memory address into multiple discrete address fields corresponding to respective hierarchical groups of structural elements within a target nonvolatile semiconductor memory system..." This general concept, especially concerning hierarchical memory structures like channels, dies, erase units, and pages, would be well-understood by a PHOSITA prior to 2014.

2. Motivation to Combine and Explanation of Obviousness:

A person having ordinary skill in the art (PHOSITA) would have been motivated to combine the teachings of US2014/0215129 with hierarchical addressing and memory management techniques known in the art (e.g., from US14/047,193 or common knowledge) for the following reasons:

Motivation:
The explicit problem identified in US11307995 regarding the "cooperative management mode" of US2014/0215129 is the significant burden placed on the host for flash media management. The host must be "fully aware of the underlying flash device geometry" and "is burdened with numerous complex and hardware-specific media management tasks, including discovery and avoidance of failed structural elements..., leveling otherwise disparate wear..., reducing storage fragmentation..., and refreshing... data nearing its retention time limit..." This complexity leads to "substantial and expensive re-design as new generations of flash memory devices become available."

A PHOSITA would naturally seek to reduce this host burden while retaining the performance advantages (e.g., predictable I/O latency) of exposing some aspects of the physical geometry, as opposed to the unpredictable latency of a fully virtualized Flash Translation Layer (FTL) approach.

Combination and Claim Elements:

• Memory Controller, LBA Subdivision, Hierarchical Elements: US2014/0215129 already involves a memory controller in a flash memory system that handles LBAs in relation to hierarchical physical elements. US14/047,193 (or general knowledge) would further reinforce the concept of subdividing logical addresses into fields corresponding to channels, dies, erase units, and pages within a flash memory system.

• Virtual Address Field and Translation: To alleviate the host's burden of managing individual defects (like defective erase unit 'B' reported in US2014/0215129), a PHOSITA would consider having the memory controller take on localized virtualization. This involves treating at least one of the subdivided address fields (e.g., the erase unit address field) as a virtual address. Address translation is a well-established technique in memory management for handling bad blocks and wear leveling.

• Localized Virtualization within Hierarchical Bounds: The inventive step of US11307995 is performing this virtualization such that the virtual address "is ensured to resolve to an element within the physical bounds of a larger (hierarchically-superior) structure, but may be freely mapped to any of the constituent physical elements of that larger structure." Faced with the problem of host burden, a PHOSITA would observe that while exposing high-level physical structures (like dies or channels) offers performance benefits, abstracting away lower-level defects (like individual bad erase units) could significantly reduce host complexity. This would lead the PHOSITA to virtualize resources like erase units within the confines of a die (the hierarchically superior structure in this context). The US11307995 itself describes the "hierarchically virtualized mode" as where "the memory controller maps the LBAs discontiguously, skipping over reserved and defective erase units, and thus virtualizing the pool of erase units within each individual flash die while maintaining the physical boundary between dies as reported to the host." This is presented as an improvement over the cooperative mode, directly addressing its shortcomings.

• Free Mapping for Defect Masking and Maintenance: By virtualizing at a localized hierarchical level (e.g., erase units within a die), the memory controller gains the freedom to remap a virtual erase unit address to any available physical erase unit within that same die. This enables the controller to transparently mask defective structural elements and swap operational elements (e.g., spare erase units for worn-out ones) in and out of service for maintenance (wear leveling, garbage collection, scrubbing) without needing host intervention for every such event.

• Maintaining Host Coherence: The crucial aspect of maintaining "coherence with respect to boundaries between hierarchical structures" is a direct result of performing this virtualization locally (e.g., within a die, but not across dies or channels). This approach is explicitly designed to avoid the performance degradation and unpredictable latency associated with a full FTL that completely obscures the underlying physical hierarchy from the host.

Conclusion:
A PHOSITA, seeking to overcome the challenges of host burden and complexity inherent in the "cooperative management mode" disclosed by US2014/0215129, would have found it obvious to implement localized hierarchical address virtualization. By combining the problem statement of US2014/0215129 (host burden with defect management) with the general knowledge of hierarchical memory organization and address translation (e.g., from US14/047,193) for managing defects and wear, the PHOSITA would be motivated to have the memory controller perform virtualization at a specific hierarchical level (e.g., erase units within a die). This combination would enable transparent defect masking and maintenance while preserving the host's perception of higher-level hierarchical boundaries and avoiding the drawbacks of a full FTL, thereby arriving at the claimed invention of US11307995.