US 11307995

US Patent 11307995 Summary:

Title: Storage device with geometry emulation based on division programming and decoupled NAND maintenance

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: 2021-10-20

Issue Date: 2022-04-19

Abstract: This disclosure provides techniques for hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

---

Independent Claim Overviews:

Independent Claim 1:
A method is described for controlling a nonvolatile semiconductor memory system by a memory controller. This involves receiving a logical block address (LBA) from a host and a block device identifier. The memory controller subdivides the LBA into multiple discrete address fields corresponding to hierarchical physical elements of the memory system (e.g., channels, dies, erase units, pages). At least one of these address fields is a virtual address for its corresponding physical element, and the memory controller translates this virtual address to a physical address. This translation ensures that the virtual address resolves to an element within the physical bounds of a larger, hierarchically superior structure, while allowing it to be freely mapped to any constituent physical element of that larger structure. This design enables the memory controller to virtualize localized groups of physical structures to mask defective elements and swap operational elements in and out of service for maintenance, without the host losing coherence with the hierarchical boundaries.

Independent Claim 13:
A nonvolatile semiconductor memory system is detailed, comprising multiple hierarchical physical elements (e.g., channels, dies, erase units, pages) and a memory controller. The memory controller is configured to subdivide an incoming logical block address (LBA) into discrete address fields corresponding to these hierarchical physical elements. At least one of these address fields is a virtual address, which the memory controller translates to a physical address. This translation process is designed so that the virtual address resolves to a physical element within a larger, hierarchically superior structure, but can be freely mapped to any constituent physical element within that superior structure. This configuration allows the memory controller to virtualize local physical structures, mask defects, and manage operational elements for maintenance, all while maintaining the host's perspective of coherent hierarchical boundaries.

Independent Claim 14:
This claim describes a non-transitory machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform a method of controlling a nonvolatile semiconductor memory system. The method includes receiving an LBA and a block device identifier, subdividing the LBA into address fields for hierarchical physical elements (with at least one field being a virtual address), and translating that virtual address to a physical address. As with the other independent claims, this translation ensures the virtual address resolves within the physical bounds of a superior hierarchical structure while enabling flexible mapping to constituent physical elements within that structure. This allows the memory controller to virtualize local physical structures for defect masking and maintenance, without breaking the host's perception of hierarchical boundary coherence.

---

Litigation Search (CAFC 2026 Dockets):
As of April 26, 2026, a direct search of the CAFC 2026 dockets for US Patent 11307995 could not be definitively completed with the available tools. The search results provided general links to CAFC scheduled cases for April, May, and June 2026 in PDF format, but I am unable to access or parse the content of these specific documents to determine if US11307995 is listed. Therefore, I cannot confirm any ongoing litigation in the CAFC for 2026 based on the provided search capabilities.