US 9858215

I'll search for authoritative information on this specific patent number, then summarize.

Let me pull the specific claim set and confirm the independent claims.

US Patent 9,858,215 — Summary

Identification (literal, as issued)

Sources: Google Patents, https://patents.google.com/patent/US9858215/en ; USPTO copy of the printed patent via Docket Alarm, https://www.docketalarm.com/cases/[PTAB](/ptab)/IPR2023-00203/Micron_Technology_Inc._v._Netlist_Inc/docs/03-09-2023-Patent_Owner/Exhibit-2109-EX2109_US9858215.pdf

Note on identifiers: some litigation filings render the application number variously as "14715,486" or "147715,486." Under the literal-interpretation rule, these are still the same application — 14/715,486. I did not find any different patent numbered 9858215; all hits correspond to US 9,858,215 B1.

Abstract (verbatim)

"A memory module is operable to communicate data with a memory controller via a memory bus in response to memory commands received from the memory controller. The memory module comprises a plurality of memory integrated circuits arranged in ranks and including at least one first memory integrated circuit in a first rank and at least one second memory integrated circuit in a second rank, and further comprises a buffer coupled between the at least one first memory integrated circuit and the memory bus and between the at least one second memory integrated circuit and the memory bus. The memory module further comprises logic providing first control signals to the buffer to enable communication of a first data burst between the memory controller and the at least one first memory integrated circuit through the buffer in response to a first memory command, and providing second control signals to the buffer to enable communication of a second data burst between the at least one second memory integrated circuit and the memory bus through the buffer in response to a second memory command."

Independent claims in plain language

The record I could verify identifies claim 1 (apparatus) and claim 21 (method) as independent. (I could not independently enumerate the full claim set beyond this, so I flag residual uncertainty on whether any third independent claim exists.)

Claim 1 — Memory module (apparatus)

• The module plugs into a computer system and exchanges data bursts with the system's memory controller over a memory bus, acting on successive memory commands (a "first" command followed by a "second" command).
• It is built on a printed circuit board with edge connections to the module slot.
• A register on the board receives and buffers the command-and-address signals for both the first and the second commands.
• Memory ICs on the board are organized into ranks, including a first rank and a second rank. The first rank is selected to receive/output the first burst and not selected (does not communicate) for the second; the second rank is selected for the second burst and not selected for the first. In other words, the two ranks are mutually exclusive on any given command, and the controller only "sees" one rank at a time.
• A buffer sits between each rank's ICs and the memory bus (i.e., between first-rank ICs and bus, and between second-rank ICs and bus).
• Logic coupled to the buffer responds to the first command by sending first control signals to the buffer, enabling the first burst to pass between the controller and the first rank through the buffer; and it responds to the second command by sending second (different) control signals enabling the second burst between the controller and the second rank through the buffer.
• Net effect: the on-module control logic steers/isolates the data path so that only the addressed rank's data is coupled to the bus for each burst, while the unaddressed rank is isolated — the "data buffering / rank isolation" concept.

Claim 1 language confirmed in PTAB papers, e.g., Samsung IPR2023‑00455 Petition at 37: "a register…configured to…buffer" (Ex. 1001, 37:27–31) and the "logic…providing first control signals…second control signals being different from the first control signals" limitations. See https://storage.courtlistener.com/recap/gov.uscourts.txed.[216364](/patent/216364)/gov.uscourts.txed.216364.88.3.pdf

Claim 21 — Method of operating a memory module

• A method for operating a module coupled to a memory controller through a memory bus that has a control/address (C/A) bus and a data bus; the module contains at least a first and a second memory IC.
• Receive a first set of input C/A signals (first command) and generate a first set of output C/A signals that select the first rank to receive/output the first data burst.
• Receive a second set of input C/A signals (second command) and generate a second set of output C/A signals that select the second rank to receive/output the second data burst.
• While the first burst is occurring, couple the first IC(s) to the data bus and isolate the second IC(s); then, for the second burst, couple the second IC(s) and isolate the first IC(s).
• The claim also calls for providing first/second control signals to a buffer (the same control-signal mechanism recited in claim 1).

Language confirmed in the Wolfe declaration for IPR2023‑00455 (limitations [21.e]–[21.g]); see https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1554310](/patent/1554310)/download-documents

Related-posture note (as requested re: dockets)

• PTAB: Samsung filed IPR 2023‑00455 (Jan. 10, 2023) and Micron filed IPR 2023‑01142 (May 8, 2023) against the '215 patent. On July 30, 2024 the PTAB issued final written decisions in both, finding all challenged claims unpatentable. Netlist appealed on Dec. 10, 2024; the appeal is CAFC No. 2025‑1286 (Netlist, Inc. v. Micron Technology, Inc., with Samsung participating), and the Federal Circuit scheduled oral argument for Sept. 9, 2026. (Note: this is a 2025 docket number, not a "2026" docket number.)
• District court: The '215 patent has been asserted by Netlist, e.g., in E.D. Tex. cases 2:22‑cv‑00293 and 2:22‑cv‑00294 (Netlist v. Samsung, filed Aug. 2022), and appears in an Idaho District Court case 1:25‑cv‑00323. In the Nov. 2024 E.D. Tex. trial the jury verdict covered the '912, '417, and '608 patents (the '215 was pleaded among asserted patents but was not one of the three tried to verdict).

Sources: Google Patents family/litigation links; Unified Patents portals https://portal.unifiedpatents.com/patents/patent/9858215 and https://portal.unifiedpatents.com/ptab/case/IPR2023-00455 ; Netlist SEC filing summarizing the IPRs/appeal, http://archive.fast-edgar.com/20260811/AOBZH22C8Z22T2ZA22ZG2CZZLMARZ2S2ZB8Q/R12.htm ; CourtListener CAFC docket https://www.courtlistener.com/docket/69849096/28/netlist-inc-v-micron-technology-inc/

Certainty statement

High confidence on the bibliographic data, abstract, and the substance of independent claims 1 and 21 (corroborated across the printed patent and PTAB/district-court records). Uncertain on two points: (1) whether the '215 contains any independent claim in addition to claims 1 and 21 (I did not obtain a complete verbatim claim listing); and (2) exact present-day legal status — Google Patents labels it "Expired – Fee Related" with an adjusted expiration of 2025‑09‑15, but that field is an automated assumption, and the live CAFC appeal (2025‑1286) concerns the PTAB's invalidation of the claims, so the operative status should be treated as unsettled.

I'll research litigation involving US patent 9858215 using the sources you specified.

Let me gather more detail on the specific cases identified.

Let me investigate the remaining cases: the 2:22-cv-00294 case, the Idaho case, and the CAFC appeal.

Litigation Involving U.S. Patent No. 9,858,215 ("'215 Patent") — "Memory module with data buffering"

Scope note: I searched the Unified Patents litigation portal (portal.unifiedpatents.com), CourtListener/RECAP, Docket Alarm, and Netlist's SEC filings. Because I hit a tool-use limit, I could not run independent PACER docket pulls for every case, so the entries below are cross-referenced from the sources that were returned. Where a detail is unconfirmed I say so.

The '215 patent is owned by Netlist, Inc. (Irvine, CA). It issued Jan. 2, 2018 from application 14/715,486 (a continuation in the long Netlist memory-module family claiming priority to Mar. 5, 2004). Note the Google Patents record lists it as "Expired - Fee Related, expires 2025-09-15."

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A. District Court litigation directly asserting the '215 patent

1. Netlist, Inc. v. Samsung Electronics Co., Ltd., et al. — E.D. Tex., Case No. 2:22-cv-00293-JRG (lead case)

• Plaintiff: Netlist, Inc.
• Defendants: [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.; Samsung Electronics America, Inc.; Samsung Semiconductor, Inc.
• Jurisdiction: U.S. District Court for the Eastern District of Texas (Judge Rodney Gilstrap)
• Case No.: 2:22-cv-00293-JRG
• Filing date: August 1, 2022
• Basis: Originally filed asserting the '912 patent; Netlist amended to add U.S. Patent Nos. 11,093,417 ('417), 9,858,215 ('215), and 10,268,608 ('608).
• Outcome/status: Netlist dropped the '215 patent from the case several months before trial (Dkt. No. 325). The Nov. 22, 2024 jury verdict and the Dec. 2, 2024 Final Judgment covered only the '912, '417, and '608 patents (Samsung found to have willfully infringed; $118 million lump-sum award). The Final Judgment expressly dismissed without prejudice Netlist's claim that Samsung infringes the '215 patent. So the '215 patent was adjudicated only up to claim construction/pretrial in this action.
• Citation: Final Judgment, Dkt. 855 (E.D. Tex. Dec. 2, 2024) (via CourtListener docket 64861664).

2. Netlist, Inc. v. Micron Technology Texas, LLC, et al. — E.D. Tex., Case No. 2:22-cv-00294

• Plaintiff: Netlist, Inc.
• Defendants: Micron Technology Texas, LLC; Micron Technology, Inc.; Micron Semiconductor Products, Inc.
• Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case No.: 2:22-cv-00294
• Filing date: August 1, 2022 (first amended complaint Aug. 15, 2022 adding the '215 and '417 patents)
• Consolidation: On Oct. 21, 2022, Judge Gilstrap consolidated this action with the Samsung case (2:22-cv-00293) and designated the Samsung action the "LEAD CASE" for pretrial matters. Claim construction was conducted jointly (hearing Sept. 26, 2023; Claim Construction Order Nov. 21, 2023).
• Outcome/status: Reported as closed on 10/09/2024 (case docket aggregator). As with the Samsung case, the '215 patent did not go to verdict in the consolidated trial.

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B. Post-grant (PTAB) proceedings on the '215 patent

3. Samsung Electronics Co., Ltd. v. Netlist, Inc. — IPR2023-00455

• Petitioner: Samsung Electronics Co., Ltd.
• Patent Owner: Netlist, Inc.
• Filed: January 10, 2023
• Patent: 9,858,215 B1
• Outcome: Final Written Decision, July 30, 2024 — the Board determined all challenged claims 1–29 unpatentable under 35 U.S.C. § 318(a). Directory Review was denied Oct. 8, 2024 (Paper 47). Netlist filed a Notice of Appeal to the Federal Circuit on December 10, 2024.

4. Micron Technology, Inc., et al. v. Netlist, Inc. — IPR2023-01142

• Petitioners: Micron Technology, Inc.; Micron Semiconductor Products, Inc.; Micron Technology Texas LLC
• Patent Owner: Netlist, Inc.
• Filed: July 28, 2023
• Institution Decision: January 3, 2024
• Patent: 9,858,215 B1 (application 14/715,486)
• Outcome: Micron's petition and motion for joinder were granted and Micron was joined as a petitioner to IPR2023-00455; the Final Written Decision issued July 30, 2024 finding claims 1–29 unpatentable. Status recorded as "Final Written Decision – Appealed."

Note: IPR2023-00455 and IPR2023-01142 were consolidated/joined, resulting in a single July 30, 2024 Final Written Decision invalidating all claims of the '215 patent.

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C. Appellate proceedings involving the '215 patent

5. Netlist, Inc. v. Micron Technology, Inc. (formerly styled Netlist, Inc. v. Samsung Electronics Co.) — U.S. Court of Appeals for the Federal Circuit, Appeal No. 2025-1286

• Appellant: Netlist, Inc. (with Micron/Samsung as appellees/respondents)
• Jurisdiction: U.S. Court of Appeals for the Federal Circuit
• Case No.: 2025-1286 (Google Patents also lists CAFC case "25-1286")
• Basis: Netlist's appeal from the PTAB's July 30, 2024 Final Written Decision holding claims 1–29 of the '215 patent unpatentable.
• Status (per Netlist SEC filing): Netlist noticed the appeal Dec. 10, 2024; on July 21, 2026 the CAFC notified the parties that oral argument was scheduled for September 9, 2026. A Federal Circuit Blog argument recap (Sept. 18, 2026) describes the oral argument (Judges Dyk, Linn, Chen), which centered on the construction of "rank" (whether a rank may contain a single memory device) and Netlist's priority claim. (The recap does not name the patent number; based on the identity of the appeal and issues, it appears to correspond to this '215 appeal, but I have not independently confirmed the patent-to-appeal mapping beyond the Netlist SEC filing.)

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D. Other cases listed on the patent record (details unconfirmed)

The Google Patents litigation panel for US 9,858,215 also lists:

• Idaho District Court, Case No. 1:25-cv-00323 — listed as a "US case filed in Idaho District Court." I could not retrieve the parties, filing date, or patent(s) asserted before hitting the search limit. Treat as unconfirmed.
• E.D. Tex., Case No. 2:23-cv-00628 — listed as a "US case filed in Texas Eastern District Court." Parties/patent(s) unconfirmed.

Caution on a near-miss number: A Samsung Electronics v. Netlist declaratory-judgment action in D. Del. (Case No. 1:25-cv-01371, filed Nov. 11, 2025) asserts, among others, U.S. Patent No. 9,858,218 — which is not the '215 patent. Per your instruction not to auto-correct identifiers, I flag it only to note it is a different patent number and is not counted here.

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Summary table

Bottom line: The '215 patent was asserted against both Samsung and Micron in the 2022 E.D. Tex. cases but was narrowed out of the cases before trial (Samsung) / consolidated and closed (Micron). Its validity was ultimately decided by the PTAB, which invalidated all claims 1–29 on July 30, 2024 in the joined IPR2023-00455 / IPR2023-01142 proceedings; Netlist's appeal of that decision is pending at the Federal Circuit (No. 2025-1286).

I'll start by reconciling the structured block (which says no AIA trials indexed) against what the patent page itself already discloses — it lists two PTAB IPRs with Final Written Decisions. Let me research both.

Key facts emerging: two IPRs (IPR2023-00455 by Samsung; IPR2023-01142 by Micron), both with FWDs, and 01142 is on appeal (CAFC 25-1286). Now I need claim-level outcomes.

Now let me nail down the appeal posture (CAFC 25-1286) and check for any other '215 proceedings (including denied institutions).

Proceedings overview

Reconciliation note first: the structured "PTAB proceedings on file" block you supplied (USPTO ODP) reports zero AIA trial proceedings for US 9,858,215. That is wrong — or at least stale. The patent's own Google Patents record lists two PTAB cases, both marked "Final Written Decision," and both are confirmed in public PTAB/docket sources. I am treating the ODP block as non-canonical here and reporting what the record actually shows: 2 proceedings, both instituted, both reaching a Final Written Decision that invalidated all 29 claims, both terminated 2024-07-30, and both now on appeal (Fed. Cir. 2025-1286, argued 2026-09-09). Zero claims sustained, zero settlements, zero institution denials. Put bluntly for a defendant: every claim of this patent (1–29) has been held unpatentable by the Board — and the patent expired 2025-09-15. A demand letter built on any claim of 9858215 is now citing claims that a panel has already canceled and a patent term that has already run.

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IPR2023-00455 — Samsung Electronics Co., Ltd. (joined by Micron) v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2023-01-10
• Status: Final Written Decision — Determined All Challenged Claims Unpatentable (appealed). (Source of proceeding record: Google Patents litigation block for US9858215; PTAB docket via Docket Alarm; Netlist SEC disclosure.)
• Judge panel: Georgianna W. Braden (writing), Jon M. Jurgovan, Kevin C. Trock
• Petition grounds — all against claims 1–29, all under pre-AIA 35 U.S.C. § 103(a):
  • Ground 1: Perego (US 7,363,422 B2) + JEDEC JESD79-2 (DDR2 SDRAM spec, Sept. 2003)
  • Ground 2: Perego + JESD79-2 + Ellsberry (US 2006/0277355 A1)
  • Ground 3: Perego + JESD79-2 + Halbert
  • Ground 4: Perego + JESD79-2 + Matsui
• Institution decision: Instituted on 2023-08-02 on all asserted grounds, all claims (Paper 11). Netlist had argued § 325(d) and § 314(a) discretionary denial in its Preliminary Response; the Board instituted anyway. Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC were later joined as petitioners via IPR2023-01142.
• Final Written Decision: Entered 2024-07-30. Verdict: "we determine Petitioner has proven by a preponderance of the evidence that claims 1–29 of the '215 patent are unpatentable," under § 103(a). The FWD is captioned "Determining All Challenged Claims Unpatentable" and also "Dismissing Petitioner's Motion to Exclude." Claim-level granularity: all 29 claims fell — independent claim 1 and independent claim 21 (the two independent claims per the parties' claim-construction exchange), plus all dependent claims 2–20 and 22–29. No claim was held patentable. On construction, the Board adopted Petitioner's proposed meaning of "rank" — that a rank may be a single memory device — noting the parallel district court construction ("a 'rank' can include a single memory device"). The Board found the Perego-based combination rendered the claims obvious notwithstanding Netlist's arguments that Perego's Rambus architecture is incongruent with JEDEC ranks.
• Settlement / termination: None. Terminated by FWD, not settlement.
• Appeal: Yes. Netlist's Notice of Appeal (Paper 49, dated 2024-12-10) appeals the 2024-07-30 FWD and the 2024-10-08 order denying Director Review. CAFC No. 2025-1286 (Netlist, Inc. v. Micron Technology, Inc., originally styled v. Samsung Electronics Co.). Issues per the notice: the Board's unpatentability determination for claims 1–29, its claim construction of "rank" and application thereof, procedural/preservation rulings, adequacy of consideration of expert testimony, motivation-to-combine and reasonable-expectation findings, and APA compliance. Netlist's reply brief presses that the Board's obviousness theory required modifying Rambus-based Perego into a JEDEC-compliant module that the Board itself found "would make Perego's system non-functional for Rambus." Director Review was requested and denied on 2024-10-08 (Paper 47) — Director Vidal recused; the denial was issued by another PTAB decision-maker. On 2025-01-15 the '215 appeal was consolidated with the parallel '417 appeal (No. 2025-1296); on 2026-05-14 the court designated 2024-2304, 2025-1286, -1296, and 2025-1936 companion cases for the same merits panel. Oral argument: 2026-09-09 before Judges Dyk, Linn, and Chen. Decision pending as of 2026-09-28.
• Defensive value: This is the dispositive proceeding. All claims of '215 are canceled by a final Board decision, subject only to the pending Federal Circuit appeal — so an assertion today rests on a judgment of invalidity that a defendant can put in front of the court on day one. Note the asymmetry: the FWD took effect and the patent still expired 2025-09-15, so even a Netlist appellate win revives a patent with no remaining term to infringe and only a six-year pre-expiration damages lookback.

IPR2023-01142 — Micron Technology, Inc., et al. v. Netlist, Inc.

• Type: Inter Partes Review (joinder-track petition on the same patent)
• Filed: 2023-07-28 per the PTAB docket (see caveat below)
• Status: Final Written Decision — appealed (terminated 2024-07-30)
• Judge panel: FWD panel was Braden, Jurgovan, Trock (a four-name roster including Daniel Galligan appears in one public docket summary — flagging that I could not independently confirm Galligan sat on the FWD).
• Petition grounds: Directed to the same claims 1–29 of '215 as the Samsung petition; Micron sought joinder to IPR2023-00455 rather than a separately briefed trial. Micron, Micron Semiconductor Products, and Micron Technology Texas were joined as petitioners in IPR2023-00455.
• Institution decision: 2024-01-03 — the Board granted the petition/motion for joinder, adding Micron as a petitioner to IPR2023-00455.
• Final Written Decision: The substantive FWD is the 2024-07-30 decision issued in IPR2023-00455 (Paper 45), which expressly recites that Micron "filed a motion for joinder and petition in IPR2023-01142 and have been joined as petitioners to this proceeding." Claim-level outcome is therefore identical: claims 1–29 unpatentable under § 103(a). The '215 Google Patents record lists IPR2023-01142 as terminated with a "Final Written Decision" on the same 2024-07-30 date.
• Settlement / termination: None. Terminated with the FWD.
• Appeal: Yes — folded into CAFC No. 2025-1286. The May 2026 companion-case order identifies 2025-1286 as arising from IPR2023-00454, IPR2023-00455, IPR2023-01141, and IPR2023-01142. Micron (not Samsung) argued as appellee at the 2026-09-09 hearing; Samsung filed a Notice of Non-Participation on 2026-08-18 and the caption was revised accordingly on 2026-09-09.
• Defensive value: Functionally a duplicate of 00455 — it adds Micron (and its affiliates) as petitioners and thus as § 315(e)(2) estoppel parties, but it changes nothing about the claim-level outcome. For a defendant, treat 00455 and 01142 as one trial with one invalidity verdict.

Filing-date caveat: PTAB docket data (Patexia, GreyB/IPVerse, Docket Alarm) gives IPR2023-01142 a 2023-07-28 filing date. Netlist's own SEC disclosure (10-K/10-Q language) states Micron "also filed a Petition for IPR of the '215 Patent (Case No. IPR2023-01142)" on 2023-05-08. These conflict; I have not resolved which is authoritative and am reporting both rather than picking one.

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Strategic summary

Claim status. There is no surviving claim of US 9,858,215 at the PTAB. The 2024-07-30 FWD in IPR2023-00455 held claims 1–29 unpatentable, and the Board titled the decision "Determining All Challenged Claims Unpatentable." Since claims 1–29 is the entire claim set, there is no untested claim and no sustained claim — the categories are simply "canceled, subject to appeal." Independent claim 1 and independent claim 21 both fell, along with every dependent claim. The one caveat that matters: this is a Board judgment now on appeal, not a Federal Circuit affirmance. Until 2025-1286 (consolidated with 2025-1296) is decided, the technically correct statement is "all claims held unpatentable in a final agency decision that is on appeal," not "all claims canceled by a mandate." Compounding this for Netlist: the patent's adjusted expiration is 2025-09-15 per its Google Patents record ("Expired – Fee Related"), so the enforcement window has closed regardless of the appeal.

Estoppel landscape. Estoppel under § 315(e)(2) runs against Samsung Electronics Co., Ltd., Samsung Semiconductor, Inc., Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC — the identified real parties in interest — and their privies. Those parties are barred from raising in district court any ground they raised or reasonably could have raised in IPR2023-00455/01142, i.e., the Perego + JESD79-2 family (with Ellsberry, Halbert, Matsui). But estoppel is party-specific: a new defendant who was not a petitioner or privy is not estopped, and the Perego-based grounds and the Board's favorable "rank can be one memory device" construction remain fully available to it. In practice a new defendant's cheapest path is not to re-litigate invalidity but to cite the FWD as persuasive authority and to raise the expired term, laches/§ 287 limitations, and the six-year damages lookback. Conversely, if you are Samsung or Micron, the estoppel is real but largely academic — the claims are already invalid in the forum that mattered.

Pattern signals. The petitioner structure is the notable feature: Samsung led (IPR2023-00455, filed 2023-01-10) and Micron joined as a co-petitioner via its own joinder petition (IPR2023-01142), with both companies naming themselves and their product/operating subsidiaries as RPIs. So it is not "the same petitioner filing multiple IPRs on this patent" — it is two competitors coordinating on one patent, each separately challenging the sibling '417 patent (Samsung: IPR2023-00454; Micron: IPR2023-01141). Unified Patents appears in this patent's record only as litigation-data/litigation-support references in the Google Patents "Family has litigation" block — the petitioning parties here are Samsung and Micron, not a defensive aggregator, so I would not describe Unified Patents as a petitioner in the chain. Netlist, for its part, is a highly aggressive PTAB appellant (multiple appeals in this family, plus appeals in 2024-2304, 2025-1296, 2025-1936) and has also requested Director Review in this family (denied 2024-10-08). Related district court activity continues in parallel — E.D. Tex. 2:22-cv-00293 (Samsung) and 2:22-cv-00294 (Micron), plus Idaho D. Ct. 1:25-cv-00323 (Micron's bad-faith-assertion action against Netlist) — so expect hybrid litigation/PTAB pressure rather than a clean PTAB-only story.

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Recommended next steps

1. Defendant-facing bottom line. Every asserted claim of '215 — claims 1–29 — was held unpatentable in the 2024-07-30 FWD in IPR2023-00455, a decision in which Micron was a joined petitioner via IPR2023-01142. If you are a defendant and Netlist's demand letter cites claims 1–29 (or any of them), lead with the FWD disposition language: "we determine Petitioner has proven by a preponderance of the evidence that claims 1–29 of the '215 patent are unpatentable." Full text: FWD, IPR2023-00455, Paper 45. Board decisions in these proceedings are also retrievable via USPTO PTAB E2E / the PTAB Decisions portal under case IPR2023-00455.

2. Do not represent the invalidity as final. The FWD is on appeal at CAFC No. 2025-1286, Netlist, Inc. v. Micron Technology, Inc.. Argument was held 2026-09-09 (panel: Dyk, Linn, Chen); no decision has issued as of 2026-09-28. Frame it as a final agency determination entitled to weight, not an affirmed judgment.

3. Milestones to track. (a) CAFC decision in 2025-1286 / consolidated -1296; (b) any petition for rehearing/en banc after that; (c) the May 14, 2026 companion-case order grouping 2024-2304, 2025-1286, -1296, and 2025-1936 before one merits panel — a ruling in the '215 case may arrive alongside rulings on the '417 and other Netlist patents, so read them together. There are no PTAB trial-stage deadlines left to monitor on '215 — the trial is over and the appeal is fully briefed and argued.

4. Erase "no PTAB activity" from your risk model. The ODP block is not reliable here. Two instituted IPRs, two FWDs, an adverse-claim-construction loss for the patent owner, a denied Director Review request, and a consolidated Federal Circuit appeal are all on the public record. Any due-diligence memo that relies solely on the ODP "no proceedings" flag would materially understate the invalidity risk to a Netlist assertion on this patent — and, symmetrically, would overstate the patent's residual value.

Confidence flags: The panel roster, filing/institution/FWD dates, claim scope of challenge (1–29), statutory basis (§ 103(a)), prior-art references, and the "all challenged claims unpatentable" disposition are well-corroborated across the FWD text, PTAB docket aggregators, and Netlist's SEC disclosures. Two items are not fully reconciled and are flagged above rather than asserted: the IPR2023-01142 filing date (2023-07-28 vs. Netlist's 2023-05-08 disclosure) and whether Judge Galligan sat on the FWD panel. I found no third '215 proceeding, no settled proceeding, and no denied-institution proceeding on this patent; the ODP block's report of no proceedings is contradicted by the sources cited.

I'll research the assignment records and litigation context for US 9858215 before reconstructing the chain.

Let me search for the specific reel/frame records and the SVIC security interest filings.

Let me pin down the 2017 inventor assignment record and the litigation start dates for this patent.

Ownership Reconstruction — US 9,858,215 B1 ("Memory module with data buffering")

Data-source note (read first): I could not directly query the USPTO Assignment Center UI from this session. The reel/frame numbers below are grounded in (a) the Google Patents legal-events feed for this patent and (b) PTAB exhibit lists that reproduce the recorded assignment documents themselves as exhibits — EX2006 ("Security Interest Assignment… REEL: 037150 FRAME: 0897") and EX2007 ("Release of Assignment, Reel No. 065629, Frame No. 0330") in the Samsung/Micron IPRs against Netlist. Verify at https://assignmentcenter.uspto.gov/ (search "9858215"). One entry (the 2017 inventor assignment) is confirmed only by the legal-events feed; I could not retrieve its reel/frame and say so rather than guess.

Inventors

• Both are Netlist insiders — the same two names appear as the founding inventors across the entire Netlist memory-module family ('436, '386, '537, '274, '912, '150, '536, etc.), and the applicant of record for the '486 application is "Netlist, Inc., Irvine, CA."
• No unusual departure pattern. Neither inventor left Netlist within 12 months of filing, and no inventor-to-third-party assignment exists in this chain. This is the opposite of the pre-fire-sale pattern: the inventors and the assignee are the same company, and the company is still on the patent.
• The continued presence of the founder-inventors as the named inventors on later continuations (through 2017–2019 filings) corroborates that this is internal, organic R&D — not an acquired/shelled portfolio.

Original assignee

Netlist, Inc. — Delaware corporation, principal place of business 175 Technology Drive, Suite 150, Irvine, CA 92618.

• Primary line of business: design and manufacture of high-performance server memory modules. Netlist commercialized its "load isolation / rank multiplication" architecture in the HyperCloud LRDIMM (shipped in volume 2013 to IBM and HP per its ITC complaint) and later the HybriDIMM. The claims of '215 (data buffering / selective rank isolation on a memory module) read directly on Netlist's distributed-buffer product line.
• Did they ship a product embodying the claims? Yes. Netlist's own ITC §337-TA-1089/1023 filings describe domestic-industry products built on exactly this load-reduction/distributed-buffer technology, and Netlist has stated its engineers developed it over nine years — i.e., the patent is tied to a real product, not a paper portfolio.
• Current status: Operating, publicly traded (OTC: NLST), not acquired, not dissolved, not in bankruptcy. The company has, however, shifted most of its economic activity toward IP monetization and litigation (multiple nine-figure verdicts and ITC actions). It remains the record owner of '215.

Assignment timeline

Detail:

• 2015-11-18 (executed) / recorded 2015-11-20 — Reel 037150/0897

  • Conveyance: Security Interest (short-form IP security agreement recorded against the patent estate, including the '486 application that issued as '215)
  • Assignor: Netlist, Inc. (Grantor)
  • Assignee: SVIC No. 28 New Technology Business Investment L.L.P. (Secured Party) — a Korean limited liability partnership affiliated with Samsung Venture Investment Corporation (Samsung's corporate VC arm)
  • Correspondent: not retrievable in this session — flagged as a data gap. This is the one field I could not confirm from the recorded face of the document.
  • Context: securitization — collateral grant under the Nov. 18, 2015 Senior Secured Convertible Promissory Note and Warrant Purchase Agreement; netlist did not sell title, it pledged the patent as loan collateral. (Interesting juxtaposition: the secured lender is a Samsung VC affiliate, and Netlist later sued Samsung in 2021–2022 — but there is no evidence this collateral link drove the assertion.)

• recorded 2017-11-10 — reel/frame not retrieved

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Bhakta, Jayesh R.; Solomon, Jeffrey C. (the inventors)
  • Assignee: Netlist, Inc.
  • Correspondent: not retrieved (data gap).
  • Context: inventor-to-company assignment — the title link from inventors to the operating assignee. Its late recording date (2017) relative to the 2015 filing suggests a confirmatory/recordation-cleanup filing, not a contemporaneous transfer. Do not read this as a "transfer"; these are the original inventors assigning to their own employer.

• recorded 2023-11-20 — Reel 065629/0330

  • Conveyance: Release by Secured Party
  • Assignor: SVIC No. 28 New Technology Business Investment L.L.P.
  • Assignee: Netlist, Inc.
  • Correspondent: not retrieved (data gap).
  • Context: lien release / collateral discharge — SVIC released its security interest, returning the patent to Netlist free and clear. No transfer of ownership occurred at any point; Netlist held title continuously.

If the Assignment Center returns nothing additional: that is consistent with what I see — there are no post-issuance ownership transfers, no shell-entity assignments, and no NPE in the chain. Every recorded event is either a company-to-lender security pledge, its inventor-side confirmatory assignment, or the lender's release.

Timeline diagram

timeline
    title Ownership of US 9858215
    2004 : Priority application filed by inventors
    2015 : Continuation application filed by Netlist
    2015 : IP security interest recorded to SVIC
    2017 : Inventor assignment to Netlist recorded
    2018 : Granted as US 9858215
    2022 : Netlist asserts patent against Samsung
    2023 : SVIC security interest released
    2025 : Patent expires on fee lapse

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only LLC in the chain (SVIC No. 28 New Technology Business Investment L.L.P.) is a secured lender, not an assignee of title; a security interest recorded at Reel 037150/0897 is not an ownership transfer. Title has resided in Netlist, Inc., a Delaware operating corporation with a verifiable product line (HyperCloud, HybriDIMM), throughout. No "IP Holdings / Licensing / Ventures" single-member LLC ever appears.

2. Known asserter in the chain — Not present (on the enumerated lists). No assignee matches Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, or any Spangenberg entity. Caveat and nuance: the current assignee Netlist is a very high-frequency plaintiff (Samsung 2:21-cv-00463, 2:22-cv-00293, 2:23-cv-00628; Micron 2:22-cv-00203; ITC §337-TA-1023/1089/1385; plus the Idaho 1:25-cv-00323 action), and it therefore appears in Unified Patents' patent-owner database. That makes it an aggressive litigant — but it litigates its own patents against actual competitors, which is the operating-company-assertion profile, not the NPE-licensing profile.

3. Repeat correspondent across the chain — Unclear / insufficient data. I could not retrieve the correspondent of record for any of the three entries (037150/0897; the 2017 inventor assignment; 065629/0330). I will not invent a name. Note only that the several assignments were recorded years apart and involve different parties (a lender affiliate on one side, the company on the other), which is weak circumstantial evidence against a single repeat filing agent — but this is not a finding. Action item for verification: pull the correspondent field for 037150/0897 and 065629/0330 at the Assignment Center; if both name the same attorney/firm, that is a genuine recurrence signal to log against the Netlist family.

4. Cascading transfers — Not present. Three recorded events span 2015 → 2023 (eight years); none is an ownership transfer, and the sequence ends where it began (Netlist). There is no chain of LLC-to-LLC hops, no shared registered-agent address, no <24-month cascade.

5. Pre-litigation transfer — Not present. The last recorded event touching this patent before the earliest assertion was the 2015 security interest (recorded 2015-11-20); the patent was first asserted (added by amendment) in Netlist v. Samsung, EDTX 2:22-cv-00293, filed 2022-08-01. Nothing was transferred within six months of any suit — the 2023 release came after litigation was underway. No venue/standing-manufacturing transfer.

6. Bankruptcy fire-sale — Not present. Netlist has had genuine financial distress (the SVIC secured loan itself is a distress artifact) but has never filed Chapter 7/11, and the patent was never sold in a proceeding. The 2023 release restored clean title to the same original owner.

7. Privateering — Not present. Privateering requires an operating company selling to an NPE that sues on its behalf. Here the operating company is the plaintiff and retains title; there is no intermediary assertion vehicle and no evidence of a covert backer. (The collateral relationship with a Samsung VC affiliate is a factual curiosity, not privateering evidence.)

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT, Unified, or OIN. Netlist's patents are the target of Unified-petitioned IPRs (IPR2023-00455, IPR2023-01142), not contributed to a defensive pool.

Additional neutral finding — the patent is now expired. Legal status is Expired – Fee Related, with an adjusted expiration of 2025-09-15. Whatever litigation value remains runs through accrued-damages appeals (e.g., CAFC 25-1286 and the consolidated Netlist–Samsung appeals), not prospective licensing.

Verdict

Operating-company assertion.

Netlist, Inc. — the original and continuous record owner of '215 — is an operating memory-module company that ships products (HyperCloud LRDIMM, HybriDIMM) embodying the load-isolation/data-buffering claims, and it asserts this patent directly against actual competitors (Samsung in EDTX 2:22-cv-00293; Micron via 2:22-cv-00203), rather than through any shell or licensing vehicle. The only assignments on record are a 2015 security interest to SVIC No. 28 at Reel 037150/0897, an inventor-to-company assignment recorded 2017-11-10, and the 2023 release by secured party at Reel 065629/0330 — a collateral pledge and its discharge, with zero shell-entity transfers, zero NPE-list assignees, and no pre-litigation transfer. The chain terminates at the original operating assignee, so none of the eight NPE signals is present except the unverifiable correspondent field (signal 3), which I flag as a data gap rather than a finding.

Verify: https://assignmentcenter.uspto.gov/ — search patent number 9858215; also https://portal.unifiedpatents.com/patents/patent/US-9858215-B1 for the litigation/IPR docket.

I'll search for the specific patent number and its cited references.

I found key sources including the patent's own "References Cited" section. Let me dig deeper into the specific cited references.

Let me get details on the key references and the full cited-reference list.

Bottom line up front

I was able to pull US 9,858,215 B1's own front‑page "References Cited" listing only partially — the Google Patents render supplied in the user message truncated before the (56) References Cited block, and the OCR'd copies of that block that I retrieved from litigation/PTAB exhibits are mangled in several places. So rather than present a fabricated clean list, I'll (a) give the verified/partially-verified face citations with explicit OCR flags, and (b) give the far more important set — the references actually asserted against this patent in PTAB proceedings, which is where a §102/§103 analysis of '215 legitimately lives.

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1. Document identification (authoritative, from the supplied full text)

Why the priority date controls everything below: because the earliest priority is 2004‑03‑05 (with a January 19, 2005 provisional in the chain), any reference published after that date is §102 prior art only if it qualifies under pre‑AIA §102(e)/(g) (earlier effective filing date). This is the crux of the disputes described in §4 below. (Source: https://patents.google.com/patent/US9858215/en)

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2. References printed on the face of '215 (partial; OCR caveats)

Retrieved from the patent's own (56) block as reproduced in PTAB exhibit copies:
https://www.docketalarm.com/cases/PTAB/IPR2023-00203/Micron_Technology_Inc._v._Netlist_Inc/docs/03-09-2023-Patent_Owner/Exhibit-2109-EX2109_US9858215.pdf

U.S. Patent Documents (verified subset):

4,218,740 (8/1980) Bennett et al. · 4,249,253 (2/1981) Gentili et al. · 4,368,515 (1/1983) Nielsen · 4,392,212 (7/1983) Miyasaka et al. · 4,571,676 (2/1986) Mantellina et al. · 4,592,011 (5/1986) Mantellina et al. · 4,623,429 (12/1986) Lewandowski et al. (OCR variants: "4,633,429 … Tewanovsky") · 4,670,748 (6/1987) Wilkins (OCR variant: Williams) · 4,706,214 (11/1987) Kassai · 4,739,473 (4/1988) Ng · 4,866,603 (9/1989) Chiba · 4,958,322 (10/1990) Kosugi et al. (OCR: 4,958,522/4,958,532) · 4,961,204 (10/1990) Tanaka et al. · 4,961,117 (10/1990) Shubai et al. · 4,980,853 (12/1990) Morgan · 5,060,188 (10/1991) Zulian et al. · 5,272,654 (12/1993) Alexander et al. · 5,313,624 (5/1994) Harriman · 5,345,412 (9/1994) Shiratuchi · 5,357,478 (10/1994) Kikuda et al. · 5,388,072/5,388,240 (2/1995) Okamoto et al. · 5,392,252 (2/1995) Rimpo et al. · 5,426,753 (6/1995) Moon · 5,463,500/5,463,509 (10/1995) Watanabe · 5,483,497 (1/1996) Mochizuki et al. · 5,485,589 (1/1996) Koets et al. · 5,495,435 (2/1996) Sugahara · 5,513,135 (4/1996) Dell et al. · 5,532,954 (7/1996) Bechtolsheim et al. · 5,537,584 (7/1996) Miya et al. · 5,541,448 (8/1996) Carpenter · 5,559,970 (9/1996) Sharma (partial) …

Foreign Patent Documents:

• EP 1 816 570 A2 (Aug. 2007)
• JP 2009‑237492 (the face OCRs this to a "9/1997" date, which is internally inconsistent with a 2009 Japanese publication number — flag as unreliable)

Other publications / non-patent literature:

• US 6,832,284 B1, Dec. 2004, Perego et al. (printed as "(withdrawn)")
• JEDEC JESD79D, DDR SDRAM Specification, Feb. 2004 (incorporated by reference in the spec)

Character of this face list: it is dominated by pre‑2000 generic DRAM, SIMM/DIMM, stackable‑module, address‑remap and termination art. None of these was applied as a §102 anticipation of '215 in any proceeding I could retrieve — they are examiner/examiner‑style citations, which is why the substantive attack on '215 came from a different set of references (Perego, Ellsberry, Halbert, Amidi, and the JEDEC standards).

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3. The references actually asserted against '215 (the ones that matter for §102)

Sources: Samsung's IPR2023‑00455 petition and exhibits (https://storage.courtlistener.com/recap/gov.uscourts.txed.[216364](/patent/216364)/gov.uscourts.txed.216364.88.3.pdf), the Wolfe declaration (https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1554310](/patent/1554310)/download-documents?artifactId=RN3ykIJTJhIKs9wHxga9-vjWavEtkRCDJmWScbyZZrSg0DzseCAPhTc), and Patent Owner's hearing demonstratives (https://www.docketalarm.com/cases/PTAB/IPR2023-00455/Samsung_Electronics_Co._Ltd._v._Netlist_Inc/docs/04-30-2024-Patent_Owner/Exhibit-2036-EX2036_POs_Oral_Hearing_Demonstratives.pdf).

Grounds as pleaded in IPR2023‑00455 against claims 1–29:

• Ground 1: Perego in view of JESD79‑2
• Ground 2: Ground 1 + Ellsberry
• Ground 3: Ground 1 + Halbert
• Ground 4: Ground 1 + (a "Matsui"/"Matsui2" reference dealing with termination circuit 213) — number not verified

3.1 U.S. Pat. No. 6,832,284 B1 — Perego et al. ("Configurable width buffered module")

• Citation: U.S. 6,832,284 B1, issued Dec. 14, 2004; the '215 face lists it under "Other Publications." (Exact filing date not verified in the retrieved record; Petitioners rely on it as §102(e) art.)
• Description (per the petition's own record cites): a memory module (e.g., 400; and buffer device 391/405) with a buffer device between the memory controller and the memory devices that "transceives and provides isolation between signals interfacing to controller 310 and signals interfacing to the plurality of memory devices 360" (6:12–15); memory devices 410a–h arranged on multiple channels 415a/415b (Fig. 4A); "two channels 415c and 415d may transfer information simultaneously and the memory devices on the other two channels 415a and 415b remain in a ready or standby state until called upon"; interfaces 510/590, 520a/520b; multiplexers 530a/530b; transceivers 575; termination 580; multiplexing/demultiplexing logic in 591/597.
• §102 exposure: Perego is the only reference argued to teach every element of independent claim 1 in a single document, i.e., the closest thing to a §102 anticipation on this record — but note that the Board/Petitioner framed it as §103 over Perego + JESD79‑2, not pure §102. The §102‑relevant claims are the independents: claim 1 (memory module: ranks + buffer between each rank and the memory bus + logic supplying different first/second control signals per command) and claim 21 (method of operating such a module). Under Netlist's own broader construction (ranks sharing the same data lines), Petitioners also argued Perego reads on the "forks"/separate‑data‑path limitations.
• Key vulnerability to Perego: Perego is not JEDEC‑chip‑select based; Netlist's counter was "no input chip‑select signals, no plurality of ranks, no CAS‑latency claim elements" and no motivation to combine with JEDEC.

3.2 Ellsberry — U.S. Pub. No. 2006/0277355 A1 ("Capacity-expanding memory device")

• Citation: US 2006/0277355 A1, Sanmina Corp.; filed June 1, 2005; published December 7, 2006.
• Description: rank multiplication / capacity expansion on a module — the transcript describes it as "teaching rank multiplication in literally like the exact same way as what Netlist later disclosed," with chip‑select signals entering the module, JEDEC compatibility, and (Fig. 8B) adding one clock cycle to the CAS latency to account for a data buffer.
• §102 exposure: directed at the latency/registered‑buffer dependent claims — claims 3, 4, 6 (determining a latency value), and 8 (buffer comprising "combinatorial logic, registers, and logic pipelines" and registering "an additional clock cycle") — and, more broadly, the rank‑selection claims of independent claims 1/16/21 if they are read to cover rank multiplication.
• Dispositive §102(e)/(g) fight: Netlist's position is that Ellsberry is not prior art at all: "Ellsberry was filed Jun. 1, 2005. The '087 provisional application supports the challenged claims and was filed on January 19, 2005, prior to Ellsberry." So Ellsberry's §102 status turns entirely on whether the challenged '215 claims are entitled to the Jan. 19, 2005 (Prov. 60/645,087) date. Petitioners also argued "simultaneous invention" (Ellsberry filed within ~1 month of the Netlist chain).

3.3 Halbert — U.S. Pub. No. 2008/0104352 A1 ("Memory system including a high‑speed serial buffer")

• Citation: US 2008/0104352 A1, assignee Advanced Micro Devices; one retrieved source gives filing 2006‑10‑30 and publication 2008‑05‑01 (exact filing date not verified).
• Description: a memory system with a data buffer; includes timing diagrams showing that the buffer adds delay to the data signal, and shows two separate ranks (highlighted in the demonstratives). Used as Ground 3 = Perego + JESD79‑2 + Halbert.
• §102 exposure: aimed at the buffer‑delay / extra‑registered‑clock‑cycle limitations (claims 8, 20; and the CAS‑latency‑dependent claims 3, 4, 6, 19). Because it publishes in 2008 — well after '215's priority chain — Halbert can only be §102(e) art if the challenged claims lose the early priority date; on its face it is not §102(b)/(a)(1) art against '215's 2004/2005 dates. Treat any §102 characterization of Halbert as contingent.

3.4 Amidi — U.S. Pub. No. 2006/0117152 A1 ("Transparent four rank memory module for standard two rank sub‑systems")

• Citation: US 2006/0117152 A1, Smart Modular Technologies; filed Jan. 4–5, 2004 (priority 2004‑01‑05); published June 1, 2006.
• Description: a four‑rank module that emulates a two‑rank module via CPLD 410, using CS0/CS1 plus the extra address bit (A12) to select which of four ranks is active; SPD data characterizes the module as two ranks of higher density.
• §102 exposure: because its filing date (Jan. 2004) precedes '215's 2004‑03‑05 priority, Amidi is genuine pre‑AIA §102(e) art for the rank‑selection/density‑multiplier aspects — the ancestors of '215 in this family were in fact rejected/re‑examined over "Amidi in view of the JEDEC Standards" (Amidi used under §102/§103, per reexam 95/000,578 history). It maps to claim 1's rank structure (first/second ranks, different rank‑select control) and to dependent claims reciting emulation/SPD characterization. Note Amidi does not itself disclose the data buffer, so it cannot anticipate claim 1 alone; it is a §102 candidate only against claims lacking the buffer/control‑signal limitations.
• Reexam record: https://www.docketalarm.com/cases/PTAB/IPR2023-00203/Micron_Technology_Inc/docs/11-18-2022-Petitioner/Exhibit-1010-3-EX1010___Prosecution_History___95000578___Part_3_pages_1567_2184.pdf

3.5 JEDEC standards (printed publications, §102(b) if pre‑critical‑date)

• JESD79‑2, DDR2 SDRAM Specification, published September 2003 — relied on for additive latency AL, CAS latency CL, R/W latency (RL = AL + CL), and seamless bursts. It is §102(b) art against any '215 claim not entitled to an earlier date.
• JESD79D (Feb. 2004) is incorporated by reference in the '215 specification.
• JESD21‑C (SPD standard) — relied on for SPD fields (bytes 3, 4, 13, 14, 17) characterizing the module as fewer/higher‑density ranks; used in the Amidi/JEDEC combinations.
• §102 exposure: the latency and "registered additional clock cycle" claims (3, 4, 6, 8, 19, 20) and the SPD‑based claims.

3.6 "Matsui" / "Matsui2" (Ground 4 reference)

The petition record refers to a reference whose "termination circuit 213 … interfaces with memory devices and provides external termination for data signals." I could not verify its number, title, inventors, or dates from the retrieved record, and I will not guess. If it exists as pleaded, its §102 target would be the termination/ODT‑type limitations in the '215's dependent claims (the spec's FIGS. 18–19, ¶¶ discussing ODT circuits 616/626/636 and termination assembly 630).

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4. Which claims are, realistically, exposed under §102 (mapped)

Important caveat on the §102 framing: in the record I retrieved, the '215 challenges were pleaded as §103 obviousness combinations, not as standalone §102 anticipation grounds. A pure §102 case against '215 would have to rest on Perego alone (or Amidi for the non‑buffer claims), and Netlist's defenses are precisely that no single reference discloses the buffer‑between‑ranks‑and‑bus plus per‑command differing control signals as claimed.

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5. What I could not verify (stated explicitly, not guessed)

1. The complete, OCR‑clean "References Cited" list printed on '215's face. The Google Patents text supplied in the user message omits the (56) block entirely, and the litigation exhibits I retrieved are partially garbled (patent numbers/names swapped, e.g., "5,747,643 / 5,272,654," "4,623,429 / 4,633,429," "4,958,322 / 4,958,522"). I therefore gave only a verified subset and flagged the rest.
2. The literal text of claims 1–29 of '215 — not present in the supplied full text and not retrieved. All claim mapping above is derived from the IPR/reexam record.
3. Exact filing dates and assignees for Perego (6,832,284) and Halbert (2008/0104352). Only issue/publication dates and one publication‑date data point for Halbert were retrievable. Do not treat those filing dates as confirmed.
4. The Ground‑4 "Matsui"/"Matsui2" reference's identity.
5. Whether the Board's Final Written Decisions in IPR2023‑00455 / IPR2023‑01142 found any claim anticipated (as opposed to obvious). The Google Patents page merely flags "Final Written Decision" for both; I did not retrieve the outcomes.

If you want, I can next attempt to (i) pull the full rule‑by‑rule (56) list from the issued‑patent PDF, and (ii) retrieve the IPR2023‑00455 Final Written Decision to confirm which claims, if any, were held anticipated versus obvious.

I'll start by grounding this analysis in the actual prior-art materials associated with this patent.

Let me pull the specifics of the prior-art references and the PTAB's findings.

Let me get the Board's specific findings for the '215 patent claims.

Obviousness Analysis — U.S. Patent No. 9,858,215 B1 (“Memory Module with Data Buffering”)

Note on dates: The system header for this session gives today as 2026‑09‑28 (and the patent page as fetched 2026‑09‑28), while your instruction line says April 26, 2026. I have not reconciled these; where a date matters I cite the document’s own date rather than “today.”

Note on the “Prior Art section”: The Google Patents page for US 9,858,215 supplies (a) Prior art keywords: memory, data, command, memory module, burst; (b) Prior art date: 2004‑03‑05; and (c) the cited-reference list on the face of the patent (Perego US 6,832,284, JP 2009‑237492, EP 1 816 570 A2, etc.) plus the related-family members. The 285‑item “Patent Art” list surfaced on the Unified Patents mirror (portal.unifiedpatents.com/patents/patent/9858215) is the fuller version of that section. I use all three, and then cross-check them against the actual §103 grounds that were litigated, because those grounds identify which of those references actually teach the claim elements.

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1. The claim to be tested

Claim 1 (the independent module claim; claim 21 is the parallel independent method claim) requires, in substance:

The commercially and legally significant dependents are: claims 3–4 / 24–25 (overall CAS latency one cycle greater than the actual operational CL of the memory ICs); claims 8 / 17 / 20 (buffer registering an additional clock cycle of data transfer); claims 9–11 / 23 (chip-select signals as inputs to the module); claims 12–13 / 28–29 (back-to-back adjacent read commands, and the buffer preventing the first burst of data strobes from interfering with the second); claims 14–15 / 26 (a circuit component providing a first or second data path in response to the control signals).

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2. Prior art that matters, drawn from the page’s Prior Art section

Critical realism check: the page’s own prior-art lists include several items that are not prior art to this patent — e.g., US 7,881,150, US 8,081,536, US 8,516,188, US 10,489,314 — because they are members of the same Netlist continuation family. Those cannot be used under §103 (they are the same invention). The usable art is the third-party art above.

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3. Combination A (the strongest): Perego + JESD79‑2 → claims 1–29

This is the combination that was actually run and that succeeded.

Mapping

Motivation to combine (three independent, each sufficient)

1. Express disclosure. Perego itself discloses DDR2 DRAM devices (10:54–59) and expressly says “other memory devices may be implemented” — so the JEDEC specification for DDR2 (JESD79‑2) is the natural, self-identified companion document.
2. Perego is not Rambus-limited. The Board credited Perego’s disclosure of bussed topologies as alternatives to point-to-point links (3:41–47; 8:42–47), individual control lines including RAS/CAS (9:43–45), and a 64-bit module width (14:16–23) — all JEDEC-compatible. A POSITA therefore does not have to “change Perego’s principle”; it selects an embodiment Perego already describes.
3. Market forces (KSR). JEDEC-compliant modules dominated the market by the mid-2000s — a point established partly through Netlist’s own expert. A POSITA seeking to use Perego’s data buffering in a saleable product had a strong market-driven reason to implement it in a JEDEC-compliant DIMM.

Why the obviousness case is strong on this combination

• The “different control signals” limitation (1.f.2) is satisfied by ordinary rank/channel decoding: signals that enable rank A/Port A differ from those that enable rank B/Port B.
• The remaining dependents fall down a short ladder: the CAS-latency claims (3–4, 24–25) are met by the well-known consequence that inserting a buffering stage adds a cycle — the patent itself concedes this (“a one-clock cycle time delay, which is equivalent to a registered DIMM,” ’215 at 20:22–47). The Board found it obvious to add a cycle to the overall CL while staying within JESD79‑2 timing.
• No credible secondary consideration was presented; Netlist offered no objective evidence of non-obviousness.

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4. Combination B: Perego + JESD79‑2 + Ellsberry → same claims, stronger on the rank-multiplication and strobe-collision dependents

Ellsberry is the reference that makes the purpose of the buffer explicit and gives a second, independent teaching for the “different control signals” and for claims 12–13 / 28–29.

What Ellsberry teaches:

• A control unit (1202) and bank switch (1204) that take a single chip-select (CS0) and generate two per-rank chip selects, CS0A and CS0B — and, in the four-rank version of its Fig. 13, CS0A/CS1A/CS0B/CS1B. Commands go to the target bank, with NOP/DESELECT to the non-targeted bank.
• Two bidirectional drivers (402, 404) on separate ports (Port A → bus 234; Port B → bus 236), each carrying DQ and DQS, with the drivers driving the system bus 230 one at a time. Ellsberry expressly states that this “reduces resistive and/or capacitive loading of the data bus” ([0031]).
• Explicit cost/economics motivation: two smaller-capacity DDR devices emulate one double-capacity device “without the need for additional chip select lines on the main memory bus” ([0026]).

Motivations:

1. Both references buffer module data lines → combining them improves the same devices in the same way, a predictable variation.
2. Both use JEDEC DDR/DDR2 memory devices, so JESD79‑2 is common ground; Ellsberry [0008]–[0009], [0026], [0046] describe module interfaces aligned with JESD21‑C.
3. Ellsberry supplies the cost-saving rank-multiplication rationale (buying two cheaper lower-density parts instead of one expensive higher-density part) that Perego alone does not articulate.
4. For claims 12–13 / 28–29, Ellsberry’s use of separate drivers per port means the post-amble of burst 1 is never driven onto the shared bus while the pre-amble of burst 2 begins — exactly the interference the ’215 patent claims to prevent, and the reason the ’215 patent’s own specification admits the alternative workaround (the memory controller inserting an extra cycle for “BBARX”).

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5. Alternative and supplementary combinations

Combination C — Perego + Amidi (+ JESD79‑2). Amidi (US 2006/0117152) is a “transparent four-rank module for two-rank sub-systems,” i.e. it takes the two chip-selects + an extra address bit a two-rank controller provides and generates four gated CAS/chip-select signals. That is a direct teaching of 1.d + 1.f (rank selection by decoding an address bit into rank-enable control signals) and of the density-transition-bit concept the ’215 specification touts as its “memory density multiplication.” The motivation is identical (cost per bit of lower-density devices, plus the design goal of transparency to an unchanged BIOS/motherboard). Caveat: the exact filing/priority dates of Amidi relative to the ’215 claims’ effective filing dates should be verified before relying on it as §102(e)/§103 art; it appeared in the record with an early-2004 priority but I have not independently confirmed that date here.

Combination D — Perego + JESD79‑2 + Halbert and Perego + JESD79‑2 + Matsui. Both were pled as separate grounds in IPR2023‑00455 and were not reached because Ground 1 disposed of all claims.

Combination E (Rambus-line supplementation). US 7,464,225 (Rambus) — “Memory Module Including a Plurality of Integrated Circuit Memory Devices and a Plurality of Buffer Devices in a Matrix Topology” — appears in the page’s Patent Art list and independently evidences that buffering the module data path between ranks and the bus was known; it is useful as corroborating art, though less central than Perego.

Combination F (older, simpler art). US 5,313,624 (“DRAM Multiplexer,” Next Computer) and US 6,438,062 (IBM, multiple-bank command for synchronous DRAMs), both in the page’s prior-art list, corroborate the two core mechanisms — multiplexing two memory arrays onto one port, and generating multiple bank/rank commands from one — but they predate DDR2 signaling and would be better used as evidence of the general knowledge of a POSITA than as primary references.

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6. Level of ordinary skill and why it matters here

The Board adopted (with “at least” struck) the petitioner’s definition: an advanced degree in electrical/computer engineering plus ~2 years, or a bachelor’s plus ~3 years, with familiarity with JEDEC DDR/DDR2 and JESD21‑C standards, tri-state buffers, flip-flops, registers, ASICs and CPLDs. At that level, the asserted combinations are not merely “obvious to try” — they are the straightforward substitution of one standardized, dominant interface for another while keeping the known benefit of data buffering.

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7. Secondary considerations

• No objective evidence of non-obviousness was credited. Netlist’s response to the “simultaneous invention” argument was its only objective-indicia submission, and it did not identify unexpected results, licensing nexus, or industry praise tied to the claim scope.
• “Simultaneous invention” cuts the other way. Ellsberry, filed close to the ’215 family’s earliest filings and independently solving rank multiplication and the back-to-back-read collision problem, is evidence of the level of skill in the art at the critical time, not of non-obviousness.
• Narrowing amendments don’t help. The related ’912 patent’s claims were narrowed during reexamination to require gated CAS/chip-select signal generation from row address, bank address, chip-select, and PLL clock signals (see the E.D. Tex. briefing quoting the ’912 reexam record). That narrowing was expressly to distinguish Amidi-type art — which concedes that the broader concept was old.

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8. Outcome and current status (as ground truth)

• IPR2023‑00455 (Samsung; Micron joined via IPR2023‑01142): Final Written Decision issued 2024‑07‑30, holding claims 1–29 unpatentable under pre‑AIA 35 U.S.C. §103(a) over Perego + JESD79‑2; the Ellsberry, Halbert and Matsui grounds were not reached. Petitioner’s motion to exclude was dismissed as moot. Sources: IPR2023‑00455, IPR2023‑01142, FWD text.
• Parallel IPR2023‑00454 on the child patent US 11,093,417 reached the same result over the same combination (1,093,417 shares this specification).
• Appeal: the Federal Circuit, by order dated 2026‑05‑14, consolidated Appeal Nos. 2024‑2304; 2025‑1286, ‑1296; and 2025‑1936 as companion cases before one merits panel (order PDF). Netlist’s appellate attack is confined largely to the motivation to combine (that Perego is Rambus-specific) — it did not seriously contest that the art teaches the limitations (appellee brief).
• Litigation: E.D. Tex. 2:22‑cv‑00293 and ‑00294; N.D. Idaho 1:25‑cv‑00323; all listed on the patent page.
• Status: “Expired – Fee Related,” adjusted expiration 2025‑09‑15.

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9. Bottom line

Under §103, Perego in view of JESD79‑2 renders claim 1 obvious, and the dependent claims fall with it — the buffer/register/rank architecture and the “different control signals” limitation are all present in Perego once it is implemented as the JEDEC DDR2 module its own disclosure contemplates. Adding Ellsberry (US 2006/0277355) supplies the explicit cost-driven rank-multiplication rationale and per-port strobe isolation that directly answers the rank-multiplication and back-to-back adjacent read dependents. Perego + Amidi + JESD79‑2 is a viable alternative route.

Two caveats worth stating plainly:

1. I am relying on the record for the paragraph-level citations to Perego, JESD79‑2 and Ellsberry rather than on my own independent reading of those documents; if you need pinpoint cites for a filing, they should be verified against the exhibits.
2. The obviousness determination is on appeal. The Federal Circuit appeal has been briefed and consolidated but, per the last document I can see (May 2026 order), not decided — so the holding is not yet final as a matter of law, even though it is the current operative administrative determination.