US 11347657

Patent US11347657: Addressing Techniques for Write and Erase Operations in a Non-Volatile Storage Device

Title: Addressing techniques for write and erase operations in a non-volatile storage device

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: 2021-09-20

Issue Date: 2022-05-31

Abstract: This disclosure presents methods for hierarchical address virtualization within a memory controller and configurable block device allocation. By limiting address translation to specific hierarchical levels, a memory controller can be designed to offer predictable I/O latency with minimal logical-to-physical address translation time. One embodiment allows address translation to be implemented entirely with logic gates and lookup tables within a memory controller integrated circuit, eliminating the need for processor cycles. The virtualization scheme also provides flexibility in customizing virtual storage device configurations to present almost any desired configuration to a host or client.

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Plain-Language Overview of Independent Claims:

Independent Claim 1: This claim describes a method for a memory controller to manage a non-volatile memory system. The method involves receiving a logical memory address (LBA) and a block device identifier from a host. Using the block device identifier, the memory controller retrieves configuration details for a specific block device. This configuration includes an address space layout (ASL) for the logical memory address. The memory controller then uses this ASL to break down the LBA into several sub-addresses, each corresponding to a different hierarchical level of the physical memory (like channels, dies, erase units, and pages). At least one of these sub-addresses is a virtual address. The memory controller translates this virtual sub-address into a physical sub-address using a lookup table, while other sub-addresses might remain physical. Finally, these physical sub-addresses are used to perform the requested memory operation (read or write) on the non-volatile memory.

Independent Claim 10: This claim focuses on a memory controller apparatus designed to manage a non-volatile memory system with a hierarchical structure (channels, dies, erase units, pages). The apparatus includes a host interface, a flash interface, and a control logic unit. The control logic is configured to receive a logical memory address and a block device identifier from a host via the host interface. It then accesses block device configuration information based on the identifier, which includes an address space layout for the logical memory address. The control logic uses this ASL to extract multiple sub-addresses from the logical memory address, each corresponding to a different hierarchical level of the memory system. For at least one of these sub-addresses, which is a virtual address, the control logic performs a translation to obtain a physical address. The memory operation is then executed on the non-volatile memory using the resulting physical addresses via the flash interface.

Independent Claim 16: This claim describes a non-transitory computer-readable medium storing instructions that, when executed by a processing entity within a memory controller, perform a method. The method involves configuring a non-volatile memory system to present a pseudo-physical geometry to a host, where this geometry includes a configurable quantity of structural elements (channels, dies, erase units, pages). The instructions then enable the memory controller to receive a logical memory address (LBA) from the host that aligns with this pseudo-physical geometry. The LBA includes at least one virtual address field for a specific hierarchical level of structural elements. The memory controller uses this virtual address field to map the LBA to a physical storage location, potentially skipping defective or reserved elements transparently to the host, thereby maintaining the perceived pseudo-physical geometry.

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CAFC 2026 Dockets:

A search of CAFC 2026 dockets for patent number 11347657 did not return any direct results, meaning there are no publicly available records of litigation involving this specific patent in the Court of Appeals for the Federal Circuit for the year 2026 as of the current date. However, it is important to note that the Google Patents record for US11347657B1 indicates active litigation, specifically mentioning a PTAB case IPR2025-01378 filed (Settlement) and a US case filed in Texas Eastern District Court (2:24-cv-01073). These are not CAFC cases, and the CAFC search was specific to 2026 dockets. Therefore, while there is active litigation, it is not currently reflected in the CAFC 2026 dockets.## Patent US11347657: Addressing Techniques for Write and Erase Operations in a Non-Volatile Storage Device

Title: Addressing techniques for write and erase operations in a non-volatile storage device

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: 2021-09-20

Issue Date: 2022-05-31

Abstract: This disclosure provides techniques for hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

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Plain-Language Overview of Independent Claims:

Independent Claim 1: This claim describes a method for a memory controller to handle memory operations in a non-volatile storage device. The method involves receiving a logical memory address (LBA) and an identifier for a "block device" from a host system. The memory controller then uses this block device identifier to retrieve specific configuration details, including how the logical address space is laid out (Address Space Layout or ASL). This ASL guides the memory controller in breaking down the LBA into several smaller "sub-addresses," each pointing to a different level in the physical memory's hierarchy (such as specific channels, dies, erase units, and pages). At least one of these sub-addresses is treated as a "virtual" address and is translated into its corresponding "physical" address using a lookup table. The other sub-addresses may already be physical. Finally, the memory controller uses these combined physical addresses to perform the requested read or write operation on the non-volatile memory.

Independent Claim 10: This claim describes a memory controller apparatus designed to manage a non-volatile memory system that has a hierarchical structure (e.g., channels, dies, erase units, pages). The apparatus includes a host interface for communicating with a host system and a flash interface for communicating with the memory. A crucial component is the control logic, which is configured to receive a logical memory address and a block device identifier from the host via the host interface. The control logic then consults stored block device configuration information, which includes an address space layout (ASL) that dictates how the logical address maps to the physical memory. Using this ASL, the control logic extracts multiple sub-addresses from the logical memory address, each corresponding to a specific hierarchical level within the memory. For any sub-address identified as a virtual address, the control logic translates it into a physical address. Subsequently, the memory controller uses these resolved physical addresses to perform the requested memory operation through the flash interface.

Independent Claim 16: This claim outlines a non-transitory computer-readable medium (like firmware or software) that stores instructions. When these instructions are executed by a processor within a memory controller, they enable a method for managing a non-volatile memory system. The method begins by configuring the memory system to present an "idealized" or "pseudo-physical" view of its structure to a host system. This view includes a definable number of structural elements at various hierarchical levels (e.g., channels, dies, erase units, pages). The memory controller then receives a logical memory address (LBA) from the host, which is designed to be compatible with this pseudo-physical view. This LBA contains at least one virtual address field that corresponds to a particular hierarchical level of memory elements. The memory controller uses this virtual address field to translate the LBA to an actual physical storage location. Importantly, this translation process can transparently bypass any faulty or reserved physical memory elements, ensuring that the host continues to perceive a defect-free and consistent pseudo-physical memory structure.

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CAFC 2026 Dockets:

A search of the CAFC 2026 dockets for patent number 11347657 did not yield any direct results as of April 26, 2026. This indicates no publicly recorded litigation specifically pertaining to this patent in the Court of Appeals for the Federal Circuit for the year 2026. However, it is noted from the Google Patents record that US11347657B1 is involved in active litigation, including PTAB case IPR2025-01378 (which has reached a settlement) and a US District Court case filed in the Eastern District of Texas (case number 2:24-cv-01073). These are not CAFC cases, and thus would not appear in a CAFC docket search.