US 11347657

Patent US11347657: Addressing Techniques for Write and Erase Operations in a Non-Volatile Storage Device

Title: Addressing techniques for write and erase operations in a non-volatile storage device

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: 2021-09-20

Issue Date: 2022-05-31

Abstract: This disclosure presents methods for hierarchical address virtualization within a memory controller and configurable block device allocation. By limiting address translation to specific hierarchical levels, a memory controller can be designed to offer predictable I/O latency with minimal logical-to-physical address translation time. One embodiment allows address translation to be implemented entirely with logic gates and lookup tables within a memory controller integrated circuit, eliminating the need for processor cycles. The virtualization scheme also provides flexibility in customizing virtual storage device configurations to present almost any desired configuration to a host or client.

Plain-Language Overview of Independent Claims:

Independent Claim 1: This claim describes a method for a memory controller to manage a non-volatile memory system. The method involves receiving a logical memory address (LBA) and a block device identifier from a host. Using the block device identifier, the memory controller retrieves configuration details for a specific block device. This configuration includes an address space layout (ASL) for the logical memory address. The memory controller then uses this ASL to break down the LBA into several sub-addresses, each corresponding to a different hierarchical level of the physical memory (like channels, dies, erase units, and pages). At least one of these sub-addresses is a virtual address. The memory controller translates this virtual sub-address into a physical sub-address using a lookup table, while other sub-addresses might remain physical. Finally, these physical sub-addresses are used to perform the requested memory operation (read or write) on the non-volatile memory.

Independent Claim 10: This claim focuses on a memory controller apparatus designed to manage a non-volatile memory system with a hierarchical structure (channels, dies, erase units, pages). The apparatus includes a host interface, a flash interface, and a control logic unit. The control logic is configured to receive a logical memory address and a block device identifier from a host via the host interface. It then accesses block device configuration information based on the identifier, which includes an address space layout for the logical memory address. The control logic uses this ASL to extract multiple sub-addresses from the logical memory address, each corresponding to a different hierarchical level of the memory system. For at least one of these sub-addresses, which is a virtual address, the control logic performs a translation to obtain a physical address. The memory operation is then executed on the non-volatile memory using the resulting physical addresses via the flash interface.

Independent Claim 16: This claim describes a non-transitory computer-readable medium storing instructions that, when executed by a processing entity within a memory controller, perform a method. The method involves configuring a non-volatile memory system to present a pseudo-physical geometry to a host, where this geometry includes a configurable quantity of structural elements (channels, dies, erase units, pages). The instructions then enable the memory controller to receive a logical memory address (LBA) from the host that aligns with this pseudo-physical geometry. The LBA includes at least one virtual address field for a specific hierarchical level of structural elements. The memory controller uses this virtual address field to map the LBA to a physical storage location, potentially skipping defective or reserved elements transparently to the host, thereby maintaining the perceived pseudo-physical geometry.

CAFC 2026 Dockets:

A search of CAFC 2026 dockets for patent number 11347657 did not return any direct results, meaning there are no publicly available records of litigation involving this specific patent in the Court of Appeals for the Federal Circuit for the year 2026 as of the current date. However, it is important to note that the Google Patents record for US11347657B1 indicates active litigation, specifically mentioning a PTAB case IPR2025-01378 filed (Settlement) and a US case filed in Texas Eastern District Court (2:24-cv-01073). These are not CAFC cases, and the CAFC search was specific to 2026 dockets. Therefore, while there is active litigation, it is not currently reflected in the CAFC 2026 dockets.## Patent US11347657: Addressing Techniques for Write and Erase Operations in a Non-Volatile Storage Device

Title: Addressing techniques for write and erase operations in a non-volatile storage device

Assignee: Radian Memory Systems LLC

Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin

Filing Date: 2021-09-20

Issue Date: 2022-05-31

Abstract: This disclosure provides techniques for hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Plain-Language Overview of Independent Claims:

Independent Claim 1: This claim describes a method for a memory controller to handle memory operations in a non-volatile storage device. The method involves receiving a logical memory address (LBA) and an identifier for a "block device" from a host system. The memory controller then uses this block device identifier to retrieve specific configuration details, including how the logical address space is laid out (Address Space Layout or ASL). This ASL guides the memory controller in breaking down the LBA into several smaller "sub-addresses," each pointing to a different level in the physical memory's hierarchy (such as specific channels, dies, erase units, and pages). At least one of these sub-addresses is treated as a "virtual" address and is translated into its corresponding "physical" address using a lookup table. The other sub-addresses may already be physical. Finally, the memory controller uses these combined physical addresses to perform the requested read or write operation on the non-volatile memory.

Independent Claim 10: This claim describes a memory controller apparatus designed to manage a non-volatile memory system that has a hierarchical structure (e.g., channels, dies, erase units, pages). The apparatus includes a host interface for communicating with a host system and a flash interface for communicating with the memory. A crucial component is the control logic, which is configured to receive a logical memory address and a block device identifier from the host via the host interface. The control logic then consults stored block device configuration information, which includes an address space layout (ASL) that dictates how the logical address maps to the physical memory. Using this ASL, the control logic extracts multiple sub-addresses from the logical memory address, each corresponding to a specific hierarchical level within the memory. For any sub-address identified as a virtual address, the control logic translates it into a physical address. Subsequently, the memory controller uses these resolved physical addresses to perform the requested memory operation through the flash interface.

Independent Claim 16: This claim outlines a non-transitory computer-readable medium (like firmware or software) that stores instructions. When these instructions are executed by a processor within a memory controller, they enable a method for managing a non-volatile memory system. The method begins by configuring the memory system to present an "idealized" or "pseudo-physical" view of its structure to a host system. This view includes a definable number of structural elements at various hierarchical levels (e.g., channels, dies, erase units, pages). The memory controller then receives a logical memory address (LBA) from the host, which is designed to be compatible with this pseudo-physical view. This LBA contains at least one virtual address field that corresponds to a particular hierarchical level of memory elements. The memory controller uses this virtual address field to translate the LBA to an actual physical storage location. Importantly, this translation process can transparently bypass any faulty or reserved physical memory elements, ensuring that the host continues to perceive a defect-free and consistent pseudo-physical memory structure.

CAFC 2026 Dockets:

A search of the CAFC 2026 dockets for patent number 11347657 did not yield any direct results as of April 26, 2026. This indicates no publicly recorded litigation specifically pertaining to this patent in the Court of Appeals for the Federal Circuit for the year 2026. However, it is noted from the Google Patents record that US11347657B1 is involved in active litigation, including PTAB case IPR2025-01378 (which has reached a settlement) and a US District Court case filed in the Eastern District of Texas (case number 2:24-cv-01073). These are not CAFC cases, and thus would not appear in a CAFC docket search.

Unfortunately, I cannot directly access PACER or CAFC databases to search for litigation, as these often require specific login credentials and structured queries that are beyond my current capabilities.

However, based on the information provided in the patent document US11347657B1 itself, which was fetched on 2026-05-14, there is information regarding litigation:

Known Litigation Involving US Patent 11347657:

1. PTAB Case IPR2025-01378

   • Outcome/Current Status: Settlement
   • Petitioner: "Unified Patents PTAB Data" (Unified Patents)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01378
   • Filing Date: Not explicitly stated, but the case number implies a filing in 2025.

2. US Case filed in Texas Eastern District Court

   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:24-cv-01073
   • Source: District Court
   • Outcome/Current Status: Litigation (active)
   • Plaintiff(s) and Defendant(s): Not specified in the provided text.
   • Filing Date: Not explicitly stated, but the case number implies a filing in 2024.

3. First worldwide family litigation filed

   • Outcome/Current Status: Litigation (active)
   • Jurisdiction: Not specified, but indicates "First worldwide family litigation".
   • Case Number: Not specified.
   • Plaintiff(s) and Defendant(s): Not specified.
   • Filing Date: Not specified.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 11347657. This proceeding, IPR2025-01378, was terminated due to a settlement between the parties before a final written decision was issued. This gives a defendant facing assertion of this patent a neutral defensive posture as no claims were invalidated or sustained by the PTAB.

IPR2025-01378 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Radian Memory Systems LLC

• Type: Inter Partes Review
• Filed: 2025-08-05
• Status: Terminated-Settled. The proceeding concluded without a final decision on the merits due to a settlement agreement between the petitioner and the patent owner.
• Judge panel: Information regarding the specific judge panel for this IPR is not publicly available on general search platforms for terminated-settled cases without deep docket access, and the provided prompt context does not include it.
• Petition grounds: Details regarding the specific claims challenged, prior art cited, and statutory bases (§ 102 / § 103 / § 112) of the petition are not readily available in public summaries for settled cases without accessing the petition itself.
• Institution decision: The status "Terminated-Settled" on 2026-01-09, following a filing date of 2025-08-05, indicates that the proceeding likely settled before the institution decision deadline (typically 3 months from the patent owner's preliminary response or 6 months from petition filing). Therefore, an institution decision was likely not issued.
• Final Written Decision: Not issued, as the proceeding was terminated due to settlement.
• Settlement / termination: The proceeding was terminated on 2026-01-09 due to settlement. The specific terms of the settlement are typically confidential between the parties involved.
• Appeal: No appeal was filed, as there was no Final Written Decision to appeal.
• Defensive value: This IPR does not impact the patentability of the claims of US11347657, as it settled before any PTAB decision on the merits. Therefore, a defendant facing assertion of this patent cannot point to any claims having been invalidated by this particular IPR.

Strategic summary

As of today, May 21, 2026, all claims of US Patent 11347657 remain UNTESTED by the PTAB, as the sole IPR proceeding filed against it, IPR2025-01378, was terminated due to settlement. No claims were canceled, nor were any explicitly sustained as patentable by the PTAB. This means the patent's validity has not been evaluated by the PTAB.

Regarding the estoppel landscape, since IPR2025-01378 was terminated-settled before institution or a final written decision, there is no statutory estoppel under 35 U.S.C. § 315(e)(2) for the petitioner (Samsung Electronics Co., Ltd. et al.) or their privies. This implies that the prior-art grounds that could have been raised in IPR2025-01378 might still be available in district court litigation or for future PTAB challenges by different petitioners, assuming no contractual estoppel was part of the confidential settlement. Without knowing the specific grounds raised in the petition, it's impossible to identify precisely which prior-art arguments could have been raised.

There are no clear pattern signals of aggressive PTAB appeals by the patent owner or multiple IPRs from the same petitioner based on the single proceeding on record. The petitioner, Samsung Electronics Co., Ltd. et al., is a significant industry player, and their decision to settle might indicate either a perceived strength of the patent or a strategic business decision, the details of which are confidential. Unified Patents is listed in the Google Patents litigation section as involved in this IPR, suggesting a defensive aggregator may have initiated or funded the challenge, which is a common pattern in patent defense.

Recommended next steps

For a defendant considering challenging US11347657:

• Given the prior IPR was settled, the patent has not been subjected to PTAB scrutiny. A new IPR petition could be a viable defense strategy if strong prior art exists.
• The absence of an institution decision means the PTAB has not yet formally reviewed the merits of any invalidity arguments.
• Consider a thorough prior art search to identify new grounds or re-evaluate the grounds that may have been present in the settled IPR. This will inform the strength of a potential new IPR petition.
• It would be beneficial to review the public records of IPR2025-01378 on the USPTO PTAB E2E system if possible, to understand the petition and the scope of claims challenged, even though no decision was rendered.
• If a demand letter or complaint cites claims of US11347657, understand that these claims have not been legally tested at the PTAB. The lack of prior invalidation means a defendant would bear the burden of proof in challenging the patent.

The PTAB's case information for IPR2025-01378 can be accessed here: https://portal.unifiedpatents.com/ptab/case/IPR2025-01378.

Inventors

The named inventors for US Patent 11347657 are:

• Robert Lercari
• Alan Chen
• Mike Jadon
• Craig Robertson
• Andrey V. Kuzmin

At the time of filing, these inventors appear to have assigned their interest to Radian Memory Systems, LLC, as indicated by the assignment recorded on 2021-09-20 (executed) / recorded 2021-09-20, where the inventors are listed as assignors to Radian Memory Systems, LLC. It is a common pattern for inventors to assign their patent rights to their employer at the time of invention.

Original assignee

The entity named as the original assignee on the issued patent US11347657 is Radian Memory Systems LLC.

Radian Memory Systems LLC's primary line of business is developing and providing composable memory solutions, including intelligent NVMe Flash drives and software-defined memory products for data centers. They appear to ship products embodying the claims, specifically their "Radian Memory Drives" and "Radian software-defined memory" solutions, which relate to memory management and addressing techniques in non-volatile storage.

As of the current date (2026-05-21), Radian Memory Systems LLC appears to be an active, operating company.

Assignment timeline

The following is a chronological list of every recorded assignment for US Patent 11347657:

• 2021-09-20 (executed) / recorded 2021-09-20 — Reel 057053/0002
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: CHEN, ALAN; JADON, MIKE; KUZMIN, ANDREY V.; LERCARI, ROBERT; ROBERTSON, CRAIG
  • Assignee: Radian Memory Systems, LLC
  • Correspondent: LAW OFFICE OF ROBERT LERCARIA, 15127 SKYVIEW WAY, SAN JOSE, CALIFORNIA 95139
  • Context: Transfer of inventor's interest to the original assignee.
• 2021-09-20 (executed) / recorded 2021-09-20 — Reel 057053/0003
  • Conveyance: CHANGE OF NAME
  • Assignor: Radian Memory Systems, LLC
  • Assignee: Radian Memory Systems, Inc.
  • Correspondent: LAW OFFICE OF ROBERT LERCARIA, 15127 SKYVIEW WAY, SAN JOSE, CALIFORNIA 95139. This correspondent recurs in this chain.
  • Context: Internal corporate reorganization/change of name from LLC to Inc.
• 2024-05-20 (executed) / recorded 2024-05-20 — Reel 063674/0971
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: Radian Memory Systems, Inc.
  • Assignee: RADIAN MEMORY SYSTEMS LLC
  • Correspondent: LAW OFFICE OF ROBERT LERCARIA, 15127 SKYVIEW WAY, SAN JOSE, CALIFORNIA 95139. This correspondent recurs in this chain.
  • Context: Internal corporate reorganization/change of name from Inc. back to LLC.

Timeline diagram

timeline
    title Ownership of US 11347657
    2014 : Priority date
    2021 : Inventors assign to Radian Memory Systems LLC
         : Radian Memory Systems LLC changes to Inc
    2022 : Patent issued
    2024 : Radian Memory Systems Inc assigns to Radian Memory Systems LLC

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The transfers observed are between different legal forms of the same operating company, Radian Memory Systems. There is no indication of a transfer to a licensing-only LLC.
2. Known asserter in the chain — Not present. Radian Memory Systems LLC is not on the provided list of known NPEs or commonly identified as such by RPX or Unified Patents in my training data.
3. Repeat correspondent across the chain — Present. The correspondent "LAW OFFICE OF ROBERT LERCARIA, 15127 SKYVIEW WAY, SAN JOSE, CALIFORNIA 95139" appears for all three recorded assignments: Reel 057053/0002, Reel 057053/0003, and Reel 063674/0971. This indicates consistency in legal representation for Radian Memory Systems.
4. Cascading transfers — Not present. While there are two assignments on the same day in 2021, they represent an initial inventor assignment and an immediate corporate name change, not a series of transfers through different entities. The subsequent transfer in 2024 is also a corporate name change.
5. Pre-litigation transfer — Unclear. The litigation filed in Texas Eastern District Court (2:24-cv-01073) began in 2024. The most recent assignment (Radian Memory Systems, Inc. to RADIAN MEMORY SYSTEMS LLC) was executed and recorded on 2024-05-20 (Reel 063674/0971). Without a precise filing date for the Texas case, it's unclear if this assignment falls within 6 months prior to the suit. The patent itself does not provide the exact filing date of the Texas lawsuit, only that it was filed in 2024.
6. Bankruptcy fire-sale — Not present. There is no information to suggest Radian Memory Systems underwent bankruptcy proceedings.
7. Privateering — Not present. No evidence from the assignment records or the patent text suggests privateering.
8. Defensive aggregator (anti-NPE) — Not present. The current assignee is Radian Memory Systems LLC, an operating company, not a defensive aggregator.

Verdict

Operating-company assertion
The assignment chain primarily reflects internal corporate reorganizations (name changes between LLC and Inc. forms of Radian Memory Systems) as evidenced by Reel 057053/0003 and Reel 063674/0971. The initial assignment on Reel 057053/0002 is from the inventors to Radian Memory Systems, LLC, which is typical for an operating company. While there is ongoing litigation, the patent remains with the operating company, Radian Memory Systems LLC.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

Radian Memory Systems. Products - Radian Memory Systems. https://www.radianmemory.com/products/
Radian Memory Systems. Home - Radian Memory Systems. https://www.radianmemory.com/
US11347657B1. US11347657B1 - Addressing techniques for write and erase operations in a non-volatile storage device. Google Patents. https://patents.google.com/patent/US11347657/en

To identify the most relevant prior art for US patent 11347657, I will examine the "Cited by" section of the patent on the USPTO website. This section lists the patents and publications that the examiner considered during prosecution, as well as those cited by the applicant. Since I cannot directly access the USPTO database with specific queries at this moment, I will rely on the provided patent text which lists prior art keywords and priority claims.

The patent document US11347657B1 itself cites several documents as having priority or being incorporated by reference. These often represent critical prior art that the patent builds upon or distinguishes itself from.

Here's an analysis of the prior art mentioned within the patent document US11347657B1:

Priority/Incorporation by Reference Documents:

1. U.S. Utility patent application Ser. No. 16/808,304

   • Full Citation: U.S. Utility patent application Ser. No. 16/808,304, filed on Mar. 3, 2020, on behalf of first-named inventor Robert Lercari for “Nonvolatile memory controller supporting variable configurability and forward compatibility.”
   • Publication/Filing Date: March 3, 2020
   • Brief Description: This is a continuation of the application that led to US11347657, focusing on nonvolatile memory controllers supporting variable configurability and forward compatibility. As a direct lineage, it establishes the groundwork for the inventive concepts in US11347657, particularly around memory controller capabilities and addressing schemes.
   • Potential Anticipation (35 U.S.C. § 102): Since US11347657 is a continuation of this application, this document itself would not anticipate US11347657, as it shares the same inventive entity and effectively the same subject matter for priority purposes. It would serve as foundational disclosure rather than anticipatory prior art.

2. U.S. Utility patent application Ser. No. 15/690,006 (U.S. patent Ser. No. 10/642,748)

   • Full Citation: U.S. Utility patent application Ser. No. 15/690,006, filed on Aug. 29, 2017, on behalf of first-named inventor Robert Lercari for “Memory Controller with multimodal control over memory dies” (issued on May 5, 2020, as U.S. patent Ser. No. 10/642,748).
   • Publication/Filing Date: August 29, 2017 (filed); May 5, 2020 (issued)
   • Brief Description: This patent describes a memory controller with multimodal control over memory dies, which is a core concept in US11347657 regarding different operating modes (physical access, linearly virtualized, cooperative management, hierarchically virtualized).
   • Potential Anticipation (35 U.S.C. § 102): Similar to the above, this patent is part of the priority chain. The disclosed concepts of multi-modal control, exposing physical or pseudo-physical geometry, and hierarchical virtualization are fundamental to US11347657. Any claims in US11347657 that merely reiterate what is fully disclosed in this earlier patent without a novel distinction could potentially be anticipated. For example, the high-level description of a memory controller having multiple operating modes, including a hierarchically virtualized mode, could be anticipated if not further refined or combined with other elements in US11347657's claims.

3. U.S. Utility patent application Ser. No. 15/074,778 (U.S. Pat. No. 9,785,572)

   • Full Citation: U.S. Utility patent application Ser. No. 15/074,778, filed on Mar. 18, 2016, on behalf of first-named inventor Robert Lercari for “Expositive Flash Memory Control” (issued on Oct. 10, 2017, as U.S. Pat. No. 9,785,572).
   • Publication/Filing Date: March 18, 2016 (filed); October 10, 2017 (issued)
   • Brief Description: This patent introduces "Expositive Flash Memory Control," which is a foundational concept for the pseudo-expositive and hierarchically virtualized modes in US11347657. It likely details the mechanisms for exposing flash geometry to the host and managing it.
   • Potential Anticipation (35 U.S.C. § 102): As an earlier patent in the family, it could anticipate claims in US11347657 that are directly and identically disclosed in U.S. Pat. No. 9,785,572, especially those related to the fundamental aspects of expositive flash memory control and hierarchical address virtualization without additional distinguishing features.

4. U.S. Utility patent application Ser. No. 14/880,529 (U.S. Pat. No. 9,542,118)

   • Full Citation: U.S. Utility patent application Ser. No. 14/880,529, filed on Oct. 12, 2015, on behalf of first-named inventor Robert Lercari for “Expositive Flash Memory Control” (issued on Jan. 10, 2017, as U.S. Pat. No. 9,542,118).
   • Publication/Filing Date: October 12, 2015 (filed); January 10, 2017 (issued)
   • Brief Description: This is also titled "Expositive Flash Memory Control" and is a predecessor to U.S. Pat. No. 9,785,572. It would lay further groundwork for the concepts of exposing flash geometry and hierarchical virtualization.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the other family members, any claims in US11347657 that are identically disclosed in U.S. Pat. No. 9,542,118 without further novel elements or arrangements could be anticipated. This would include core concepts of dividing an incoming memory address into discrete address fields corresponding to hierarchical groups of structural elements and using at least one virtual address field.

5. U.S. Provisional Patent Application No. 62/199,969

   • Full Citation: U.S. Provisional Patent Application No. 62/199,969, filed on Jul. 31, 2015, on behalf of first-named inventor Robert Lercari for “Expositive Flash Memory Control.”
   • Publication/Filing Date: July 31, 2015
   • Brief Description: A provisional application for "Expositive Flash Memory Control," providing an early disclosure of the concepts.
   • Potential Anticipation (35 U.S.C. § 102): Provisional applications establish an early filing date for the subject matter they disclose. If any claims in US11347657 are fully and identically disclosed in this provisional application, they would be covered by its priority date and thus not anticipated by it. However, if another reference predates this provisional application and discloses the same subject matter, that other reference could be anticipatory.

6. U.S. Provisional Patent Application No. 62/194,172

   • Full Citation: U.S. Provisional Patent Application No. 62/194,172, filed on Jul. 17, 2015, on behalf of first-named inventor Robert Lercari for “Techniques for Memory Controller Configuration.”
   • Publication/Filing Date: July 17, 2015
   • Brief Description: This provisional application focuses on techniques for memory controller configuration, which is relevant to how block devices are defined and allocated in US11347657.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the above provisional, it sets an early priority date. Claims in US11347657 related to configurable block device allocation and memory controller configuration, if fully disclosed here, would be protected by this priority date against later art.

7. U.S. Provisional Patent Application No. 62/063,357

   • Full Citation: U.S. Provisional Patent Application No. 62/063,357, filed on Oct. 13, 2014, on behalf of first-named inventor Robert Lercari for “Techniques for Memory Controller Configuration.”
   • Publication/Filing Date: October 13, 2014
   • Brief Description: Another provisional application relating to memory controller configuration techniques.
   • Potential Anticipation (35 U.S.C. § 102): Establishes an even earlier priority date for memory controller configuration aspects.

8. U.S. Utility patent application Ser. No. 14/848,273

   • Full Citation: U.S. Utility patent application Ser. No. 14/848,273, filed on Sep. 8, 2015, on behalf of first-named inventor Andrey V. Kuzmin for “Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation.”
   • Publication/Filing Date: September 8, 2015
   • Brief Description: This patent focuses on data migration techniques based on per-data metrics and memory degradation, a specific maintenance operation that can be managed by the memory controller described in US11347657.
   • Potential Anticipation (35 U.S.C. § 102): Claims in US11347657 that cover the specific data migration techniques detailed in this application, if fully disclosed here and not further distinguished, could be anticipated.

9. U.S. Provisional Patent Application No. 62/048,162

   • Full Citation: U.S. Provisional Patent Application No. 62/048,162, filed on Sep. 9, 2014, on behalf of first-named inventor Andrey V. Kuzmin for “Techniques for Data Migration Based On Per-Data Metrics and Memory Degradation.”
   • Publication/Filing Date: September 9, 2014
   • Brief Description: A provisional application for data migration techniques.
   • Potential Anticipation (35 U.S.C. § 102): Establishes priority for the data migration aspects described above.

10. U.S. Patent Publication 2014/0215129

    • Full Citation: U.S. Patent Publication 2014/0215129, for “Cooperative Flash Memory Control.”
    • Publication/Filing Date: Not explicitly stated, but the publication number indicates 2014.
    • Brief Description: This publication relates to "Cooperative Flash Memory Control," which is one of the operating modes (mode 116) discussed in US11347657. It involves the host receiving physical geometry and defining address assignments, with the memory controller assisting with statistics and maintenance notifications.
    • Potential Anticipation (35 U.S.C. § 102): Claims in US11347657 directed specifically to the "cooperative management mode" as described in Publication 2014/0215129, without further novel features, could be anticipated.

11. U.S. Utility patent application Ser. No. 14/047,193

    • Full Citation: U.S. Utility patent application Ser. No. 14/047,193, filed on Oct. 7, 2013, on behalf of first-named inventor Andrey V. Kuzmin for “Multi-Array Operation Support And Related Devices, Systems And Software.”
    • Publication/Filing Date: October 7, 2013
    • Brief Description: This application covers multi-array operation support, which is relevant to flash memory devices with multiple channels and dies.
    • Potential Anticipation (35 U.S.C. § 102): Any claims in US11347657 that describe basic multi-array operation in a flash memory system, if fully disclosed in this earlier application, could be anticipated.

General Note on Anticipation (35 U.S.C. § 102):

For a claim to be anticipated under 35 U.S.C. § 102, a single prior art reference must disclose every element of the claimed invention, either expressly or inherently, and the elements must be arranged as required by the claim. The disclosure must be identical to the claimed invention. Since many of the above listed references are part of the same patent family or are incorporated by reference, they establish the priority date for the claimed subject matter. Therefore, they would generally not anticipate the claims of US11347657 if those claims are adequately supported by the earlier filing dates of these documents. However, if any claims in US11347657 introduce new subject matter not explicitly or inherently disclosed in these earlier applications/patents, then other prior art that predates US11347657's effective filing date (and the priority dates of any new subject matter) could potentially anticipate those new claims. The above analysis focuses on how these cited documents relate to the present patent, rather than identifying external prior art.

To perform a thorough prior art analysis under 35 U.S.C. § 102, a patent examiner would typically conduct a comprehensive search of various public information sources, including other patents, publications, products, and public knowledge. The USPTO provides tools for searching its patent database.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 11347657

This analysis assesses the obviousness of US Patent 11347657's independent claims (Claims 1, 10, and 16) in light of prior art, specifically focusing on US Patent 9,542,118 (Lercari et al.), which is a direct parent patent in the same family and explicitly referenced within the disclosure of US11347657. The earliest priority date for US11347657 is 2014-09-09. US Patent 9,542,118 was issued on January 10, 2017, from an application filed on October 12, 2015, and claims benefit of a provisional application filed on September 9, 2014 (U.S. Provisional Patent Application No. 62/048,162), which shares the earliest priority date with US11347657. Therefore, the teachings of US 9,542,118, particularly those derivable from its earliest priority date, are highly relevant prior art.

A person having ordinary skill in the art (PHOSITA) in the field of non-volatile memory systems would have been motivated to combine the teachings of the identified prior art to arrive at the claimed invention, particularly given the explicit overlap in objectives related to improving flash memory performance, predictability, and management.

Combination of Prior Art: US Patent 9,542,118 (Lercari et al.)

US Patent 9,542,118, titled "Expositive Flash Memory Control," discloses a substantial portion of the subject matter claimed in US11347657. The abstract of US 9,542,118 provides a comprehensive overview that closely aligns with the independent claims of US11347657.

Obviousness of Independent Claim 1 (Method for Memory Controller):

Claim 1 describes a method for a memory controller to manage a non-volatile memory system, involving:

1. Receiving a logical memory address (LBA) and a block device identifier from a host.
2. Retrieving block device configuration information, including an address space layout (ASL).
3. Subdividing the LBA into hierarchical sub-addresses, with at least one being a virtual address.
4. Translating the virtual address into a physical address using a lookup table.
5. Performing a memory operation using the physical addresses.

US 9,542,118 explicitly teaches a "memory controller that subdivides an incoming memory address into multiple discrete address fields corresponding to respective hierarchical groups of structural elements... and in which at least one of the discrete address fields constitutes a virtual address for the corresponding physical element within the structural hierarchy." This directly covers the subdivision of LBAs into hierarchical sub-addresses with at least one virtual address.

Furthermore, US 9,542,118 also discloses that "the net storage volume of a nonvolatile semiconductor memory system is subdivided into discrete performance-isolated storage regions... each such storage region being mapped by an independent linear range of logical addresses." These regions "may be presented to one or more host access requestors as an independent block device... each having its own performance characteristics and address space." The patent further states that "the mapping of the logical address space within a given block device, referred to herein as 'address space layout,' may vary from one block device to another... to yield configurable and varied block device characteristics in terms of endurance and I/O bandwidth." This disclosure clearly describes the use of block devices, their associated configuration (including ASL), and the use of identifiers to manage them.

Regarding the translation of virtual addresses, US 9,542,118 states that this "hierarchical subdivision" allows the virtual address "to be freely mapped to any of the constituent physical elements of that larger structure." It also highlights that "this architecture provides for greatly simplified address translation (e.g., which can optionally be implemented entirely in hardware), and facilitates configurable and predictable I/O latency." While "lookup table" is not explicitly in the abstract of 9,542,118, implementing such hardware-based address translation for virtual-to-physical mapping would be a conventional and obvious choice for a PHOSITA in designing high-performance memory controllers once the concept of hierarchical virtualization is established.

Motivation to Combine/Modify: A PHOSITA, seeking to implement a memory controller with the benefits of hierarchical virtualization and configurable block devices as taught by US 9,542,118, would find it obvious to use common data structures like lookup tables in hardware to perform the necessary address translations efficiently, especially for "greatly simplified" and "predictable I/O latency" operations. The explicit mention of hardware implementation in US 9,542,118 provides direct motivation for this design choice.

Obviousness of Independent Claim 10 (Memory Controller Apparatus):

Claim 10 describes a memory controller apparatus with a host interface, a flash interface, and control logic configured to perform steps analogous to Claim 1.

The apparatus claim follows directly from the method claim. The abstract of US 9,542,118 comprehensively describes the functional capabilities of such a memory controller, including its interaction with a host (receiving LBAs) and its management of non-volatile memory (performing operations on physical elements). The concept of a memory controller having control logic to execute these functions is fundamental. US11347657 also discusses its implementation as a "memory controller integrated circuit (IC)" featuring "hardware translation circuitry" and "lookup tables" (FIG. 14 description). Since US 9,542,118 is a parent patent, these implementation details are highly likely to be disclosed or obvious from its full specification.

Motivation to Combine/Modify: A PHOSITA designing a memory controller based on the principles of US 9,542,118 would find it obvious to incorporate the necessary control logic and hardware components (like interfaces and translation circuitry, including lookup tables) to achieve the described hierarchical address virtualization and block device management. These are standard architectural elements for a memory controller designed to achieve the performance goals articulated in US 9,542,118.

Obviousness of Independent Claim 16 (Non-Transitory Computer-Readable Medium):

Claim 16 describes a non-transitory computer-readable medium storing instructions that, when executed, perform a method comprising:

1. Configuring a non-volatile memory system to present a pseudo-physical geometry to a host.
2. Receiving an LBA from the host aligning with the pseudo-physical geometry, the LBA including at least one virtual address field.
3. Mapping the LBA to a physical storage location by translating the virtual address field to a physical address, thereby transparently skipping a defective or reserved physical element and maintaining the pseudo-physical geometry.

US 9,542,118 explicitly describes presenting an "idealized or pseudo-physical description of the underlying geometry" to the host. It also states that the memory controller maintains this "static idealized perspective" by "holding in reserve some number of erase units (or dies or any other resource likely to fail over time)." This directly teaches the concept of configuring a pseudo-physical geometry with configurable quantities of structural elements.

Furthermore, US 9,542,118 teaches that the memory controller is "free, by virtue of one or more virtualized address fields within the incoming logical addresses, to virtualize localized groups of physical structures and thus mask defective structural elements and swap operational structural elements into and out of service, for example, as they wear or otherwise require maintenance." This directly covers receiving an LBA with a virtual address field and mapping it to a physical location while transparently skipping defective or reserved elements, thereby maintaining the pseudo-physical geometry.

Motivation to Combine/Modify: A PHOSITA developing firmware or software for a memory controller based on US 9,542,118 would find it obvious to program instructions to implement the disclosed methods of configuring pseudo-physical geometry, processing LBAs with virtual address fields, and transparently managing defective or reserved physical elements. The ability to mask defects and maintain a consistent, idealized view for the host is a core benefit articulated in US 9,542,118, providing strong motivation for a PHOSITA to implement these features.

In conclusion, the independent claims of US Patent 11347657 would have been obvious to a person having ordinary skill in the art based on the teachings of US Patent 9,542,118 alone, which, as a direct parent patent, provides comprehensive disclosure of the key elements and their underlying principles. The advancements in US11347657 appear to be logical extensions or specific implementations of the broad concepts already laid out in US 9,542,118.

To provide a detailed analysis of US patent 11347657 regarding its term adjustments, extensions, related applications, and projected expiration date, I need to access the official USPTO patent records directly. While I cannot perform a live, interactive search of the USPTO database like Patent Center (which requires specific login credentials and structured queries beyond my current capabilities), I can interpret the information usually found in such records based on the details already available within the patent document and general patent law principles.

Based on the information available and general patent practice:

Patent Term Adjustments (PTA)

Patent Term Adjustments (PTA) compensate patent owners for delays caused by the USPTO during the patent examination process. This typically includes delays if the USPTO fails to issue a first office action within 14 months of filing, fails to respond to a reply or an appeal within four months, or fails to issue a patent within three years of the application filing date. The total PTA is calculated at the time of patent issuance and is added to the standard 20-year patent term.

To determine the exact PTA for US11347657, one would need to consult the "Issue Notification Letter" that was mailed to the applicant approximately three weeks prior to the patent's issuance (May 31, 2022). This letter details the PTA calculation, including any deductions for applicant delays. Without direct access to this document or the Patent Center details for 11347657, I cannot provide the precise PTA.

Patent Term Extensions (PTE)

Patent Term Extensions (PTE) are distinct from PTA and are granted under 35 U.S.C. § 156. They restore patent term lost due to delays in regulatory review for certain products, primarily human drugs, medical devices, food additives, and other specified products requiring premarket government approval.

There is no information within the provided patent text for US11347657 that indicates it claims a product subject to regulatory review that would qualify for a PTE. Therefore, it is highly unlikely that US11347657 has received or is eligible for a Patent Term Extension.

Continuation and Divisional Applications

The provided patent text explicitly states that US11347657 is a continuation of several earlier-filed applications:

• U.S. Utility patent application Ser. No. 16/808,304, filed on Mar. 3, 2020.
• U.S. Utility patent application Ser. No. 15/690,006, filed on Aug. 29, 2017 (issued as U.S. patent Ser. No. 10/642,748).
• U.S. Utility patent application Ser. No. 15/074,778, filed on Mar. 18, 2016 (issued as U.S. Pat. No. 9,785,572).
• U.S. Utility patent application Ser. No. 14/880,529, filed on Oct. 12, 2015 (issued as U.S. Pat. No. 9,542,118).
• U.S. Utility patent application Ser. No. 14/848,273, filed on Sep. 8, 2015.

These are all part of the patent's prosecution history, indicating a series of continuation applications. A "continuation application" is a second application for the same invention claimed in a prior nonprovisional application and filed while the prior application is still pending. A "divisional application" is a type of continuing application that claims subject matter disclosed in an earlier filed parent application but distinct from the claims of the parent application. The provided text indicates a chain of continuations, but does not explicitly mention divisional applications stemming from 11347657 itself.

Related Family Members

Based on the continuation chain provided, the following are direct related family members in the United States, sharing a common priority:

• US10642505B1 (issued May 5, 2020, from Ser. No. 15/690,006)
• US9785572B1 (issued Oct. 10, 2017, from Ser. No. 15/074,778)
• US9542118B1 (issued Jan. 10, 2017, from Ser. No. 14/880,529)

Additionally, several provisional applications contribute to the priority date:

• U.S. Provisional Patent Application No. 62/199,969, filed on Jul. 31, 2015.
• U.S. Provisional Patent Application No. 62/194,172, filed on Jul. 17, 2015.
• U.S. Provisional Patent Application No. 62/063,357, filed on Oct. 13, 2014.
• U.S. Provisional Patent Application No. 62/048,162, filed on Sep. 9, 2014.

These documents form the US patent family for the core inventive concepts. A "patent family" can refer to all patent documents in various countries related to a single invention, or more simply, all documents having at least one common priority.

Projected Expiration Date

For utility patents filed on or after June 8, 1995, the patent term generally extends 20 years from the earliest filing date of the application, or if it claims priority to an earlier application, 20 years from the filing date of the earliest such application.

US11347657 claims priority from U.S. Provisional Patent Application No. 62/048,162, which was filed on September 9, 2014. This is the earliest priority date established in the patent's lineage.

Therefore, the base expiration date (before any Patent Term Adjustment) for US11347657 is 20 years from September 9, 2014, which is September 9, 2034.

However, as mentioned in the "Patent Term Adjustments" section, any PTA granted would be added to this 20-year term. The Google Patents record for US11347657B1 explicitly states an "Anticipated expiration" date of 2035-09-08. This indicates that approximately one year of Patent Term Adjustment was likely granted. This adjustment would move the expiration from September 9, 2034, to September 8, 2035. This difference between the calculated 20-year term and the "Anticipated expiration" suggests a PTA of approximately one year.