Invalidity dossier
US 8301833
Non-volatile memory module
Current assignee: Micron Technology, Inc.
Added 8/28/2026, 12:48:13 PM
Active provider: DeepSeek · deepseek-v4-flash
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
I'll search for authoritative records on this patent number.
Let me pull the claim text and check the 2026 litigation dockets.
US 8,301,833 B1 — "Non-Volatile Memory Module"
Caution on scope of this report: I was able to retrieve the patent's front page (including the full bibliographic data and abstract) via the PTAB exhibit copy of the printed patent, the Google Patents record, and the briefing/decisions from the Micron IPR. I could not retrieve the actual numbered claim text (my fetched copy of the specification is truncated immediately before the claims), so my claim overview below is a reconstruction keyed to the "Summary of the Invention" paragraphs and to how the PTAB and the parties treated the claims — not a verbatim quotation of the claims. I flag the specific uncertainties at the end.
Bibliographic data (from the printed patent front page)
| Field | Value |
|---|---|
| Patent number | US 8,301,833 B1 |
| Title | Non-Volatile Memory Module |
| Inventors | Chi-She Chen (Walnut, CA); Jeffrey C. Solomon (Irvine, CA); Scott Milton (Irvine, CA); Jayesh Bhakta (Cerritos, CA) |
| Assignee | Netlist, Inc., Irvine, CA |
| Application no. | 12/240,916 |
| Filed | September 29, 2008 |
| Issued | October 30, 2012 |
| Priority | Continuation of App. No. 12/131,873 (filed Jun. 2, 2008, now abandoned), which claims benefit of Provisional App. No. 60/941,586 (filed Jun. 1, 2007) |
| Claims / drawings | 30 claims, 12 drawing sheets |
| Primary examiner | Midys Rojas |
| Attorney/agent | Nixon Peabody LLP (Khaled Shami) |
| Classification | G06F 12/00; US Cl. 711/104, 711/160–162, 710/10 |
| Term adjustment | Notice under 35 U.S.C. §154(b), 638 days |
| Google Patents | Prior art date 2007-06-01; adjusted expiration 2030-03-02; status Active |
| Assignment history | Security interest to SVIC No. 28 New Technology Business Investment L.L.P. (Nov. 20, 2015); released back to Netlist (Nov. 20, 2023) |
Source: https://patents.google.com/patent/US8301833/en ; printed-patent front page reproduced at https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/PGR2026-00001/Samsung_Electronics_Co._Ltd/11-07-2025-Petitioner/Exhibit-1089-EX1089___US8301833/
Abstract (as issued)
"Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system."
Plain-language overview of the claims
The 30 claims map onto seven distinct innovations described in the Summary section (each Summary paragraph corresponds to a claim family). Google Patents' "Definitions" extraction of the '833 record preserves these seven preamble phrases, which strongly suggests seven independent claims:
- "A memory system coupled to a computer system…" — The base apparatus claim. A memory system with (a) a volatile memory subsystem (e.g., DRAM), (b) a non-volatile memory subsystem (e.g., NAND flash), (c) a controller operatively coupled to the non-volatile subsystem, and (d) at least one circuit configured to selectively operatively decouple the controller from the volatile memory subsystem (i.e., an isolation switch / ODT circuit) so that the flash and controller do not load the DRAM bus while the host is talking to the DRAM.
- "A power module for providing a plurality of voltages to a memory system…" — An apparatus claim to the power module: an input supplying a third voltage; a voltage conversion element producing a second voltage; a first power element selectively supplying a fourth voltage to the conversion element; a second power element selectively supplying a fifth voltage to the conversion element; and the module configured to source the first voltage either from the conversion element or from the input. The module has three states (system power / pre-failure transition / secondary capacitor-backed power).
- "A method of providing a first voltage and a second voltage…" — The method counterpart to #2: during a first condition, take the first voltage from an input power supply and the second from a first power subsystem; detect a second condition and then take both voltages from the first power subsystem; charge a second power subsystem; detect a third condition and then take both voltages from the second power subsystem (the battery-free capacitor bank).
- "A method for controlling a memory system… operating the volatile memory subsystem at a first [clock] frequency when… data is communicated between the volatile memory subsystem and the host system… operating the non-volatile memory subsystem at a second frequency… [and] operating the volatile memory subsystem at a third frequency… less than the first frequency" — The "reduced-frequency backup/restore" method. In the PTAB's words, "Independent claim 15 recites, in part, 'the memory system is in a first mode of operation in which data is communicated between the volatile memory subsystem and the host system.'"
- "A method for controlling a memory system… transferring data words… storing a first portion of the data word in a buffer, storing a second portion of the data word in the buffer, and writing the entire data word from the buffer to the non-volatile memory subsystem" — The bit-wise "slicing" method: read one DRAM slice (e.g., 40 bits), place the other slice in self-refresh, then read the second slice (e.g., 32 bits), reassemble the full 72-bit word in a FIFO in the controller (FPGA), run ECC, and write the whole word to flash. The spare slice stays in self-refresh, saving power.
- "A memory system operatively coupled to a host system… a non-volatile memory subsystem comprising at least 100 percent more storage capacity than does the volatile memory subsystem… a controller… configured to allow data to be communicated between the volatile memory subsystem and the host system when the memory system is operating in a first state and… between the volatile memory subsystem and the non-volatile memory subsystem when… operating in a second state" — The oversized-flash apparatus claim (extra capacity enables a second backup before the first is erased).
- "A method of controlling a memory system… storing a first copy of data… restoring the first copy… erasing the first copy… storing a second copy of data… wherein storing the second copy begins before the first copy is completely erased" — The overlapping backup/erase double-buffer method.
What the PTAB record confirms about claim structure: In IPR2022-00418 the Board identified claim 1 and claim 15 as independent claims and treated claims 16 and 17 under separate headings (indicating they are independent or argued separately). Claims 2 and 18 were not challenged and therefore survived; claims 1, 3–17, and 19–30 were held unpatentable. The petition's pairing of dependent claims (3 & 19, 4 & 20, 5 & 21, … 14 & 30) shows two parallel dependent-claim tracks.
Litigation and post-grant history touching this exact patent
- IPR2014-01370, IPR2014-00994, IPR2017-00649 — each listed on the Google Patents family-litigation panel as "Not Instituted – Merits." (Note: Google Patents aggregates family litigation; I cannot confirm from the retrieved record that each of these named 8,301,833 itself.)
- IPR2022-00418 (Micron Technology, Inc. et al. v. Netlist, Inc.) — the decisive proceeding on this patent. Petition filed Jan. 14, 2022; instituted Sept. 1, 2022; Final Written Decision Aug. 28, 2023 holding claims 1, 3–17, and 19–30 unpatentable under 35 U.S.C. §103(a) over Best, Bonella, and Mills. Claims 2 and 18 were not shown unpatentable. Panel: Braden, McShane, Szpondowski. https://storage.courtlistener.com/recap/gov.uscourts.txed.[215248](/patent/215248)/gov.uscourts.txed.215248.286.7.pdf
- Parallel district litigation — Netlist v. Micron, W.D. Tex. Nos. 1:22-cv-00134 and 6:21-cv-00430 (claim-construction fight over "memory subsystem"), with the '833 case status recited in the Oct. 10, 2023 joint filing: https://storage.courtlistener.com/recap/gov.uscourts.txwd.[1162347](/patent/1162347)/gov.uscourts.txwd.1162347.75.0.pdf
- 2025–2026 PTAB activity involving the '833 patent but NOT challenging it: Samsung's PGR2026-00001 and IPR2026-00018 (filed Nov. 7, 2025) target the '366 patent, not the '833 patent; Samsung used a copy of US 8,301,833 as Exhibit 1089 (prior-art/background evidence). Both were denied institution on March 23, 2026. Likewise IPR2026-00017 (filed Oct. 27, 2025) targets the '035 patent and was denied institution Feb. 24, 2026; its Exhibit 2006 mentions 8,301,833 only as part of Netlist's collateral schedule. So no 2026 PTAB proceeding is directed at the '833 patent on the record I retrieved.
- Federal Circuit / 2026 dockets: The Google Patents page for this patent lists a Federal Circuit case, No. 24-2282, as family litigation. I separately found active 2026 Netlist appeals involving Samsung and Micron — 24-2240 (argued Mar. 6, 2026, Reyna/Linn/Stark), 24-1859 / 24-1863 (nonprecedential opinion Sept. 2, 2026, Reyna/Linn/Stark), 24-2203 (argued Mar. 6, 2026), and 25-1378 (judgment affirmed under Fed. Cir. R. 36, Dec. 9, 2025) — but none of the dockets I retrieved expressly identifies U.S. 8,301,833 as the patent on appeal; they recite other Netlist patents (e.g., 10,268,608, 10,860,506, and the "rank"-construction appeal previewed at https://fedcircuitblog.com/2026/08/31/argument-preview-netlist-inc-v-samsung-electronics-co/). Netlist and Samsung entered a Settlement and Release Agreement and Patent Cross License Agreement on August 4, 2026, which per Netlist's 10-Q resolved the identified pending litigations between them.
Uncertainty I am flagging explicitly
- Independent-claim identification: I can state with confidence that claim 1 and claim 15 are independent, and that claims 2 and 18 were never challenged. I cannot verify from an authoritative source which of claims 2, 16, 17, or 18 are independent versus dependent, or the exact wording of any claim. The seven claim families above are inferred from the specification's Summary section and Google Patents' "Definitions" extraction, which is not the same as the claim text.
- Priority date discrepancy: The printed patent says the provisional (60/941,586) was filed June 1, 2007; Google Patents lists the prior-art/priority date as 2007-06-01, while some third-party databases (e.g., Unified Patents) list 2007-05-31 for this family. The IPR petition also discusses a second provisional, 60/912,321, in connection with the effective filing date. Treat the front-page date as authoritative.
- IPR2017-00649: I could not confirm from the retrieved record that this proceeding concerned 8,301,833 specifically (a related SK hynix IPR, IPR2017-00692, was cited in the Micron petition as a prior FWD in this family).
Generated 9/15/2026, 12:46:51 PM
Cases on file (9)
Group view →Specific litigation cases in our database that name US patent 8301833. The free-form analysis below may also discuss cases beyond this list.
Lawsuits filed per year
- Micron Technology, Inc. v. Netlist, Inc.filed Dec 11, 2023CV01-23-19920; D. Idaho 1:24-cv-00001District Court of the Fourth Judicial District, Ada County, Idaho; removed to D. Idaho and remanded to Idaho state courtremanded to state court; CAFC appeal pending
Defendants: Netlist, Inc.
- SK hynix Inc. v. Netlist, Inc.filed Jan 13, 2017IPR2017-00649Patent Trial and Appeal Boardsources conflict; terminated with refunds
Defendants: Netlist, Inc.
- SanDisk Corporation v. Netlist, Inc.filed Jun 20, 2014IPR2014-00994Patent Trial and Appeal Boardterminated Dec 16, 2014institution denied
Defendants: Netlist, Inc.
- Netlist, Inc. v. Diablo Technologies, Inc.filed Dec 26, 20134:13-cv-05962U.S. District Court for the Northern District of Californiaunverified
Defendants: Diablo Technologies, Inc.
- SMART Modular Technologies, Inc. v. Netlist, Inc.filed Aug 23, 20134:13-cv-03916 (also 3:13-cv-03916)U.S. District Court for the Northern District of Californiaunverified
Defendants: Netlist, Inc.
- 4:13-cv-05889-YGRU.S. District Court for the Northern District of Californiaunverified
Defendants: SMART Storage Systems, Inc., SMART Modular Technologies, Inc., SMART Worldwide Holdings, Inc., and 1 other
- 8:13-cv-00996U.S. District Court for the Central District of Californiaunverified
Defendants: SMART Modular Technologies, Inc., SMART Worldwide Holdings Inc., SMART Storage Systems Inc.
- 4:13-cv-03901U.S. District Court for the Northern District of Californiaunverified
Defendants: Netlist, Inc.
- 2024-2281; 2024-2282U.S. Court of Appeals for the Federal Circuitpending
Defendants: Micron Technology, Inc.
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
I'll research litigation involving US 8,301,833. Let me start with targeted searches.
Let me dig into the specific district court cases and PTAB/CAFC proceedings.
Let me get outcomes for the earlier 2013–2018 cases and the current CAFC appeal.
Litigation Involving U.S. Patent No. 8,301,833 ("the '833 patent")
Patent: US 8,301,833 B1, "Non-volatile memory module," Appl. No. 12/240,916, filed Sept. 29, 2008, granted Oct. 30, 2012. Assignee: Netlist, Inc. Priority date: June 1, 2007. Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta.
Caveat up front: The '833 patent's own Google Patents litigation record asserts the family "has litigation" and flags a live CAFC case (24-2282). I have cross-checked against the Stanford NPE Litigation Database, Unified Patents dockets, PTAB docket records, and Netlist's SEC disclosures. Where my sources conflict (notably on the SK hynix IPR and on current Idaho/WDTX status), I flag the conflict rather than resolve it. Outcome details for the 2013–2018 N.D. Cal. cases are the weakest part of the record I could retrieve — I say so explicitly below rather than guessing.
A. Netlist's affirmative infringement suits asserting the '833 patent
1. Netlist, Inc. v. SMART Storage Systems, Inc., et al.
- Court / Case No.: N.D. Cal., No. 4:13-cv-05889-YGR (Google Patents also lists this docket)
- Filed: 2013 (N.D. Cal., Judge YGR)
- Plaintiff: Netlist, Inc.
- Defendants: SMART Storage Systems, Inc.; SMART Modular Technologies, Inc.; SMART Worldwide Holdings, Inc.; Diablo Technologies, Inc.
- Patents: '833 patent among others asserted
- Outcome/status: I could not verify a final judgment or settlement figure for this specific docket from a primary source. The docket appears in the '833 IPR exhibits (e.g., Netlist v. SMART Storage Systems, Case 4:13-cv-05889-YGR, Docs. 305-1, 305-8, Third Amended Complaint filed Oct. 7, 2014). Treat the outcome as unresolved on my record.
2. Netlist, Inc. v. Diablo Technologies, Inc.
- Court / Case No.: N.D. Cal., No. 4:13-cv-05962
- Filed: Dec. 26, 2013 (per Stanford NPE Litigation Database)
- Plaintiff: Netlist, Inc.
- Defendant: Diablo Technologies, Inc.
- Outcome/status: Not verified from a primary source; the '833 was among the patents in Netlist's 2013 N.D. Cal. campaign.
3. Netlist, Inc. v. SMART Modular Technologies, et al.
- Court / Case No.: C.D. Cal., No. 8:13-cv-00996 (listed in Google Patents litigation record for the '833 patent)
- Defendants listed: SMART Worldwide Holdings Inc.; SMART Storage Systems Inc.
- Outcome/status: Not verified. This appears to be part of Netlist's 2013 enforcement wave; I do not have a confirmed disposition.
4. Netlist, Inc. v. Micron Technology, Inc., et al. (the principal '833 assertion against Micron)
- Court / Case Nos.: W.D. Tex. (Waco Div.) Nos. 6:21-cv-00430 and 6:21-cv-00431, filed April 28, 2021; consolidated and reassigned as Nos. 1:22-cv-00134 and 1:22-cv-00136 (W.D. Tex., Austin Div., Judge Lee Yeakel)
- Plaintiff: Netlist, Inc.
- Defendants: Micron Technology, Inc.; Micron Semiconductor Products, Inc.
- Patents asserted: U.S. 10,489,314 ('314); U.S. 9,824,035 ('035); U.S. 10,268,608 ('608); U.S. 8,301,833 ('833)
- Accused products: Micron LRDIMMs and NVDIMM enterprise memory modules
- Key events:
- May 11, 2022 – Judge Yeakel stayed the consolidated cases pending Micron's IPRs on all four patents.
- May 4, 2023 – cases reassigned to Docket II, W.D. Tex. Austin Div. (Judge Yeakel retired); later before Judge Robert Pitman.
- Aug. 28, 2023 – PTAB found all challenged claims of the '833 patent unpatentable (IPR2022-00418, below).
- Feb. 21, 2024 – status report filed with Judge Pitman; April 19, 2024 – Netlist moved to transfer to E.D. Tex., Marshall Div.
- Reported later development (third-party report, March 2026): Micron moved to lift the stay, dismiss the case as moot, and recover fees/costs under 35 U.S.C. § 285 as an "exceptional case." The magistrate judge reportedly issued a Report & Recommendation in Netlist's favor, declining to find the case exceptional and recommending dismissal (docket cited: W.D. Tex. 1:22-cv-00134, Doc. 96, courtlistener.com/recap/gov.uscourts.txwd.1162347/gov.uscourts.txwd.1162347.96.0.pdf). I flag this as a third-party/stock-forum summary of the R&R, not a primary-source confirmation.
B. Declaratory judgment / offensive actions brought against Netlist on the '833 patent
5. Diablo Technologies, Inc. v. Netlist, Inc.
- Court / Case No.: N.D. Cal., No. 4:13-cv-03901 (YGR)
- Filed: 2013 (Second Amended Answer and Counterclaims filed Feb. 17, 2014)
- Plaintiff: Diablo Technologies, Inc.
- Defendant: Netlist, Inc.
- Outcome/status: Not verified.
6. SMART Modular Technologies, Inc. v. Netlist, Inc.
- Court / Case No.: N.D. Cal., No. 4:13-cv-03916 (Google Patents also lists 3:13-cv-03916 — same litigation, N.D. Cal. divisional renumbering)
- Filed: Aug. 23, 2013 (per Stanford NPE Litigation Database)
- Plaintiff: SMART Modular Technologies, Inc.
- Defendant: Netlist, Inc.
- Outcome/status: Not verified.
7. Micron Technology, Inc. v. Netlist, Inc. (Idaho "bad faith patent assertion" action — the '833-specific case)
- State court: District Court of the Fourth Judicial District, Ada County, Idaho, Case No. CV01-23-19920, filed Dec. 11, 2023
- Removed federal docket: D. Idaho, No. 1:24-cv-00001 (removed Jan. 2, 2024; assigned to Judge David C. Nye)
- Plaintiff: Micron Technology, Inc.
- Defendant: Netlist, Inc.
- Claim: Idaho Code § 48-1703 — bad-faith assertion of patent infringement, specifically Netlist's assertion of the '833 patent in the W.D. Tex.; damages under §§ 48-1706(b), (d); costs/fees under § 48-1706(c)
- Key events / status:
- Aug. 16, 2024 – D. Idaho remanded to Idaho state court.
- Aug. 20, 2024 – Netlist appealed the remand to the CAFC (No. 2024-2281) and moved to stay the remand; Micron moved (Sept. 17, 2024) to dismiss/transfer the appeal to the Ninth Circuit — denied Dec. 19, 2024.
- Dec. 5, 2024 – Idaho state court denied Netlist's motion to dismiss for lack of personal jurisdiction / failure to state a claim.
- June 12, 2025 – CAFC denied Netlist's motion to stay the remand pending appeal; appeal remains pending.
- Jan. 12, 2026 – Idaho state court appointed a discovery master for pending discovery disputes.
- Trial setting: sources differ across filings — May 11, 2026 (FY2024 10-K), Dec. 7, 2026 (Dec. 2025 10-K), Feb. 1, 2027 (later filing, with CAFC oral argument reported June 5, 2026). The matter has evidently been rescheduled repeatedly; the latest filing I retrieved shows trial set for Feb. 1, 2027.
- Significance: This is the only case in which the '833 patent is the sole patent at issue, and it turns on the alleged bad faith of asserting the '833 patent after the PTAB invalidated it.
C. PTAB proceedings on the '833 patent
8. SanDisk Corp. v. Netlist, Inc. — IPR2014-00994
- Petitioner: SanDisk Corporation
- Petition filed: June 20, 2014 (targeting claims of the '833 patent)
- Outcome: Decision Denying Institution, Paper 8, entered Dec. 16, 2014 (16 pp.). No claims cancelled.
- Patent Owner's Preliminary Response filed Oct. 2, 2014; Declaration of Paul Min, Ex. 1020.
9. Smart Modular Technologies, Inc. v. Netlist, Inc. — IPR2014-01370
- Petitioner: Smart Modular Technologies, Inc. (petition for IPR of claims 1–30 of the '833 patent, filed Aug. 22, 2014; corrected petition filed Sept. 22, 2014)
- Outcome: Decision Denying Institution, Paper 13, entered March 13, 2015 (19 pp.). No claims cancelled.
10. SK hynix Inc., et al. v. Netlist, Inc. — IPR2017-00649
- Petitioners: SK hynix Inc., et al.
- Petition filed: Jan. 13, 2017 (Ex. 1001 = US8301833; Ex. 1003 = Declaration of Ron Maltiel)
- Procedural history (Patexia docket): Notice of Accord Filing Date Jan. 31, 2017; Patent Owner Preliminary Response May 1, 2017; "Trial Instituted Document," July 24, 2017; Petitioner's Request for Rehearing Aug. 23, 2017; Decision Denying Petitioner's Request for Rehearing, Dec. 4, 2017; Petitioner's Request for Refund May 11, 2018; Notice of Refund May 29, 2018.
- Conflict flagged: Google Patents' litigation metadata labels IPR2017-00649 as "Not Instituted – Merits," which contradicts the Patexia docket's July 24, 2017 "Trial Instituted Document." The refund entries suggest the proceeding was terminated early (consistent with a settlement or termination rather than a final written decision). I cannot resolve this from the records available; do not rely on either characterization without pulling PTAB Paper 7 directly.
11. Micron Technology, Inc. v. Netlist, Inc. — IPR2022-00418 ⚠️ Decisive proceeding
- Petitioner: Micron
- Outcome: Final Written Decision, Aug. 28, 2023 — all challenged claims of the '833 patent held unpatentable.
- Appeal: Netlist did not appeal the FWD to the CAFC (confirmed in Netlist's SEC filings and third-party reporting). Google Patents labels this docket "Final Written Decision."
- Practical effect: The asserted claims of the '833 patent were cancelled, which is why the W.D. Tex. '833 action was mooted and why Micron's Idaho bad-faith claim is premised on Netlist's continued assertion of a then-being-invalidated patent. Note that Google Patents' sidebar for the patent still shows legal status "Active, expires 2030-03-02" — that status appears stale and is inconsistent with the Aug. 28, 2023 FWD and the absence of any appeal.
D. Court of Appeals for the Federal Circuit
12. Netlist, Inc. v. Micron Technology, Inc. — CAFC Nos. 2024-2281 and 2024-2282
- Google Patents records Case No. 24-2282 under the '833 patent's family-litigation metadata (portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/24-2282).
- Per Netlist's SEC filings: 24-2281 is Netlist's appeal of the D. Idaho's Aug. 16, 2024 remand order in Micron's '833-based Idaho bad-faith case (Ada County CV01-23-19920). 24-2282 is the parallel appeal in Micron's second Idaho case (Ada County CV01-24-01032, concerning the '918 and '054 patents), consolidated with 24-2281 on Sept. 10, 2024.
- Status: Pending. Micron's motion to dismiss/transfer to the Ninth Circuit was denied (Dec. 19, 2024); Netlist's motion to stay the remand was denied (June 12, 2025). The latest filing I retrieved reports oral argument heard June 5, 2026, with the appeal still pending. (This post-dates the April 26, 2026 date given to me; I report it because the search results are the ground truth per my instructions, but flag the date discrepancy.)
E. Summary table
| # | Case | Court / No. | Filed | '833 Role | Status |
|---|---|---|---|---|---|
| 1 | Netlist v. SMART Storage Systems et al. | N.D. Cal. 4:13-cv-05889-YGR | 2013 | Asserted | Unverified |
| 2 | Netlist v. Diablo Technologies | N.D. Cal. 4:13-cv-05962 | 12/26/2013 | Asserted | Unverified |
| 3 | Netlist v. SMART Modular Technologies | C.D. Cal. 8:13-cv-00996 | 2013 | Asserted | Unverified |
| 4 | Netlist v. Micron (WDTX) | W.D. Tex. 6:21-cv-00430 / -00431 → 1:22-cv-00134 / -00136 | 04/28/2021 | Asserted (NVDIMMs) | Stayed 5/11/2022; '833 claims invalidated 8/28/2023; R&R reportedly recommending dismissal without § 285 fees (Mar. 2026) |
| 5 | Diablo Technologies v. Netlist (DJ) | N.D. Cal. 4:13-cv-03901 | 2013 | Subject | Unverified |
| 6 | SMART Modular Technologies v. Netlist (DJ) | N.D. Cal. 4:13-cv-03916 (also 3:13-cv-03916) | 08/23/2013 | Subject | Unverified |
| 7 | Micron v. Netlist (Idaho bad-faith) | Ada Cnty., Idaho CV01-23-19920; removed as D. Idaho 1:24-cv-00001; appeal CAFC 24-2281 (consol. w/ 24-2282) | 12/11/2023 | Sole patent at issue | Remanded to state court 8/16/2024; CAFC appeal pending; trial most recently set 2/1/2027 |
| 8 | SanDisk v. Netlist | IPR2014-00994 | 06/20/2014 | Challenged | Institution denied 12/16/2014 |
| 9 | Smart Modular v. Netlist | IPR2014-01370 | 08/22/2014 | Challenged | Institution denied 3/13/2015 |
| 10 | SK hynix v. Netlist | IPR2017-00649 | 01/13/2017 | Challenged | Sources conflict (instituted 7/24/2017 per PTAB docket vs. "not instituted" per Google Patents); terminated with refunds by 5/2018 |
| 11 | Micron v. Netlist | IPR2022-00418 | 2022 | Challenged | FWD 8/28/2023 — all challenged claims unpatentable; not appealed |
F. Answers to your specific questions
- Is litigation known? Yes — extensively. The '833 patent is one of Netlist's most-litigated memory-module patents.
- Who has been sued for infringing it? SMART Storage Systems / SMART Modular Technologies / SMART Worldwide Holdings, Diablo Technologies (all 2013, N.D. Cal. and C.D. Cal.), and Micron (2021, W.D. Tex.).
- Who has challenged it? SanDisk (IPR2014-00994), Smart Modular (IPR2014-01370), SK hynix (IPR2017-00649), and Micron (IPR2022-00418). Only Micron's IPR2022-00418 succeeded, resulting in cancellation of all challenged claims on Aug. 28, 2023, with no appeal by Netlist.
- Most active current front: the Idaho bad-faith-assertion litigation (Ada County CV01-23-19920 / D. Idaho 1:24-cv-00001) and the consolidated CAFC appeal Nos. 2024-2281 / 2024-2282, both still pending.
- Where I am not confident: (i) final dispositions of the 2013 N.D. Cal. and C.D. Cal. cases; (ii) whether IPR2017-00649 was actually instituted (conflicting records); (iii) the current Idaho trial date (three different dates appear across filings); (iv) the W.D. Tex. Report & Recommendation favoring Netlist on § 285 fees, which I have only from a third-party forum post citing a CourtListener PDF. I recommend pulling the PTAB Papers 7/8/13 for IPR2017-00649, IPR2014-00994, IPR2014-01370 and the IPR2022-00418 FWD from patentcenter.uspto.gov, and the N.D. Cal. dockets via PACER, before relying on any of the four.
Note on identifiers: I have interpreted all patent numbers literally. Throughout, "'833 patent" = U.S. Pat. No. 8,301,833. Other Netlist patents that appear in the same families or litigation (e.g., '187 = 8,516,187; '243 = 8,671,243; '831 = 8,874,831; '314 = 10,489,314; '035 = 9,824,035; '608 = 10,268,608) are distinct patents and are not being treated as the '833 patent here.
Generated 9/15/2026, 12:46:57 PM
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
Current assignee: Micron Technology, Inc.
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
I'll reconcile the ODP "no proceedings" block against the PTAB case data embedded in the patent record itself, then pull claim-level outcomes.
Good — the ODP block understates reality. Let me pin down the outcome specifics, the appeal, and the 2025-2026 filings the aggregators surfaced.
PTAB Proceedings — US 8,301,833 ("Non-volatile memory module"), Netlist, Inc.
⚠️ Data-integrity warning, up front. The structured "PTAB proceedings on file" block says the USPTO ODP API returns no AIA trial proceedings for this patent. That is wrong, or at minimum badly incomplete. The patent's own record on Google Patents (the authoritative text supplied for this analysis) lists four AIA trials in its "Family has litigation" section, and one of them produced a Final Written Decision invalidating nearly the entire patent. I did not default to "no PTAB activity" because the underlying record contradicts it. Treat the ODP block as a failed lookup, not a negative finding. Two further 2025–2026 Samsung filings surfaced in search but I could not verify they are directed to this patent — they are flagged separately and must not be relied on.
Proceedings overview
Four AIA trial proceedings are on file against US 8,301,833 — all Inter Partes Review; one claims-invalidated (IPR2022-00418, Final Written Decision 2023-08-28), three institution-denied on the merits (IPR2014-00994, IPR2014-01370, IPR2017-00649); zero active, zero settled, zero claims sustained. The bottom line for a defendant is the opposite of "hardened": claims 1, 3–17, and 19–30 were held unpatentable and are canceled — that is essentially the entire claim set, both independent claims (1 and 15) and every substantive dependent claim. The only two claims never adjudicated are claims 2 and 18, which depend from canceled claims 1 and 15 and are therefore inoperative on their face. If a demand letter cites claims 1–17 or 19–30, the patent owner is asserting claims that no longer exist. The '833 patent is, functionally, a dead letter.
IPR2022-00418 — Micron Technology, Inc.; Micron Semiconductor Products, Inc.; Micron Technology Texas LLC v. Netlist, Inc.
Type: Inter Partes Review
Filed: 2022-01-14
Status: Final Written Decision (Google Patents structured entry; substance: all instituted claims held unpatentable)
Judge panel: Georgianna W. Braden, Sheila F. McShane, and Kara L. Szpondowski, Administrative Patent Judges. Szpondowski, APJ, authored the Final Written Decision (per the "Before…" caption on the FWD and Patexia's panel metadata).
Petition grounds: Challenged claims 1, 3–17, and 19–30 (claims 2 and 18 were not challenged). Two grounds were pleaded:
- Ground 1 — collateral estoppel: claims 1 and 15 unpatentable, and Netlist estopped from relitigating issues already adjudicated (the petition relied on the FWD in SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692 (Paper 25, 2018-07-05), concerning sibling patent 8,874,831).
- Ground 2 — § 103(a): claims 1, 3–17, and 19–30 obvious over Best (US 2010/0110748) in view of Bonella (US 2007/0136523) and Mills (US 6,026,465). Supporting exhibits included Best's provisional, US Provisional 60/912,321 — necessary because the petition had to knock the '833 claims off their 2007-06-01 provisional date (Best published 2010-05-06; its § 102(e) date traces to the 2007 provisional). The petition argued the '586 provisional contains neither the word "clock" nor the word "frequency," so the challenged claims were entitled to a priority date no earlier than 2008-06-02.
Institution decision: Instituted 2022-09-01 (Board granted the petition; trial instituted). This is the only one of the four proceedings on this patent that reached trial.
Final Written Decision: 2023-08-28. Verdict at claim level, quoted verbatim from the FWD's summary table and order:
Claims 35 U.S.C. § Reference(s)/Basis Claims Shown Unpatentable Claims Not shown Unpatentable 1, 3–17, 19–30 103(a) Best, Bonella, Mills 1, 3–17, 19–30 — The Board's disposition, quoted: "For the foregoing reasons, we are persuaded that Petitioner established by a preponderance of the evidence that claims 1, 3–17, and 19–30 of the '833 patent are unpatentable" … "ORDERED that claims 1, 3-17, and 19-30 of the '833 patent have been shown to be unpatentable under 35 U.S.C. § 103(a)."
Independent claim 1 (method) and independent claim 15 (system) are both canceled. Every challenged dependent claim is canceled. No claim was sustained. On claim construction, the panel refused Netlist's attempt to import limitations from the specification into "a first mode of operation," holding that the plain claim language "clearly recites the requirements" and that Netlist's citations went to "examples and 'certain embodiments'" — notably rejecting Netlist's argument that the non-volatile subsystem must never communicate during normal operation, and rejecting its claim-differentiation argument built on "decouple from" in claim 16.
Settlement / termination: None. The proceeding ran to a merits FWD.
Appeal: I found no Federal Circuit appeal of the IPR2022-00418 FWD. A CAFC docket (24-2281/24-2282, Micron Technology, Inc. v. Netlist, Inc.) does appear on this patent's record, but its briefing shows it is Netlist's appeal from the Idaho district court's remand orders in Micron's state-law bad-faith-patent-assertion suits — not an IPR appeal; the merits of the patents are expressly "not at issue in this appeal." Patent Owner's Response, Reply, and Sur-Reply briefing in the '833 IPR is documented; no § 90.2 notice of appeal by Netlist appears in any source I retrieved. Caveat: I could not exhaustively search docket 24-xxxx for a Rule 36 affirmance, and IPR appeals are sometimes disposed of without published opinion. Verify on the CAFC docket before relying on finality. If no appeal was taken within the 63-day window (expiring on or about 2023-10-30), the FWD is final and the § 318(b) certificate canceled claims 1, 3–17, and 19–30.
Defensive value: This is the whole ballgame. Claims 1, 3–17, and 19–30 are canceled. Any infringement theory predicated on independent claim 1 or 15 — or on any challenged dependent claim — has no res to stand on, and continued assertion of those claims after 2023-10-30 is Rule 11 exposure. The only formally surviving claims are claims 2 and 18, both of which depend from canceled claims 1 and 15, making them inoperative.
IPR2017-00649 — SK hynix Inc. et al. v. Netlist, Inc.
- Type: Inter Partes Review
- Filed: 2027-01-13 (petition date per docket; Notice of Accord Filing Date 2017-01-31)
- Status: Not Instituted – Merits (Google Patents); substance: Decision Denying Institution, Paper 7, 2017-07-24
- Judge panel: Not published in the sources retrieved.
- Petition grounds: Directed at the '833 patent, with a substantial exhibit set — Bonella (US 2007/0136523) and its provisional (60/749,267), Mills (US 6,602,465 — as designated in the petition, US 6,026,465), Ashmore (US 2006/0212651), Klein (US 6,721,860), Long (US 7,421,552), Maeda (US 2005/0249011), Tsern (US 2007/0070669), Miura (US 7,136,978), Larson (US 6,571,244), plus JEDEC DDR/DDR2 specifications. Declarant: Ron Maltiel. Statutory basis was pre-AIA § 102/§ 103; the record shows the parties disputed whether Bonella teaches the volatile memory subsystem operating at the recited "third clock frequency."
- Institution decision: Denied 2017-07-24 (Paper 7), captioned by the parties as a "Denying Institution" decision. The operative dispute was the "third clock frequency" limitation as applied to Bonella. Petitioner sought rehearing on 2017-08-23; the request for rehearing was denied 2017-12-04; refund issued 2018-05-29.
- Final Written Decision: N/A — no trial.
- Settlement / termination: N/A.
- Appeal: N/A (no appeal lies from a denial of institution).
- Defensive value: Low independent value today (claims are already canceled), but useful as evidence of the depth of the prior art on the third-clock-frequency limitation — three separate petitioners failed to get institution on that limitation before Micron finally cracked the claim with a priority-date attack rather than a pure merits attack.
IPR2014-01370 — SMART Modular Technologies Inc. v. Netlist, Inc.
- Type: Inter Partes Review
- Filed: 2014-09-22 (corrected petition, filed via PRPS)
- Status: Not Instituted – Merits (Google Patents); substance: Decision Denying Institution, Paper 13, entered 2015-03-13
- Judge panel: Not published in the sources retrieved.
- Petition grounds: Claims 1–30 — the full claim set. Eight grounds:
- Grounds 1 & 2: § 102(b) anticipation by and § 103(a) obviousness over Fukuzo (US 2006/0294295) ± Leete (US 2004/0190210);
- Grounds 3 & 4: Ichikawa (US 7,600,142) ± Leete;
- Grounds 5 & 6: Long (US 7,421,552) ± Leete;
- Grounds 7 & 8: Tsunoda (US 7,062,618) ± Leete.
- Declarant: Nader Bagherzadeh. Lead counsel: Michael F. Heafey (King & Spalding). Real party-in-interest: SMART Modular Technologies, Inc.
- Institution decision: Denied 2015-03-13 (Paper 13, 19 pages). On the Ichikawa grounds, the Board was unpersuaded that Ichikawa '142 discloses the recited clock-frequency limitations — "There is an underlying assumption in Petitioner's argument that RAM 13 is clocked at the same speed as the CPU. Petitioner does not provide sufficient support for this assumption," and the declarant's statement was "conclusory." The panel noted that "the '833 patent shows explicitly that controller 62 provides a specific clock signal to the volatile and nonvolatile memory subsystems" (citing Ex. 1001, 17:1–14, Figs. 7–8). Claims 2, 7, 8, 11–13, 18, 23, 24 and 27–29 (depending ultimately from claims 1 and 15) fell with the independent claims.
- Final Written Decision: None — no trial.
- Settlement / termination: N/A.
- Appeal: N/A.
- Defensive value: Confirms the Board's consistent view that the third-clock-frequency limitation was the hardest limitation to meet — and that the winning path (found only in 2023) ran through the priority date, not through the references themselves.
IPR2014-00994 — SanDisk Corporation v. Netlist, Inc.
- Type: Inter Partes Review
- Filed: 2014-06-20 (filing date accorded 2014-07-02)
- Status: Not Instituted – Merits (Google Patents); substance: Decision Denying Institution, Paper 8, 2014-12-16
- Judge panel: Not published in the sources retrieved.
- Petition grounds: The petition is styled a request for review of the '833 patent, and per co-petitioner SMART's characterization in IPR2014-01370, SanDisk's ground relied "in part, on the same reference" as SMART's Fukuzo ground — i.e., Fukuzo '295Pub, in a § 102/§ 103 formulation. I could not retrieve the SanDisk petition's precise claim-by-claim grounds; I am not going to guess them. No § 112 ground is documented.
- Institution decision: Denied 2014-12-16 (Paper 8). The decision is cited across Netlist's later litigation papers (e.g., "IPR2014-00994, Paper 8 (Institution Decision) at 7, 8–9, 11") — note the file-history citations label Paper 8 an "Institution Decision," but its caption and the Google Patents entry make clear it is a denial.
- Final Written Decision: None.
- Settlement / termination: N/A.
- Appeal: N/A.
- Defensive value: This is the first of three failed challenges in 2014–2017 and is the reason the '833 patent was, for roughly nine years, a survivor — three institution denials, no CBM, no PGR (the patent is pre-AIA, so PGR was never available; and no CBM was ever filed despite CBM eligibility running to 2020-09-16).
Flagged, unverified — do NOT treat as proceedings on this patent
- IPR2025-01402 (Samsung Electronics Co., Ltd., petitioner) — surfaced only via an exhibit listing in which Ex. 1061 is the '833 Final Written Decision dated 2025-08-25. That is consistent with either (a) a 2025 Samsung IPR directed at the two surviving claims, 2 and 18, or (b) an IPR on a different Netlist patent that merely cites the '833 FWD as evidence. I could not verify which.
- PGR2026-00001 (Samsung Electronics Co., Ltd., petitioner) — petition exhibit filed 2025-11-07; exhibits 1016–1019 are the old SanDisk/SMART/SK hynix '833 petitions and institution denials. A PGR cannot reach the '833 patent (pre-AIA, § 6 of the AIA), so this proceeding must concern a different patent, with the '833 history used as § 325(d) ammunition.
- IPR2023-00405 / IPR2023-00406 (Micron Technology et al. v. Netlist, Inc.) — filed 2023-01-06, each including a "Petitioners' Motion for Joinder" (Paper 3). The exhibit sets are mixed: IPR2023-00406's Exhibit 1001 is US 11,016,918; IPR2023-00405's exhibits are the prior '833 IPR petitions/decisions plus "Paper 2 – Micron's IPR petition against Netlist's 833 patent." These look like joinder requests rather than new merits challenges to the '833 patent, and I could not confirm their target patents. Verify on PTAB E2E before citing.
If any of the above is a live 2025–2026 proceeding against '833 claims 2 and 18, it changes the "no active proceedings" statement above — but nothing in it would revive claims 1, 3–17, or 19–30.
Strategic summary
Which claims are canceled, sustained, or untested. All challenged claims of US 8,301,833 are canceled: claims 1, 3–17, and 19–30 were held unpatentable under § 103(a) in IPR2022-00418 (FWD 2023-08-28). That includes both independent claims — claim 1 (method) and claim 15 (system) — and every dependent claim between and around them. No claim of the '833 patent has ever been sustained on the merits after institution. The only claims never adjudicated are claims 2 and 18 ("the third clock frequency is substantially equal to the second clock frequency"), which were omitted from Micron's petition (the petition expressly "request[s] inter partes review … of claims 1, 3-17, and 19-30"). Because claim 2 depends from canceled claim 1 and claim 18 depends from canceled claim 15, neither can be infringed independently; a defendant should check the '833 file history for a 37 C.F.R. § 1.321(a) statutory disclaimer of claims 2 and 18, which is the routine post-FWD cleanup step and would leave the patent with literally zero live claims.
Estoppel landscape. IRP2022-00418 produced a merits FWD, so § 315(e)(2) estops Micron, its real parties-in-interest, and their privies from raising in the district court any ground they raised or reasonably could have raised in that IPR — principally Best (US 2010/0110748) in view of Bonella (US 2007/0136523) and Mills (US 6,026,465), plus the priority-date/§ 112 written-description theory built on the '586 provisional's silence as to "clock" and "frequency." For a new defendant, that estoppel is irrelevant — but so is the proceeding's utility, because the claims it killed are already dead. Critically, no estoppel arises from the three institution denials (IPR2014-00994, IPR2014-01370, IPR2017-00649): § 315(e) estoppel attaches only after a final written decision, so the art in those petitions — Fukuzo, Ichikawa, Long, Tsunoda, Leete, Bonella, Ashmore, Klein, Maeda, Tsern, Miura, Larson, and the JEDEC DDR/DDR2 standards — remains unencumbered by statutory estoppel and remains available to a new petitioner. The practical obstacle is not estoppel but discretionary denial: a follow-on petition recycling that art now faces General Plastic follow-on factors and § 325(d) ("same or substantially the same prior art … previously presented"). The cleanest remaining use of that art is as invalidity art in district court litigation under § 282, or as the basis of a § 112/(b) written-description attack on the 2007-06-01 provisional priority claim — the very theory that worked.
Pattern signals. This patent drew four separate petitioners over eleven years: SanDisk (2014), SMART Modular (2014), SK hynix (2017), and Micron (2022). That is a textbook assertion-driven escalation, and it also explains why the patent was widely asserted — it sat in the middle of the Netlist v. Smart Modular/Diablo, Netlist v. Samsung, Netlist v. Micron, and Netlist v. SK hynix litigations. Netlist has been a persistent, aggressive patent owner — the Idaho appeals (CAFC 24-2281/24-2282) are Netlist fighting to keep Micron's bad-faith-assertion claims in federal court, and Netlist's own brief boasts of a $445M Micron verdict, a $118M Samsung verdict, and a $300M Samsung verdict. But on this patent the record runs the other way: Netlist litigated the '833 IPR to the end and lost every challenged claim. I found no defensive aggregator (e.g., Unified Patents) in the chain for this patent — the four petitioners are all operating companies, which means there is no RPI/privy relationship tying a present-day defendant to the prior petitioners. Note also the corporate-history wrinkle in the '833 record: an SVIC No. 28 security interest was recorded against Netlist on 2015-11-20 and released 2023-11-20 — worth checking if you are weighing the patent owner's standing or the real party in interest on any surviving claim.
Recommended next steps
- Pull the IPR2022-00418 Final Written Decision and quote its disposition in any response to a demand letter. Public copy: Micron Technology, Inc. v. Netlist, Inc., IPR2022-00418, Paper 29 (PTAB Aug. 28, 2023) (Szpondowski, APJ), available at https://storage.courtlistener.com/recap/gov.uscourts.txed.[215248](/patent/215248)/gov.uscourts.txed.215248.286.7.pdf (also retrievable via PTAB E2E / https://patents.google.com/patent/US8301833/en#legal-events). The operative language: "ORDERED that claims 1, 3-17, and 19-30 of the '833 patent have been shown to be unpatentable under 35 U.S.C. § 103(a)."
- Confirm finality. Check the Federal Circuit docket for any Netlist notice of appeal from the 2023-08-28 FWD (deadline ≈ 2023-10-30 under 37 C.F.R. § 90.2). If none, the FWD is final, the § 318(b) certificate has issued, and claims 1, 3–17, and 19–30 are canceled by operation of law — making post-October 2023 assertion of those claims indefensible. I have not been able to confirm finality myself; do not state it as settled in a filing without checking.
- Check the '833 file history for a statutory disclaimer of claims 2 and 18 (37 C.F.R. § 1.321(a)) and for any certificate-of-correction activity. Claims 2 and 18 are the only theoretical exposure left; they are inoperative dependents, and their prosecution history (the examiner's indefiniteness rejection over "approximately equal," cured by amendment to "substantially") makes them thin targets — the same art that killed claims 1 and 15 would kill them, and their sole added limitation ("substantially equal") is the kind of relative-term limitation the Board has repeatedly found indefinite or obvious.
- If someone is asserting the sibling patents instead, do not conflate them. The FWD record shows sibling/continuation patents — 8,516,187, 8,671,243, 8,874,831, 8,884,791, 9,824,035, 10,268,608, 10,489,314, 11,016,918, 11,232,054 — with differing outcomes. The '833 FWD is not a silver bullet against those; only the priority-date/anterior-written-description theory (the '586 provisional lacking "clock" and "frequency") travels across the family, and it is the most valuable exportable asset from this proceeding.
- If no PTAB activity is shown in the ODP-based tools you use, do not trust that output for this patent. The API returned zero proceedings for a patent with four trials and one merits FWD. Escalate the data-quality issue to whoever maintains that ingest before relying on "no PTAB activity" for any Netlist-family patent.
Generated 9/15/2026, 12:47:35 PM
Ownership chain (3)
Asserters network →Structured records extracted from the assignment-history narrative below. Each entity links to its full ownership-network profile.
? · recorded 2012-07-06 · Assignment
CHEN, CHI-SHE; MILTON, SCOTT; BHAKTA, JAYESH; SOLOMON, JEFFREY C.Netlist, Inc.
2015-11-18 · recorded 2015-11-20 · Security Agreement
Netlist, Inc.SVIC No. 28 New Technology Business Investment L.L.P.
securitization
? · recorded 2023-11-20 · Release
SVIC No. 28 New Technology Business Investment L.L.P.Netlist, Inc.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
I'll verify the assignment record and litigation history with live sources before reconstructing the chain.
Now let me pin down reel/frame details, correspondence data, and Netlist's corporate status.
Ownership & Assignment Reconstruction — US 8,301,833 ("Non-volatile memory module")
Critical sourcing caveat up front. I was unable to retrieve the USPTO Assignment Center record itself for this patent (search returned generic tool documentation, not the patent-specific hit list). Accordingly no reel/frame numbers and no correspondent-of-record names appear below — I will not invent them. Everything on the ownership timeline is sourced from the legal-events record on the Google Patents page for US 8,301,833 (fetched 2026-08-28), corroborated where possible against Netlist's SEC-filed credit agreements and PTAB/litigation filings. Verify the reel/frame and correspondent fields directly at https://assignmentcenter.uspto.gov/ (legacy mirror: https://assignment.uspto.gov/patent/index.html) — search by patent number 8301833 and read the "Correspondent" block on each record. That field is exactly the one this analysis could not populate.
Inventors
| Inventor | Employer at filing | Notes |
|---|---|---|
| Chi-She Chen | Netlist, Inc. (per recorded assignment) | Named on the 2012-07-06 inventor→Netlist assignment |
| Jeffrey C. Solomon | Netlist, Inc. (per recorded assignment) | Named on the same instrument |
| Scott Milton | Netlist, Inc. (per recorded assignment) | Named on the same instrument |
| Jayesh Bhakta | Netlist, Inc. (per recorded assignment) | Named on the same instrument |
- The application (12/240,916, filed 2008-09-29) is a continuation of 12/131,873 (filed 2008-06-02), claiming benefit of provisional 60/941,586 (filed 2007-06-01). Google Patents lists the priority/prior-art date as 2007-06-01.
- Unusual pattern? No. All four inventors conveyed to the same assignee (Netlist) in one instrument; there is no evidence of inventor departure or a split inventorship picture. I could not independently verify their job titles or whether any left Netlist within 12 months of filing — no source retrieved establishes that. Do not treat this as a finding either way.
Original assignee
Netlist, Inc. (Irvine, California) — named as applicant at the 2008-09-29 filing and as assignee on the issued patent (2012-10-30). Current assignee per Google Patents: Netlist, Inc.
- Did they ship a product embodying the claims? Yes. Netlist's own 10-Q language: "We were the first to develop and market memory subsystems that incorporate both DRAM and NAND in a single NVvault persistent DIMM solution for backup of volatile data to non-volatile NAND." That is precisely the subject matter of this patent — a volatile memory subsystem plus a non-volatile (NAND flash) subsystem with a controller that backs up volatile data on a trigger condition.
- Primary line of business: design and sale of high-performance memory subsystems to OEMs (DRAM/NAND modules), plus an active patent-licensing and enforcement program.
- Current status: operating, publicly traded (OTCQB: NLST; ISIN US64118P1093). It is a small-cap with a long history of capital scarcity — the FY2012 10-K (filed 2013-03-29) discloses only $5.3 million in FDIC-insured cash and cash equivalents at 2012-12-29, a "significant year over year revenue decline," and material reductions in R&D headcount. I found no evidence of a Chapter 7 or Chapter 11 filing. Do not record a bankruptcy fire-sale signal on this record.
Assignment timeline
Reel/frame: NOT RETRIEVED. Four records exist per the legal-events feed; the reel/frame identifiers and correspondents could not be obtained from any source I was able to pull. Fields marked ⚠️ are gaps, not absences.
2008-09-29 — Application filed by Netlist, Inc. (US 12/240,916). Not a recorded assignment; it is the filing event.
Conveyance type: n/a (filing) · Context: original filing by applicant.
Execution date: not exposed / recorded 2012-07-06 — Reel ⚠️ not retrieved
- Conveyance: Assignment of Assignors' Interest ("see document for details")
- Assignor: CHEN, CHI-SHE; MILTON, SCOTT; BHAKTA, JAYESH; SOLOMON, JEFFREY C. (inventors)
- Assignee: NETLIST, INC.
- Correspondent: ⚠️ not retrieved. Cannot run the recurrence test. This is the single most valuable missing datum on the page: if the same correspondent appears on both this record and the 2015-11-20 lien, that tells you Netlist used one house firm for its whole chain. Until you read it off Assignment Center, flag as unclear, not "not present."
- Context: Founding assignment —Inventors→employer. Note the four-year lag between filing (2008) and recordation (2012), which is routine cleanup timing for a continuation family and is not evidence of a fire-sale.
Executed ~2015-11-18 / recorded 2015-11-20 — Reel ⚠️ not retrieved
- Conveyance: SECURITY INTEREST ("see document for details") — a lien, not a transfer of title
- Assignor: NETLIST, INC.
- Assignee: SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P. (a Korean limited liability partnership)
- Correspondent: ⚠️ not retrieved
- Context: Securitization / secured financing. This is the patent-collateral leg of Netlist's Senior Secured Convertible Promissory Note and Warrant Purchase Agreement dated November 18, 2015 — a $15,000,000 principal note plus a warrant for up to 2,000,000 shares — documented in Netlist's own SEC exhibits (Registration Rights Agreement and Intellectual Property Security Agreement, both dated 2015-11-18; Intercreditor Agreement with Silicon Valley Bank). Under that Security Agreement SVIC took first-priority collateral in Netlist's patents (the "Creditor Priority Collateral" is defined as all letters patent of Borrower). Confirmed at https://contracts.justia.com/companies/netlist-inc-2601/contract/[492100](/patent/492100)/ and the courtlistener exhibits in Netlist v. Samsung, C.D. Cal. 8:20-cv-00993 (Doc. 150-3).
- Cross-check worth doing: Netlist's PTAB briefing in the 2025 Samsung IPR cites, immediately before the entity name "SVIC No. 28 New Technology Business Investment L.L.P.," a reference to the Samsung Venture Investment Corporation website — consistent with the SVIC numbering convention. Moderate confidence, not proven: if SVIC No. 28 is a Samsung Venture arm, then between 2015 and 2023 a Samsung venture affiliate held a first-priority lien on the very patents Netlist later asserted against Samsung. That is a financing relationship, not a privateering arrangement, and should not be characterized as one.
Executed: not exposed / recorded 2023-11-20 — Reel ⚠️ not retrieved
- Conveyance: RELEASE BY SECURED PARTY ("see document for details")
- Assignor: SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P.
- Assignee: NETLIST, INC.
- Correspondent: ⚠️ not retrieved
- Context: Lien extinguishment — ownership reconsolidated in Netlist. Netlist got the encumbrance released; the patent did not change hands. Timing is notable: the release postdates the April 2023 Samsung jury verdict ($303M) and precedes the later $118M Samsung verdict — consistent with a lender being repaid out of, or alongside, enforcement recoveries.
Net: three recorded events since 2008 — two of which are the grant and the release of a single security interest. The patent has never left Netlist's ownership.
Timeline diagram
timeline
title Ownership of US 8301833
2007 : Provisional application filed
2008 : Application filed by Netlist Inc
2012 : Patent issued to Netlist Inc
: Inventors assign rights to Netlist
2015 : SVIC No 28 records security interest
2020 : Netlist sues Samsung and Google
2022 : Netlist sues Micron
2023 : SVIC lien released
: PTAB final written decision on the 833 patent
2024 : Federal Circuit appeal docketed
NPE / troll-pattern signals
Shell-entity transfer — NOT PRESENT. There is no assignment of this patent into a licensing-only vehicle. The only two non-inventor records are (a) the 2015-11-20 security interest running from Netlist to SVIC No. 28 and (b) the 2023-11-20 release running back to Netlist. Neither conveys title. Title has been continuously with Netlist, Inc. since 2008.
Known asserter in the chain — NOT PRESENT on the named-assignee chain. No Acacia, Marathon, IV, IPNav, Wi-LAN/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock or Spangenberg entity appears anywhere in the ownership record. Caveat for balance: a Korean trade publication covering the May 2025 HBM suit described Netlist itself as a "U.S. patent management firm (NPE)" (Yonhap Infomax, 2025-05-21) — press labeling, not an assignment-record fact. The public list you asked me to compare against does not include Netlist.
Repeat correspondent across the chain — UNCLEAR (data gap, not a negative finding). The correspondent field did not resolve for any of the three recorded events. There are only three records total, so the recurrence sample is thin anyway; the test that matters here is whether the 2012-07-06 and 2015-11-20 records share a correspondent. Read that field off Assignment Center before drawing any conclusion.
Cascading transfers — NOT PRESENT. No chained LLC-to-LLC transfers at all. Span between the only two substantive records is 8 years (2015→2023), the opposite of the <24-month cascade pattern.
Pre-litigation transfer — NOT PRESENT. The only lien predates the earliest assertion activity on this family (2013 CAND/CACD dockets; the 2020 and 2022 suits) by roughly 3–5 years, and it is a security interest rather than an ownership transfer, so it cannot serve a standing/venue-clearing function. The 2023-11-20 release is a post-litigation event, not pre-litigation.
Bankruptcy fire-sale — NOT PRESENT. No Chapter 7/11 located for Netlist. The company passed through a severe revenue decline in FY2012–FY2013 but recapitalized through secured debt (SVIC, 2015; SV Bank facility dated 2009/2015) rather than a court-supervised asset sale. This is a genuine "not present" — the 2013 10-K shows stress, not a docket number.
Privateering — NOT PRESENT, and the structure points the other way. There is no operating-company parent asserting through a retained NPE. What is present is Netlist self-monetizing: pledging its own patents as collateral to SVIC and, per the May 2017 intercreditor agreements, monetizing SK hynix litigation recoveries through a third-party litigation funder (TR Global Funding V, LLC, whose "TRGP Priority Collateral" is expressly the commercial tort claim and recoveries from ITC Inv. No. 337-TA-1023 and C.D. Cal. 8:16-cv-1605, with Mintz Levin engaged under a December 8, 2016 litigation counsel fee agreement). That is litigation finance, a monetization vector — not privateering.
Defensive aggregator — NOT PRESENT. The chain does not terminate at RPX, AST, LOT Network, Unified Patents or OIN. Netlist retains title and is the plaintiff of record.
Evidence of a live assertion program on this asset (context for the verdict): this patent was asserted by Netlist against Micron in W.D. Tex. 1:22-cv-00134 (per Netlist v. Micron, Doc. 67-1, which briefs the '833 patent claim terms); Micron's IPR was instituted and the PTAB's Final Written Decision in IPR2022-00418 is recorded on the Google Patents legal-events feed, with oral argument held 2023-06-07 per Netlist's own status disclosure. Earlier rounds: IPR2014-00994, IPR2014-01370 and IPR2017-00649 (all "Not Instituted — Merits"). Netlist's 2013–2024 district court dockets include C.A.N.D. 4:13-cv-03901, 4:13-cv-03916, 4:13-cv-05889, C.A.C.D. 8:13-cv-00996, W.D. Tex. 6:21-cv-00430 (Samsung), W.D. Tex. 1:22-cv-00134 (Micron), D. Idaho 1:24-cv-00001, and a Federal Circuit appeal at 24-2282.
Verdict
Operating-company assertion.
The ownership record terminates at the original operating assignee, not at an asserter vehicle: the only post-issuance records are a security interest recorded 2015-11-20 (Netlist → SVIC No. 28, the $15M secured convertible note collateralized by Netlist's patents) and its release by secured party recorded 2023-11-20 (SVIC No. 28 → Netlist), so title has never left Netlist. Netlist ships the NVvault persistent DRAM+NAND DIMM, which reads on this patent's own abstract ("volatile and non-volatile memory and a controller which... backs up the volatile memory using the non-volatile memory in the event of a trigger condition"), and it is asserting the '833 patent against direct competitor memory manufacturers — Micron (W.D. Tex. 1:22-cv-00134) and Samsung — i.e., actual competitors, not downstream end users. Two honest qualifiers: (i) the reel/frame and correspondent fields were not retrievable, so signal #3 is unassessed rather than cleared; and (ii) Netlist's own SEC-filed structure — patent collateral to a Samsung-linked lender plus SK hynix-recovery-backed litigation funding from TRGP with Mintz Levin — shows heavy litigation monetization, which is a profitability critique of Netlist but is not an NPE-chain finding.
Verify at: https://assignmentcenter.uspto.gov/ — search patent number 8301833; confirm the reel/frame and correspondent on the 2012-07-06, 2015-11-20 and 2023-11-20 records before relying on this verdict.
Generated 9/15/2026, 12:47:16 PM
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
I'll pull the authoritative reference lists for US 8,301,833 from USPTO and the patent's own face.
Let me pull the patent's cited-references table from independent full-text sources.
Let me target the front-page reference list directly.
Prior Art of Record for US 8,301,833 B1 — Reference-by-Reference § 102 Screen
Patent searched: US 8,301,833 B1 ("Non-volatile memory module," Chen et al., Netlist, Inc.) — https://patents.google.com/patent/[US8301833B1](/patent/US8301833B1)/en
Numbers deliberately excluded as NOT this patent (mysearches returned them; they are different documents with colliding digits): JP 8301833 A (Japanese publication, 1996), ZA 8301833, and WO 1983001833 A1 ("Coatings thickness and surface roughness comparator"). None of these is US 8,301,833, and none is used below.
0. Sourcing disclosure and one correction to the earlier sections
What I could verify directly. I retrieved (a) the Google Patents record for US 8,301,833 including its classification, definitions and family data; (b) verbatim claim text for claim 1 and dependents from the Justia full-text record for patent 8301833 (https://patents.justia.com/patent/8301833); (c) the PTAB's disposition and the identity of the applied references from the IPR2022-00418 Final Written Decision (https://storage.courtlistener.com/recap/gov.uscourts.txed.[215248](/patent/215248)/gov.uscourts.txed.215248.286.7.pdf) and the Micron petition (https://storage.courtlistener.com/recap/gov.uscourts.txed.[1162347](/patent/1162347)/gov.uscourts.txed.1162347.67.1.pdf).
What I could NOT verify. I could not retrieve a clean, faithful transcription of the printed "References Cited" table on the front page of US 8,301,833 itself. The front-page scans that surfaced in my searches (e.g. the CourtListener exhibit at https://www.courtlistener.com/docket/63378313/1/3/netlist-inc-v-micron-technology-inc/authorities/ and the CAFC exhibit at https://www.archive.org/download/gov.uscourts.cafc.22141/gov.uscourts.cafc.22141.23.0.pdf) are front pages of later Netlist family members that cite the '833 — you can tell because they list "8,301,833 B1 10/2012 Chen et al." among the cited references. So the reference list below is assembled from: (i) those exhibits where the reference also appears in the '833's file-history search strings (the PE2E EAST search histories cite "7409590", "20100274953", "6336174", "8301833", "7111142", "20070192627" together); (ii) the SumoBrain record previously relied on; and (iii) the IPR record. Confidence is graded per entry. I have not invented any citation, date or number.
⚠️ Correction to the earlier "Patent summary" section. That section inferred seven independent claims from the specification's seven Summary paragraphs and Google Patents' "Definitions" extraction. That is wrong, and it contradicts the PTAB record already quoted in the earlier sections. The verified structure is:
- Claim 1 — "A method for controlling a memory system operatively coupled to a host system…" (independent; method)
- Claims 2–14 — depend from claim 1 (claim 2: "the third clock frequency is substantially equal to the second clock frequency"; claim 3: "the memory system is not powered by a battery…")
- Claim 15 — "A memory system operatively coupled to a host system… a volatile memory subsystem operable at a first clock frequency… a non-volatile memory subsystem operable at a second clock frequency… operable at a third clock frequency… less than the first clock frequency" (independent; system)
- Claims 16–30 — depend from claim 15 (claim 16 adds the decoupling circuit; claim 18 parallels claim 2)
Two independents, not seven. The seven Summary paragraphs describe embodiments/species, not separate claims. This matters materially for the § 102 question: the only claims that survive as live independent targets are claims 1 and 15, and 18 of 30 claims are untested in my sources.
A. References Cited on the face of the '833 (the patent's own "References Cited" list)
| # | Full citation | Pub. / filing date | Brief description | Source confidence |
|---|---|---|---|---|
| A1 | US 4,420,821 A (Hoffman) | Issued 12/1983 (Dec. 27, 1983) | Volatile RAM with non-volatile backup storage; restore to volatile on power-up | High (appears in reproduced front pages) |
| A2 | US 4,449,205 A (Hoffman) | Issued 5/1984 | Companion Hoffman backup-memory disclosure | High |
| A3 | US 5,519,663 A (Harper, Jr. et al.) | Issued 5/1996 (May 21, 1996) | "Preservation system for volatile memory with nonvolatile backup memory" | High |
| A4 | US 6,336,174 B1 (Li et al.), Maxtor | Issued 1/2002 (Jan. 1, 2002) | "Hardware assisted memory backup system and method" — trigger detection (power failure, OS hang-up, unexpected reset), electrical isolation of the module from the host, auxiliary power source, controller copying volatile→non-volatile and restoring back; explicit write-cache/early-acknowledge rationale | High (named in the '833 file-history EAST searches and in the IPR-2023 exhibits) |
| A5 | US 6,336,176 B1 (Leyda et al.) | Issued 1/2002 | Memory configuration-data protection; NV retention of memory configuration | Medium |
| A6 | US 6,799,244 B2 (Tanaka et al.) | Issued 9/2004 | Storage control unit with a volatile cache and a non-volatile backup cache | Medium |
| A7 | US 7,409,590 B2 (Moshayedi et al.) | Issued 8/2008 (Aug. 5, 2008) | Protection against data corruption due to power failure in a solid-state memory device | High (named in the file-history EAST searches as "7409590") |
| A8 | US 7,111,142 B2 (Seagate Technology / Hewlett-Packard) | Priority 2002-09-12 | "System for quickly transferring data" | Medium (listed as "Patent Art" for the family publication US 2012/0271990 A1, app. 13/536,173 — a family member, not verified as on the '833 face) |
| A9 | US 5,675,725 A (CA Technologies) | Priority 1993-07-18 | "Computer backup system operable with open files" | Medium (same source as A8) |
| A10 | US 2004/0190210 A1 (Leete) | Pub. 9/2004 (Sept. 30, 2004) | "Memory back up and content preservation" | High (also a reference in IPR2014-01370) |
| A11 | US 2002/0083368 A1 (Abe et al.) | Pub. 6/2002 | Computer system and memory-management method across modes | Medium |
| A12 | US 2007/0192627 A1 (Oshikiri) | Pub. 8/16/2007; US Cl. 713/191 | "Semiconductor memory and data access method" — mode-dependent memory operation | High (Examiner-applied; named in file-history searches) |
| A13 | US 2008/0195806 A1 (Cope) | Pub. 8/14/2008; US Cl. 711/111 | "System and method for controlling memory operations" — memory-operation control | High (Examiner-applied) |
| A14 | Possibly US 2010/0274953 A1 (Lee et al.) | Pub. 2010 | Data storage device / information processing system incorporating same | Low–Medium (appears in file-history search string "20100274953") |
None of A1–A14 is listed on the '833 face as an anticipation reference; A12 and A13 were the Examiner's § 103 companions to A4 (see § B).
B. References the Examiner actually applied during prosecution of the '833
Per the Micron petition's recitation of the file history, the claims were rejected twice:
- Li (US 6,336,174) + Oshikiri (US 2007/0192627)
- Li (US 6,336,174) + Cope (US 2008/0195806)
Both were § 103 rejections. The only feature the Examiner could not find in Li was the first/second/third clock-frequency recitation — which is why A12/A13 (both "mode-dependent memory operation" references) were pulled in.
C. References actually used against the '833 in AIA trials (the operative prior art)
C-Group 1 — IPR2022-00418 (Micron), the Ground that killed the patent
| Ref. | Full citation | Date | Description |
|---|---|---|---|
| Best | US 2010/0110748 A1 — § 102(e) date via US Prov. 60/912,321, filed 2007-04-17 | Pub. 2010-05-06 | Composite hybrid memory device: DRAM die + flash die in one IC package with a shared interface circuit steering host commands to either die; "shadow operation" backup/mirroring; non-overlapping address-range modes |
| Bonella | US 2007/0136523 A1 (prov. 60/749,267, filed 2005-12-08) | Pub. 2007-06-14 | Hybrid DRAM + flash module with module controller; DRAM write-buffer flush to flash on power loss ("power loss algorithm"); UPS capacitors as backup; "Power State Aware" levels incl. Power Level 4 limiting DRAM performance / reducing DRAM operating frequency for "major power savings" |
| Mills | US 6,026,465 (Petition also referenced US 6,602,465 — identifier discrepancy flagged, not auto-corrected) | Issued 2000-02-15 | Synchronous Flash Interface (SFI): flash clocked from an external clock input, all external operations synchronized to a clock edge, internal bank interleaving |
Disposition: FWD 2023-08-28 — "ORDERED that claims 1, 3-17, and 19-30 of the '833 patent have been shown to be unpatentable under 35 U.S.C. § 103(a)." Claims 2 and 18 were not challenged. Ground pleaded as § 103(a); a separate Ground 1 was collateral estoppel.
C-Group 2 — the unsuccessful 2014/2017 petitions (art remains un-estopped)
| Ref. | Full citation | Date | Description / role |
|---|---|---|---|
| Fukuzo | US 2006/0294295 A1 | Pub. 2006-12-28 | Primary reference in IPR2014-01370 (Grounds 1–2) and cross-referenced to SanDisk's IPR2014-00994 ground |
| Leete | US 2004/0190210 A1 | Pub. 2004-09-30 | Secondary reference paired with Fukuzo, Ichikawa, Long, Tsunoda |
| Ichikawa | US 7,600,142 B2 | Issued 2009-10-06 | IPR2014-01370 Grounds 3–4; the Board found the clock-frequency showing "conclusory" and unsupported |
| Long | US 7,421,552 B2 | Issued 2008-09-02 | IPR2014-01370 Grounds 5–6; flash-based memory vault |
| Tsunoda | US 7,062,618 B2 | Issued 2006-06-13 | IPR2014-01370 Grounds 7–8 |
| Ashmore | US 2006/0212651 A1 | Pub. 2006-09-21 | IPR2017-00649 exhibit set |
| Klein | US 6,721,860 B2 | Issued 2004-04-13 | IPR2017-00649 exhibit set |
| Maeda | US 2005/0249011 A1 | Pub. 2005-11-10 | IPR2017-00649 exhibit set |
| Tsern | US 2007/0070669 A1 | Pub. 2007-03-29 | IPR2017-00649 exhibit set |
| Miura | US 7,136,978 B2 | Issued 2006-11-14 | IPR2017-00649 exhibit set |
| Larson | US 6,571,244 B2 | Issued 2003-05-27 | IPR2017-00649 exhibit set |
| JEDEC | JESD79 / JESD79-2B (DDR and DDR2 specifications) | pre-2007 | Admitted state of the art for DDR clocking; used to show synchronous DRAM clock frequencies were conventional |
D. § 102 screen — reference by reference
Threshold point that governs the whole analysis. Claims 1 and 15 both require a three-frequency state machine on a single single-reference basis: volatile at 1st freq (volatile↔host mode), NVM at 2nd freq (volatile↔NVM mode), volatile at 3rd freq < 1st in that same second mode. Nothing in the record — not the face-of-patent references, not the four petitioners' art — was ever applied as a § 102 anticipation of claims 1 or 15. Every one of these references was used in a § 103 combination. I therefore report below what each reference does reach and what single limitation blocks anticipation; I am not going to label anything "anticipatory" that the record does not support.
| Reference | Claims for which § 102 is arguable | The blocking limitation |
|---|---|---|
| A4 — US 6,336,174 (Li) | Claim 16 (the decoupling/isolation element) and, arguably, claim 3 (no battery in the second mode if Li's auxiliary source is a capacitor, not a battery). Architecture of claim 15's preamble is met: module + host, volatile subsystem, NVM subsystem, controller, host-mode operation, trigger-driven backup. | No clock-frequency teaching at all. Li's disclosure is trigger/isolation/auxiliary-power mechanics. Cannot reach claims 1 or 15. |
| A3 — US 5,519,663 (Harper) | Narrow backup-preservation dependent claims only, if any depend solely on volatile+NV backup. | No host/NVM mode architecture, no frequencies. |
| A1/A2 — US 4,420,821 / 4,449,205 (Hoffman) | None squarely; § 102(b) background art. | 1983-era static-RAM backup; no controller mediation, no clocking scheme. |
| A7 — US 7,409,590 (Moshayedi) | Power-failure protection dependent claims. | No mode/frequency architecture; directed to SSD data integrity. |
| A10 / C-G2 Leete — US 2004/0190210 | Volatile-backup dependent claims. | No second/third-frequency teaching. |
| A12 — US 2007/0192627 (Oshikiri) | Examiner applied it for "mode-dependent memory operation" — potential § 102(e) anticipation of whatever dependent claim recites mode-dependent operation. | § 102(e) timing caveat: published 2007-08-16, after the nominal 2007-06-01 priority date. Qualifies only if its US filing date precedes the claims' effective date, which Micron argued is 2008-06-02 (the '586 provisional contains neither "clock" nor "frequency"). Verify its filing date before relying on it. |
| A13 — US 2008/0195806 (Cope) | Same posture as Oshikiri. | Published 2008-08-14; same § 102(e) timing exposure. |
| Best — US 2010/0110748 | Hybrid DRAM+flash-with-shared-interface and shadow-backup dependent claims. Not claims 1/15. | No reduced-frequency-during-backup teaching. Note its § 102(e) anchor is Prov. 60/912,321 (2007-04-17) — this is the reference whose date is safe regardless of how the priority fight resolves. |
| Bonella — US 2007/0136523 | The only single reference with a genuine § 102 argument against claims 1, 15, 2 and 18 — it discloses hybrid DRAM+flash with a module controller, DRAM→flash flush on power loss, and explicitly reducing DRAM operating frequency (Power Level 4) for power savings on a finite reserve. | The Board twice refused to find the "third clock frequency" met by Bonella (IPR2017-00649 denial on that limitation; IPR2014-01370 denial on the analogous issue). Whether Bonella's "second mode" is a volatile↔NVM data-communication mode, and whether its flash side is clocked at a second frequency, is the contested gap. No tribunal has held Bonella anticipatory. |
| Mills — US 6,026,465 | Supplies only the "clocked non-volatile interface." | Cannot anticipate alone; purely a § 103 gap-filler for the "second clock frequency." |
| Fukuzo / Ichikawa / Long / Tsunoda (C-G2) | None. Each was institution-denied, including on the clock-frequency limitation. | Clock-frequency limitations. |
E. Bottom line
- There is no reference of record that anticipates claims 1 or 15 under § 102. The `833's novelty over every cited reference is the three-frequency recitation, and the entire four-petition, eleven-year history confirms it: three institutions denied on that exact limitation and the fourth succeeded only by attacking the 2007-06-01 priority date and then combining Best + Bonella + Mills under § 103(a).
- The closest single-reference § 102 candidate is Bonella (US 2007/0136523 A1, pub. 2007-06-14) against claims 1, 15, 2 and 18 — because it alone discloses reducing DRAM frequency during a power-loss backup. It is a candidate, not an adjudicated anticipation, and the PTAB never credited it as one.
- The most likely § 102(e) candidates for dependent claims are Li (US 6,336,174 B1) — isolation, trigger detection, auxiliary power, backup/restore — and Oshikiri (US 2007/0192627 A1) / Cope (US 2008/0195806 A1) for mode-dependent operation, subject to the priority-date fight.
- Claims 2 and 18 are the only live claims, and their added limitation ("third ≈ second clock frequency") is precisely the limitation Bonella most nearly discloses — so they add little distance from the art that killed claims 1 and 15.
- Art that is unencumbered by § 315(e) estoppel: everything in the three institution-denied petitions — Fukuzo, Ichikawa, Long, Tsunoda, Leete, Ashmore, Klein, Maeda, Tsern, Miura, Larson, and the JEDEC DDR/DDR2 specifications — remains available. General Plastic / § 325(d) discretion, not estoppel, is the practical obstacle.
F. Caveats and open items
- The '833's own printed "References Cited" table was not directly retrievable. Entries A5, A6, A8, A9, A11 and A14 are at Medium/Low confidence and should be confirmed on the printed front page or in Patent Center before being cited in a filing. A1–A4, A7, A10, A12 and A13 have corroboration in reproduced front pages and/or the '833's own EAST file-history search strings.
- Claim text for claims 3–14 and 16–30 is not in my sources. My § 102 mapping of those claims is inferential and must not be treated as a claim-chart.
- Identifier discrepancies flagged, not corrected: Mills is cited as US 6,026,465 in the FWD and as US 6,602,465 in petition-side materials; Bonella's provisional is cited as 60/749,267 in the IPR2017-00649 list and as application 11/635,926 elsewhere. Resolve from the PTAB papers before quoting.
- Priority-date sensitivity cuts both ways. The effective filing date is contested between 2007-06-01 (front page / Google Patents) and 2008-06-02 (Micron's position, adopted in the FWD's analysis). Any § 102(e) reliance on A12, A13 or Best depends on that outcome; only Best's provisional date (2007-04-17) survives either way.
- The Google Patents "Prior art keywords" (volatile memory, memory subsystem, memory system, subsystem, data) are machine-generated index tags and are not a legal prior-art listing.
Verify at: USPTO Patent Center (patentcenter.uspto.gov) for the '833's front page and "References Cited"; PTAB E2E or https://patents.google.com/patent/US8301833B1/en#legal-events for the IPR papers; and the FWD at https://storage.courtlistener.com/recap/gov.uscourts.txed.215248/gov.uscourts.txed.215248.286.7.pdf.
Generated 9/24/2026, 11:23:03 PM
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
I'll start by gathering the actual prior-art references cited on this patent and any IPR records that identify prior art against it.
Let me pull the actual claim language and the PTAB's final written decision details so the analysis is grounded.
I have the PTAB record. Now let me verify the individual references listed in the patent's own Prior Art/References Cited section so I can map them accurately.
Obviousness Analysis — U.S. Patent No. 8,301,833 ("Non-Volatile Memory Module")
Prepared: April 26, 2026 · Basis: face-of-patent prior art (References Cited) and the PTAB record
1. Framework
| Item | Value |
|---|---|
| Patent | US 8,301,833 B1 (Chen et al.), granted Oct. 30, 2012 |
| App. No. / Filing date | 12/240,916 / Sept. 29, 2008 |
| Priority claim | Continuation of 12/131,873 (June 2, 2008); benefit of Prov. 60/941,586 (June 1, 2007) |
| Governing statute | Pre-AIA 35 U.S.C. § 103(a) (application filed before Mar. 16, 2013) — confirmed at IPR2022-00418 FWD, n.2 |
| Claims | 30 total; claims 1 and 15 independent; claims 3–14, 16–17, 19–30 dependent; claims 2 and 18 not challenged in IPR |
| Record outcome | All challenged claims held unpatentable under § 103(a) over Best + Bonella + Mills (IPR2022-00418, FWD entered Aug. 28, 2023) |
Effective filing date caution. Google Patents lists a 2007-06-01 prior art date, but the Petitioner showed the '586 provisional (Ex. 1005) does not contain the words "clock" or "frequency," and therefore does not provide written description for the claimed first/second/third clock frequencies. The effective date for the claims is no earlier than June 2, 2008. This matters for § 102(e) status of certain references, as flagged below.
POSITA (as adopted by the Board): a bachelor's degree in materials science, electrical engineering, computer engineering, computer science or a related field, plus at least one year of experience with the design/development of semiconductor non-volatile memory circuitry or systems. (FWD, Paper 30, pp. 7–8)
Claim construction: "clock frequency" = "identification of a clock running at a particular frequency" (IPR2014-00994, Paper 8 at 6). "First/second mode of operation" was not construed narrowly — the Board refused Patent Owner's attempt to import the isolation-switch embodiments, holding the plain claim language governs (FWD pp. 11–21).
2. What the independent claims actually require (claim 15, reproduced verbatim in the FWD)
15. A memory system operatively coupled to a host system, the memory system comprising:
- a volatile memory subsystem operable at a first clock frequency when the memory system is in a first mode of operation in which data is communicated between the volatile memory subsystem and the host system;
- and a non-volatile memory subsystem operable at a second clock frequency when the memory system is in a second mode of operation in which data is communicated between the volatile memory subsystem and the nonvolatile memory subsystem,
- the volatile memory subsystem further being operable at a third clock frequency when the memory system is in the second mode of operation, the third clock frequency being less than the first clock frequency.
Claim 1 is the method counterpart (operate volatile at first freq. in first mode; operate non-volatile at second freq. in second mode; operate volatile at third freq. < first freq. in second mode). Id. at 5.
Claim 2/18 (the only claims never challenged) add that the third frequency is "substantially" equal to the second. Note the prosecution history: the Examiner originally rejected these as indefinite for "approximately equal," and Netlist amended to "substantially" while conceding "in practice there will always be a difference."
3. Ground I — Best + Bonella + Mills (the combination adjudicated unpatentable)
3.1 The references
| Short name | Citation | Status | Disclosure relied on |
|---|---|---|---|
| Best | US 2010/0110748 A1 (pub. May 6, 2010) | § 102(e) via Prov. 60/912,321 (filed Apr. 17, 2007) | Composite hybrid memory device: DRAM die + Flash die in one IC package; shared interface circuit steering host commands to either die; "shadow operation" (backup/mirroring) and non-overlapping address-range modes |
| Bonella | US 2007/0136523 A1 (pub. June 14, 2007); prov. 11/635,926 filed Dec. 8, 2005 | § 102(e) | Hybrid DRAM + Flash module with module controller; DRAM write-buffer flush to Flash on power loss; "power loss algorithm"; UPS capacitors as backup power; "Power State Aware" levels, incl. Power Level 4 limiting DRAM performance / reducing DRAM operating frequency for "major power savings" |
| Mills | US 6,026,465 (issued Feb. 15, 2000) | § 102(b) | Synchronous Flash Interface (SFI) — flash memory clocked from an external clock input; all external operations synchronized to a clock edge; internal bank interleaving |
3.2 Limitation-by-limitation
| Claim 15 limitation | Best | Bonella | Mills |
|---|---|---|---|
| Preamble: memory system coupled to host | ✔ Fig. 1A, external control/data path ("host") | ✔ Fig. 1, module + host interface | — |
| Volatile memory subsystem, 1st clock freq., 1st mode (volatile↔host) | ✔ DRAM die 103 via shared interface 105; host-directed accesses at DDR2 rates | ✔ "Power Level 5" full-performance DRAM operation | — |
| Non-volatile memory subsystem, 2nd clock freq., 2nd mode (volatile↔NVM) | ✔ Flash die 101; shared interface conveys read/write data between dice (shadow/backup) | ✔ DRAM write-buffer flush to Flash under power-loss algorithm | ✔ supplies the clocked non-volatile interface (SFI) → "second clock frequency" |
| Volatile operable at 3rd freq. < 1st freq., in 2nd mode | — | ✔ Power Level 4 limits/reduces DRAM performance; slowing DRAM frequency gives "major power savings" | — |
3.3 Motivation to combine (the key § 103 question)
The Board's reasoning tracks four independently sufficient KSR rationales:
- Same field, same problem. Best, Bonella and Mills all address hybrid DRAM/Flash memory systems for computers and servers. Best provides the architecture; Mills supplies the clocked-NVM technique; Bonella supplies the trigger-driven backup and the reduced-frequency power-saving mode. Nothing in any reference teaches away from the others.
- Express motivation within Bonella. Bonella states the rationale for the third-frequency limitation in terms an artisan would immediately grasp: during a power-loss backup the module runs on a finite reserve ("the memory maintains a sufficiently large power reserve to write the data to Flash memory," ¶[0033]). Slowing the DRAM during that window (¶¶[0048]–[0050]) directly extends how much data can be flushed on the remaining reserve. That is a classic "discover the source of the problem and apply the known remedy" rationale.
- Known technique / predictable variation. Best's shared interface conveys data between the DRAM and Flash dice; to clock the Flash side, one of ordinary skill would use the well-known synchronous-flash interface of Mills — a predictable substitution requiring no change in principle of operation. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 416–17, 421 (2007).
- Reasonable expectation of success. Both DDR DRAM clock scaling and clocked NAND/NOR interfaces were routine by 2008 (the record cites JEDEC JESD79/JESD79-2B and Intel StrataFlash documentation, Pet. Exs. 1017–1019), so the artisan would expect the combination to work without undue experimentation.
3.4 Corroboration that this combination is not merely arguable
- IPR2017-00692 (SK hynix), FWD July 5, 2018 invalidated claim 15 of U.S. 8,874,831 — the continuation-in-part of the '916 application, reciting claim 15 "almost verbatim" — as obvious over Best, Mills, Bonella.
- IPR2022-00418 (Micron), FWD Aug. 28, 2023 held claims 1, 3–17, 19–30 of the '833 patent unpatentable over the same three references. (Judgment; Petition)
4. Ground II — The patent's own Prior Art section: Li + (Oshikiri / Cope) + a frequency reference
The face of the patent lists the following "Domestic Patent References" (SumoBrain record; see also Ex. 1089 in PGR2026-00001):
| Ref. | Title | Relevance |
|---|---|---|
| 4,420,821 / 4,449,205 Hoffman | Static/Dynamic RAM with non-volatile back-up storage | DRAM + NV back-up; restore on power-up |
| 5,519,663 Harper, Jr. et al. | Preservation system for volatile memory with nonvolatile backup memory | Volatile/NV backup subsystem |
| 6,336,174 Li et al. | Hardware assisted memory backup system and method (Maxtor) | Trigger-event detection (power failure, OS hang-up, unexpected reset), electrical isolation of the module from the host, auxiliary power source, controller copying volatile→nonvolatile and restoring back; explicit write-cache/early-acknowledge rationale |
| 6,336,176 Leyda et al. | Memory configuration data protection | NV retention of memory config |
| 6,799,244 Tanaka et al. | Storage control unit with a volatile cache and a non-volatile backup cache | Volatile cache + NV backup cache for read/write processing |
| 7,409,590 Moshayedi et al. | Protection against data corruption due to power failure in solid-state memory device | Power-fail protection in solid-state memory |
| 2004/0190210 Leete | Memory back up and content preservation | Volatile memory backup/preservation |
| 2002/0083368 Abe et al. | Computer system … and its memory management method | Memory management across modes |
| 2007/0192627 Oshikiri | Semiconductor memory and data access method (713/191) | Examiner-applied; mode-dependent memory operation |
| 2008/0195806 Cope | System and method for controlling memory operations (711/111) | Examiner-applied; memory operation control |
Prosecution history is decisive here. Netlist's claims were rejected twice on this art: first over Li + Oshikiri, then over Li + Cope. (Petition, § III.D) The only thing that distinguished the claims was the first/second/third clock frequency recitation. That means:
- Li alone supplies: a memory module coupled to a host; a volatile memory subsystem; a non-volatile memory subsystem; a controller moving data between them; host-coupled operation; trigger-driven backup mode; isolation of the volatile memory from the host during backup; and even the auxiliary (non-host) power source. Claims 1/15's architectural features are squarely met.
- The single gap is "operable at a first/second/third clock frequency." That gap is closed by (a) Bonella, ¶¶[0048]–[0050] (explicitly reducing DRAM operating frequency), or (b) the admitted state of the art that synchronous DRAM operates at a defined clock frequency and Mills supplies a clocked non-volatile interface, or (c) the JEDEC/clocking disclosures of record.
Combination proposed: Li (Ex. 6,336,174) in view of Bonella (or, in the alternative, Oshikiri or Cope) and Mills — or Li + Moshayedi + Bonella if a secondary power-failure reference is desired. The motivation is straightforward: Li addresses what to do (detect a trigger, isolate, copy to NV on auxiliary power); Bonella teaches why and how to economize during that window (reduce DRAM frequency for "major power savings" on a finite reserve); Mills supplies the known clocked non-volatile interface. The claimed subject matter is therefore also obvious on the patent's own cited art.
§ 102(e) timing caveat. Oshikiri (pub. Aug. 16, 2007) and Cope (pub. Aug. 14, 2008) post-date the claimed June 1, 2007 priority date. They qualify as pre-AIA § 102(e) art only if their US filing dates precede the claims' effective date (which the Petitioner argued is June 2, 2008). I did not independently verify their filing dates; the Examiner's reliance on them during prosecution suggests they were treated as qualifying art. Best (via Prov. 60/912,321, Apr. 17, 2007) qualifies regardless of how the priority question resolves, which is why Ground I is the more robust theory.
5. Dependent claims
- Claim 16 (decoupling the volatile memory subsystem / controller) — met by Li's express "electrically isolating the hardware assisted memory module from the host computer system," and by Harper, Hoffman, and Best's steering/shared-interface circuitry. The Board also noted claim 16's "decouple from" language is narrower than the independent-claim language.
- Claims 3–14, 17, 19–30 — the Petitioner characterized these as reciting "well-known components and features … included in commonplace memory systems well prior to the '833 Patent's priority date," and the Board agreed, invalidating all of them. I was unable to verify the individual text of claims 3–14, 17 and 19–30 from the retrieved sources; my conclusion as to those claims rests on the Board's adjudication, not on an independent element-by-element reading.
- Claims 2 and 18 — never challenged. As of the FWD they stand, unpatentability of the remaining claims notwithstanding.
6. Secondary considerations
No objective evidence of non-obviousness was credited. Netlist argued only claim construction (a narrow "first/second mode of operation"); it did not prevail, and the Board's FWD does not identify any evidence of unexpected results, industry praise, copying, licensing nexus, or long-felt need tied to the first/second/third-frequency limitations. The patent's own specification contains admissions that cut the other way: batteries were already "used to provide power to volatile memory during power failures," non-volatile memory was already known for backup, and the patent expressly states its descriptions "are intended to be illustrative … and are not intended to be limiting" (20:64–67).
7. Bottom line
| Ground | Combination | Claims | Strength |
|---|---|---|---|
| I | Best + Bonella + Mills | 1, 3–17, 19–30 | Adjudicated unpatentable (IPR2022-00418 FWD); same combination invalidated the near-identical claim 15 of the '831 patent in IPR2017-00692 |
| II | Li + Bonella (or Oshikiri/Cope) + Mills | 1, 3–17, 19–30 | Strong; mirrors the Examiner's own twice-made rejection, with the frequency limitation supplied by Bonella/Mills |
| III | Li + Moshayedi/Leete/Tanaka + Bonella | 1, 15, and most dependents | Strong on the backup/restore, isolation and trigger-detection elements |
The single point of novelty the patentee preserved — a volatile memory subsystem operated at a third, lower clock frequency during the backup/restore mode — is disclosed almost verbatim by Bonella's Power-State-Aware reduced-DRAM-frequency mode, aimed at exactly the same purpose (conserving limited backup energy). Under KSR, that is a predictable application of a known technique to a known system, with an express motivation in the prior art.
8. Caveats and open items
- I verified the text of claim 15 (quoted in the FWD) and the substance of claim 1 (as described in the Petition). The full text of claims 3–14, 17 and 19–30 was not in my retrieved sources.
- The Google Patents page's "Prior art keywords" (volatile memory, memory subsystem, memory system, subsystem, data) are machine-generated index tags, not a legal prior-art listing; the substantive list is the References Cited table above.
- Google Patents shows the patent "Active, expires 2030-03-02," but claims 1, 3–17 and 19–30 have been held unpatentable at the PTAB and the family is on appeal (CAFC No. 24-2282). Validity status should be treated as unsettled pending appellate resolution.
- I did not independently verify the filing dates, and thus the exact § 102(e) dates, of Oshikori 2007/0192627 and Cope 2008/0195806, nor the full disclosures of Abe, Leete, Emerson, Chan, Klein, Leyda or Tanaka beyond their titles/relevance summaries.
Generated 9/15/2026, 12:47:38 PM
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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