US 9929240

An analysis of US Patent No. 9,929,240 is provided below.

Patent Information

• Title: Memory transistor with multiple charge storing layers and a high work function gate electrode
• Assignee: The original assignee was Cypress Semiconductor Corp. As of May 4, 2019, the patent was assigned to Longitude Flash Memory Solutions Ltd.
• Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
• Filing Date: October 26, 2016
• Issue Date: March 27, 2018
• Abstract: "An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride."

Plain-Language Summary of Independent Claims

This patent describes a non-volatile memory transistor designed for improved data retention and performance. The key innovation lies in the specific structure of the charge-trapping layer within the transistor's gate stack. The independent claims define the core features of this invention.

• Independent Claim 1: This claim describes a memory device with a specific multi-layer charge trapping structure. The structure is built on a semiconductor substrate and includes a channel, a source, and a drain. The gate stack, which controls the flow of current in the channel, consists of several layers: a tunnel dielectric, a multi-layer charge trapping region, a blocking dielectric, and a high work function gate electrode. The novelty is in the multi-layer charge trapping region, which has three distinct sub-layers:

  1. An "oxygen-rich" first nitride layer.
  2. An "anti-tunneling" oxide layer on top of the first nitride layer.
  3. An "oxygen-lean" second nitride layer on top of the anti-tunneling layer.

  This unique "oxide-nitride-nitride-oxide" (ONNO) structure, particularly the anti-tunneling layer between two different nitride layers, is designed to improve how the transistor stores charge, leading to better data retention.

• Independent Claim 13: This claim outlines a method for manufacturing the memory device described in claim 1. The process involves sequentially forming the specialized layers of the gate stack. Key steps include:

  1. Forming a tunnel dielectric layer on a substrate.
  2. Depositing an oxygen-rich first nitride layer.
  3. Forming an anti-tunneling oxide layer on the first nitride layer.
  4. Depositing an oxygen-lean second nitride layer on the anti-tunneling layer.
  5. Forming a blocking dielectric layer on top.
  6. Finally, forming a high work function gate electrode over the entire stack.

  This method details the specific sequence of fabrication steps required to create the novel multi-layer charge trapping structure.

• Independent Claim 18: This claim describes another version of the memory device, focusing on the composition of the different layers. It specifies that the multi-layer charge-trapping region is made of a first silicon oxynitride layer (oxygen-rich) and a second silicon oxynitride layer (oxygen-lean), separated by an anti-tunneling oxide layer. It also specifies that the high work function gate electrode is made of doped polysilicon, making it compatible with standard CMOS manufacturing processes. This claim emphasizes the material composition and its integration with existing semiconductor manufacturing technology.