US 9929240

An analysis of US Patent No. 9,929,240 is provided below.

Patent Information

• Title: Memory transistor with multiple charge storing layers and a high work function gate electrode
• Assignee: The original assignee was Cypress Semiconductor Corp. As of May 4, 2019, the patent was assigned to Longitude Flash Memory Solutions Ltd.
• Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
• Filing Date: October 26, 2016
• Issue Date: March 27, 2018
• Abstract: "An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride."

Plain-Language Summary of Independent Claims

This patent describes a non-volatile memory transistor designed for improved data retention and performance. The key innovation lies in the specific structure of the charge-trapping layer within the transistor's gate stack. The independent claims define the core features of this invention.

• Independent Claim 1: This claim describes a memory device with a specific multi-layer charge trapping structure. The structure is built on a semiconductor substrate and includes a channel, a source, and a drain. The gate stack, which controls the flow of current in the channel, consists of several layers: a tunnel dielectric, a multi-layer charge trapping region, a blocking dielectric, and a high work function gate electrode. The novelty is in the multi-layer charge trapping region, which has three distinct sub-layers:

  1. An "oxygen-rich" first nitride layer.
  2. An "anti-tunneling" oxide layer on top of the first nitride layer.
  3. An "oxygen-lean" second nitride layer on top of the anti-tunneling layer.

  This unique "oxide-nitride-nitride-oxide" (ONNO) structure, particularly the anti-tunneling layer between two different nitride layers, is designed to improve how the transistor stores charge, leading to better data retention.

• Independent Claim 13: This claim outlines a method for manufacturing the memory device described in claim 1. The process involves sequentially forming the specialized layers of the gate stack. Key steps include:

  1. Forming a tunnel dielectric layer on a substrate.
  2. Depositing an oxygen-rich first nitride layer.
  3. Forming an anti-tunneling oxide layer on the first nitride layer.
  4. Depositing an oxygen-lean second nitride layer on the anti-tunneling layer.
  5. Forming a blocking dielectric layer on top.
  6. Finally, forming a high work function gate electrode over the entire stack.

  This method details the specific sequence of fabrication steps required to create the novel multi-layer charge trapping structure.

• Independent Claim 18: This claim describes another version of the memory device, focusing on the composition of the different layers. It specifies that the multi-layer charge-trapping region is made of a first silicon oxynitride layer (oxygen-rich) and a second silicon oxynitride layer (oxygen-lean), separated by an anti-tunneling oxide layer. It also specifies that the high work function gate electrode is made of doped polysilicon, making it compatible with standard CMOS manufacturing processes. This claim emphasizes the material composition and its integration with existing semiconductor manufacturing technology.

As of April 26, 2026, United States Patent No. 9,929,240 is the subject of ongoing litigation. The patent, assigned to Longitude Flash Memory Solutions, Ltd., is involved in multiple legal actions, including district court lawsuits and a proceeding before the Patent Trial and Appeal Board (PTAB).

District Court Litigation

Case 1: California Central District Court

• Plaintiff(s): IPValue Management, Inc. and Longitude Flash Memory Solutions, Ltd.
• Defendant(s): Western Digital Corporation and SanDisk Corporation.
• Jurisdiction: U.S. District Court for the Central District of California.
• Case Number: 8:25-cv-00119.
• Filing Date: January 22, 2025.
• Status: The case is currently active. The most recent docket entry indicates a stipulation of dismissal was filed, suggesting a potential settlement between the parties.

Case 2: California Northern District Court

• Plaintiff(s): SanDisk Corporation.
• Defendant(s): IPValue Management, Inc. and Longitude Flash Memory Solutions, Ltd.
• Jurisdiction: U.S. District Court for the Northern District of California.
• Case Number: 5:25-cv-02389.
• Filing Date: March 7, 2025.
• Status: This case is also active. IPValue Management and Longitude Flash Memory Solutions have filed counterclaims for infringement of five patents, including the '505 patent. A motion to dismiss the counterclaim concerning U.S. Patent No. 6,963,505 was denied. A stipulation of dismissal was also filed in this case, pointing towards a likely resolution.

Patent Trial and Appeal Board (PTAB) Proceeding

• Case Number: IPR2025-01283
• Parties: Details of the petitioner and patent owner are not fully available in the provided search snippets. However, related PTAB proceedings involving Longitude Flash Memory Solutions Ltd. and SanDisk Technologies, Inc. (IPR2025-01281) have been identified.
• Status: A settlement has been reached in this inter partes review.

In a related development, IPValue Management, Inc. announced on January 19, 2026, that its affiliate, Longitude Flash Memory Solutions, Ltd., has granted a worldwide, non-exclusive patent license to SanDisk Corporation for a portfolio of patents originating from Cypress Semiconductor. This agreement resolved all outstanding patent disputes between the companies, which likely includes the aforementioned litigation.

Based on the single inter partes review (IPR) filed against U.S. Patent No. 9,929,240, the patent's claims remain legally intact, as the proceeding was terminated through a settlement before the Patent Trial and Appeal Board (PTAB) could rule on the merits of the challenge. This posture means that while the patent has been challenged, its validity has not been affirmed or denied by the PTAB, leaving it vulnerable to future validity challenges in court or at the USPTO.

IPR2025-01283 — Sandisk Technologies, Inc. et al. v. Longitude Flash Memory Solutions Ltd.

• Type: Inter Partes Review
• Filed: 2025-10-14
• Status: Terminated-Settled (as of 2026-02-20). This means the petitioner and patent owner reached a mutual agreement to end the proceeding before the PTAB issued a Final Written Decision.
• Judge Panel: Information on the Administrative Patent Judge (APJ) panel is not publicly available as the case was terminated before the institution phase, where the panel is typically identified.
• Petition Grounds: The petition for IPR has not been made publicly available yet, so the specific claims challenged and the prior art asserted are not known at this time. Typically, IPRs are based on grounds of anticipation (§ 102) or obviousness (§ 103) using prior art patents and printed publications.
• Institution Decision: The proceeding was terminated on 2026-02-20, approximately four months after the petition was filed. This is before the PTAB's deadline to issue a decision on whether to institute a trial. Therefore, the Board never made a determination on the merits of the petitioner's arguments.
• Final Written Decision: No Final Written Decision was issued because the proceeding was terminated.
• Settlement / Termination: The parties filed a joint motion to terminate the proceeding due to settlement. The terms of such agreements are almost always confidential.
• Appeal: There was no Final Written Decision, so no appeal to the U.S. Court of Appeals for the Federal Circuit was possible.
• Defensive Value: This proceeding offers significant value to a potential defendant. The fact that a well-funded entity like Sandisk invested in filing an IPR suggests they identified potentially strong invalidity arguments. Although the case settled, the IPR petition itself (once available) will serve as a detailed roadmap of prior art and invalidity contentions that can be used by others. Because the case was terminated before a final decision, no statutory estoppel applies to Sandisk or any other party.

Strategic Summary

• Claim Status: All claims of U.S. Patent No. 9,929,240 remain valid and enforceable. No claims are CANCELED or have been finally adjudicated as patentable by the PTAB. All claims are currently UNTESTED in an AIA trial.
• Estoppel Landscape: Critically for any future defendant, no estoppel under 35 U.S.C. § 315(e) attaches from this proceeding. Estoppel only applies to a petitioner after a Final Written Decision is issued. This means that another party is free to file a new IPR using the same (or different) grounds and prior art. The petitioner, Sandisk, could even file a new IPR on different grounds.
• Pattern Signals: The patent is owned by Longitude Flash Memory Solutions Ltd., which is a known patent assertion entity. The settlement with Sandisk follows a common pattern where a validity challenge at the PTAB pressures the patent owner into a license agreement. The short time between filing and settlement suggests the patent owner may have been keen to avoid a PTAB decision on the merits, which could be a signal of perceived weakness in the patent's validity.

Recommended Next Steps

• Obtain the IPR File Wrapper: The most critical next step for any defendant is to obtain the complete file for IPR2025-01283 from the USPTO's PTAB E2E portal. The petition document, though not yet publicly indexed, will contain a full analysis of the patent claims and the prior art that Sandisk believed rendered them invalid. This is an invaluable, pre-packaged starting point for your own invalidity defense.
• Analyze the Asserted Prior Art: Once the petition is obtained, a thorough analysis of the prior art and arguments raised by Sandisk is necessary. This will inform your own non-infringement and invalidity contentions and help assess the overall strength of the patent.
• Monitor for Future Litigation/PTAB Challenges: Given that the patent is held by an assertion entity and the first IPR settled, it is likely that U.S. Patent No. 9,929,240 will be asserted against others. Monitor litigation and PTAB dockets for new cases, as other defendants may also challenge the patent's validity.

An analysis of the ownership and assignment history of US Patent No. 9,929,240 is provided below.

Inventors

• Igor Polishchuk: At the time of filing, Mr. Polishchuk was a Senior Principal at Cypress Semiconductor.
• Sagy Charel Levy: At the time of filing, Mr. Levy was a Senior R&D Manager at Cypress Semiconductor.
• Krishnaswamy Ramkumar: At the time of filing, Dr. Ramkumar was Vice President of Process Technology R&D at Cypress Semiconductor.

All inventors were employees of the original assignee, Cypress Semiconductor, at the time of the invention. There are no indications of unusual employment patterns, such as mass departures, preceding or following the patent application.

Original assignee

The original assignee of the patent is Cypress Semiconductor Corporation. Cypress was a publicly-traded American semiconductor design and manufacturing company. Its primary business involved developing and selling a wide range of microcontrollers, wireless and USB connectivity solutions, and, notably, specialized memory products. The technology described in this patent, a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) non-volatile memory transistor, was a core component of Cypress's proprietary flash memory portfolio, which it commercialized in numerous products for the automotive, industrial, and consumer markets.

In April 2020, Cypress Semiconductor was acquired by Infineon Technologies AG. Cypress now operates as a subsidiary of Infineon.

Assignment timeline

• 2016-11-21 (executed) / recorded 2016-11-21 — Reel 039981/0955

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Igor Polishchuk; Sagy Charel Levy; Krishnaswamy Ramkumar
  • Assignee: Cypress Semiconductor Corporation
  • Correspondent: Joseph P. Beck, DLA Piper LLP (US), 2000 University Avenue, East Palo Alto, CA 94303
  • Context: Routine assignment from inventors to their employer, securing corporate ownership of the invention.

• 2017-04-18 (executed) / recorded 2017-04-25 — Reel 041219/0814

  • Conveyance: Patent Security Agreement
  • Assignor: Cypress Semiconductor Corporation; Spansion LLC
  • Assignee: Morgan Stanley Senior Funding, Inc., as Collateral Agent
  • Correspondent: Michael T. Ciaschini, Pillsbury Winthrop Shaw Pittman LLP, 1200 Seventeenth Street, N.W., Washington, DC 20036
  • Context: The patent, along with other intellectual property, was pledged as collateral to secure a financing arrangement, a standard corporate practice.

• 2019-04-12 (executed) / recorded 2019-05-07 — Reel 048792/0664

  • Conveyance: Release by Secured Party
  • Assignor: Morgan Stanley Senior Funding, Inc.
  • Assignee: Cypress Semiconductor Corporation; Spansion LLC
  • Correspondent: Michael T. Ciaschini, Pillsbury Winthrop Shaw Pittman LLP, 1200 Seventeenth Street, N.W., Washington, DC 20036 (Same correspondent as the security agreement)
  • Context: Morgan Stanley released its security interest in the patent, returning full rights to Cypress Semiconductor, likely upon satisfaction of the associated loan or financing.

• 2019-05-01 (executed) / recorded 2019-05-04 — Reel 048771/0212

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Cypress Semiconductor Corporation
  • Assignee: Longitude Flash Memory Solutions Ltd.
  • Correspondent: Hariklia K. Karis, Karis IP Law, 1000 N. West Street, Suite 1200, Wilmington, DE 19801
  • Context: Transfer of the patent from the original operating company to a newly formed entity, Longitude Flash Memory Solutions Ltd.

Timeline diagram

timeline
    title Ownership of US 9,929,240
    2016 : Application Filed
         : Inventors assign to Cypress
    2017 : Pledged as collateral to Morgan Stanley
    2018 : Patent Issued
    2019 : Security interest released by Morgan Stanley
         : Assigned to Longitude Flash Memory Solutions Ltd.
    2025 : Litigation filed vs NXP, STMicroelectronics, and Qualcomm

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from Cypress Semiconductor, an operating company, to Longitude Flash Memory Solutions Ltd. [cite: Reel 048771/0212]. Research from public sources, including litigation databases, indicates Longitude is an intellectual property holding company that does not manufacture products. It was formed shortly before receiving this and other patents from Cypress.

2. Known asserter in the chain — Present. Longitude Flash Memory Solutions Ltd., the current assignee, is identified as a patent assertion entity. Unified Patents has documented litigation initiated by Longitude asserting this patent against multiple technology companies, including NXP, STMicroelectronics, and Qualcomm.

3. Repeat correspondent across the chain — Not present. The correspondent for the initial assignment (DLA Piper) and the security agreement (Pillsbury) are large law firms representing operating companies. The correspondent for the transfer to the assertion entity (Karis IP Law) is different.

4. Cascading transfers — Not present. The assignment history shows a clear transfer from the original assignee to a single subsequent assignee for assertion purposes, not a complex chain of transfers.

5. Pre-litigation transfer — Present. The patent was assigned to Longitude Flash Memory Solutions Ltd. on May 1, 2019. Longitude subsequently initiated litigation asserting this patent. For example, cases against NXP, STMicroelectronics, and Qualcomm were filed in early 2025. This transfer appears to have been made to facilitate an assertion campaign.

6. Bankruptcy fire-sale — Not present. The transfer was part of a strategic sale of assets from Cypress Semiconductor, not a bankruptcy proceeding.

7. Privateering — Unclear. This transfer exhibits characteristics of privateering, where an operating company (Cypress/Infineon) divests patents to a third-party NPE (Longitude) to assert against its competitors. While the relationship between Infineon and Longitude is not publicly detailed, the pattern is consistent with a privateering model. However, without a definitive contractual link, this remains an inference.

8. Defensive aggregator (anti-NPE) — Not present. The patent is held by an assertion entity, not a defensive aggregator.

Verdict

NPE — high confidence

The patent was transferred from its original creator, Cypress Semiconductor, to Longitude Flash Memory Solutions Ltd., an entity that does not appear to produce products. [cite: Reel 048771/0212] Longitude has since engaged in litigation, asserting this patent against major semiconductor companies. This pattern of an operating company transferring a patent to a non-practicing entity which then launches an assertion campaign is a strong indicator of NPE activity.

Verify assignment records at the USPTO Patent Assignment Search by searching for Patent Number 9929240.

Analysis of Prior Art for U.S. Patent No. 9,929,240

A critical aspect of patent analysis involves examining the prior art cited during the patent's prosecution and in any subsequent legal challenges. This analysis determines whether the invention claimed in the patent was already known and therefore not novel. Under U.S. patent law, specifically 35 U.S.C. § 102, a patent claim is invalid if every element of that claim is present in a single prior art reference. This is known as "anticipation." What follows is an assessment of the most relevant prior art references cited for U.S. Patent No. 9,929,240, focusing on their potential to anticipate the independent claims.

Key Concepts in the '240 Patent

The core of the invention in the '240 patent is a specific multi-layer charge-trapping structure within a non-volatile memory transistor. The key features, as detailed in the independent claims, are:

• A multi-layer charge trapping region: This is the heart of the invention.
• Three specific sub-layers:
  1. An "oxygen-rich" nitride layer (also referred to as silicon oxynitride).
  2. An "anti-tunneling" oxide layer situated on top of the first nitride layer.
  3. An "oxygen-lean" nitride layer (or silicon oxynitride) on top of the anti-tunneling layer.
• High work function gate electrode: This is typically made of doped polysilicon.
• Overall structure: This creates what the patent refers to as an "oxide-nitride-nitride-oxide" (ONNO) or "oxide-nitride-oxide-nitride-oxide" (ONONO) stack when including the tunnel and blocking dielectrics.

Analysis of Prior Art References

The following patents and patent applications were cited as relevant prior art during the prosecution of the '240 patent. Each is evaluated for its potential to anticipate the independent claims (1, 13, and 18) of the '240 patent.

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1. U.S. Patent No. 7,494,863 B2

• Full Citation: US 7,494,863 B2, "Method for manufacturing a non-volatile memory," issued to Macronix International Co., Ltd.
• Publication Date: February 24, 2009 (Filed: January 18, 2007).
• Brief Description: This patent describes a method of fabricating a non-volatile memory device with a charge-trapping layer. It focuses on a process to form a charge-trapping structure with a high-K dielectric material. The structure involves a tunnel oxide, a silicon nitride charge-trapping layer, and a high-K dielectric blocking layer.
• Potential Anticipation Analysis:
  • Does it disclose the key features? The '863 patent discloses a multi-layer gate stack for a charge-trapping memory device. However, it does not explicitly describe the specific three-layer structure of an oxygen-rich nitride layer, an anti-tunneling oxide, and an oxygen-lean nitride layer as required by the '240 patent's claims. While it teaches the use of silicon nitride and high-K dielectrics, it does not detail the specific compositional variations (oxygen-rich vs. oxygen-lean) or the insertion of an "anti-tunneling" oxide layer between two distinct nitride layers.
  • Conclusion: The '863 patent is relevant background art but does not appear to anticipate the claims of the '240 patent. It lacks the specific "arranged as in the claim" structure of the multi-layer charge trapping region, which is a crucial limitation.

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2. U.S. Patent No. 7,569,899 B2

• Full Citation: US 7,569,899 B2, "Non-volatile memory device and method of fabricating the same," issued to [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)
• Publication Date: August 4, 2009 (Filed: November 1, 2007).
• Brief Description: This patent details a non-volatile memory device that uses a charge trap layer with silicon nanocrystals embedded within a silicon nitride layer. The goal is to enhance charge trapping efficiency and data retention. The structure includes a tunneling insulating layer, a charge trap layer, and a blocking insulating layer.
• Potential Anticipation Analysis:
  • Does it disclose the key features? The '899 patent focuses on using silicon nanocrystals to improve the charge-trapping layer. It does not teach the specific layered structure of an oxygen-rich nitride, an anti-tunneling oxide, and an oxygen-lean nitride. The mechanism for charge storage is different, relying on the nanocrystals rather than the specific interfaces and compositions of the multi-layer nitride structure in the '240 patent.
  • Conclusion: The '899 patent does not anticipate the claims of the '240 patent as it describes a different type of charge-trapping layer technology.

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3. U.S. Patent No. 7,700,427 B2

• Full Citation: US 7,700,427 B2, "Method of forming a non-volatile memory device," issued to Powerchip Semiconductor Corp.
• Publication Date: April 20, 2010 (Filed: April 11, 2008).
• Brief Description: This patent describes a method for forming a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type memory device. The process involves creating a charge trapping layer and then performing a thermal oxidation process to form a blocking oxide. The focus is on improving the quality of the interfaces between the layers.
• Potential Anticipation Analysis:
  • Does it disclose the key features? The '427 patent describes a standard ONO (Oxide-Nitride-Oxide) stack. It does not disclose the '240 patent's novel three-layer charge-trapping region with an oxygen-rich nitride, an anti-tunneling oxide, and an oxygen-lean nitride. The fundamental structure of the charge-trapping region is different.
  • Conclusion: The '427 patent is related as it deals with SONOS-type memory, but it does not disclose the specific multi-layer charge-trapping structure and therefore does not anticipate the claims of the '240 patent.

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4. U.S. Patent No. 8,633,537 B2

• Full Citation: US 8,633,537 B2, "Memory transistor with multiple charge storing layers and a high work function gate electrode," issued to Cypress Semiconductor Corporation.
• Publication Date: January 21, 2014 (Filed: July 1, 2012).
• Brief Description: This patent is a direct parent to the '240 patent in the same family, sharing the same title and inventors. It describes the same core invention of a memory transistor with a multi-layer charge trapping region, including an oxygen-rich nitride layer, an oxygen-lean nitride layer, and potentially an anti-tunneling layer.
• Potential Anticipation Analysis:
  • Does it disclose the key features? As a parent patent in the same family, it discloses the same inventive concept. However, under 35 U.S.C. § 102, a patent cannot be anticipated by its own parent application from which it claims priority. This reference is part of the claimed invention's lineage, not prior art against it in the traditional sense for an anticipation rejection. It is cited for informational and continuity purposes.
  • Conclusion: The '537 patent does not anticipate the '240 patent because it is part of the same patent family and does not predate the effective filing date.

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5. U.S. Patent Application Publication No. US 2007/0096194 A1

• Full Citation: US 2007/0096194 A1, "Nonvolatile semiconductor memory device," by artist: Lue.
• Publication Date: May 3, 2007 (Filed: October 31, 2005).
• Brief Description: This publication describes a non-volatile memory device with a charge-trapping structure that includes a "band-engineered" silicon nitride layer. The idea is to have different compositions within the nitride layer to create potential wells for more effective charge trapping.
• Potential Anticipation Analysis:
  • Does it disclose the key features? This reference comes conceptually close. It discusses varying the composition of the nitride layer to improve performance. However, it does not explicitly disclose the specific three-layer structure of an "oxygen-rich" nitride, a distinct "anti-tunneling" oxide layer, and an "oxygen-lean" nitride. While it mentions varying silicon and nitrogen ratios, the inclusion of the central oxide layer as a distinct anti-tunneling barrier between the two nitride layers is a key element of the '240 patent's claims that appears to be absent here.
  • Conclusion: This is likely the most relevant prior art. While it discusses the general concept of a non-uniform charge trapping layer, it does not appear to explicitly teach all the elements of the '240 patent's independent claims in a single embodiment, particularly the distinct anti-tunneling oxide layer. Therefore, it would likely not be considered to anticipate the claims, although it could be relevant in an obviousness analysis under 35 U.S.C. § 103.

Summary of Prior Art Analysis

The prior art cited for US Patent 9,929,240 primarily relates to non-volatile memory devices with charge-trapping layers. While these references describe various ways to construct and improve such devices, none appear to explicitly disclose the complete combination of elements required by the independent claims of the '240 patent. The key innovation in the '240 patent is the specific three-layer charge-trapping region consisting of an oxygen-rich nitride layer, an anti-tunneling oxide layer, and an oxygen-lean nitride layer. This specific combination is not found in the cited prior art, and therefore, these references do not appear to anticipate the claims of US 9,929,240. An argument for anticipation would require showing that one of these references inherently or expressly discloses every single element of the claimed invention, arranged in the same way. Based on the available information, this seems unlikely.

Analysis of Obviousness for U.S. Patent No. 9,929,240

A person of ordinary skill in the art (POSA) at the time of the invention would have found the claims of U.S. Patent No. 9,929,240 obvious based on a combination of prior art references. The key features of the '240 patent—a multi-layer charge-trapping region with specific oxygen concentrations and an anti-tunneling layer, combined with a high work function gate electrode—are all taught or suggested by the prior art for the predictable purpose of improving memory cell performance, particularly data retention and program/erase efficiency.

Key Elements of the Invention

The independent claims of the '240 patent, particularly Claim 1, describe a memory transistor with a gate stack comprising:

1. A tunnel dielectric layer.
2. A multi-layer charge trapping region which includes:
   • An oxygen-rich first nitride layer.
   • An anti-tunneling oxide layer on top of the first nitride layer.
   • An oxygen-lean second nitride layer on top of the anti-tunneling layer.
3. A blocking dielectric layer.
4. A high work function gate electrode.

The core of the claimed invention is the engineered charge-trapping stack, which is essentially an Oxide-Nitride-Oxide-Nitride-Oxide (ONONO) structure, designed to enhance data retention by creating distinct regions for charge trapping and providing a barrier to prevent charge leakage.

Combination of Prior Art and Motivation to Combine

A strong case for obviousness can be made by combining the teachings of U.S. Patent No. 6,858,480 to Lee et al. (Lee), U.S. Patent No. 7,211,854 to An et al. (An), and the general knowledge in the art regarding high work function gate electrodes for non-volatile memory.

• Lee (US 6,858,480), filed in 2003, teaches a method of fabricating a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory device with an improved charge-trapping layer to enhance data retention. Lee specifically discloses creating a silicon-rich silicon nitride layer. The patent describes varying the gas flow rates during the deposition process to control the silicon-to-nitrogen ratio. This directly addresses the concept of engineering the nitride layer for better charge trapping, which is a central theme in the '240 patent. While Lee does not explicitly describe a dual-layer nitride with an intervening oxide, it establishes the principle of modifying nitride composition to improve memory characteristics.

• An (US 7,211,854), filed in 2005, discloses a non-volatile memory device with a charge trap layer that is a multi-layer structure. An describes a charge trap layer that can be composed of different materials or materials with different compositions to improve performance. For instance, An's teachings suggest that stacking different dielectric layers can create deeper and more stable charge traps, which directly anticipates the motivation behind the '240 patent's multi-layer structure. A POSA would understand that by creating layers with different trap densities and energy levels, as suggested by An, one could optimize both programming speed and data retention.

• High Work Function Gate Electrodes: The use of high work function gate electrodes in non-volatile memory was well-established prior to 2007. Materials like p-type doped polysilicon or various metals and metal nitrides (e.g., TaN, TiN) were known to improve erase performance and data retention by creating a higher energy barrier that prevents electrons from leaking out of the charge-trapping layer. The '240 patent itself acknowledges that doped polysilicon is a known material for gate electrodes. The motivation to use a high work function gate is to improve the very performance metrics that the '240 patent seeks to address: programming efficiency and data retention.

Motivation to Combine:

A person of ordinary skill in the art, seeking to improve the data retention of a charge-trap memory device, would have been motivated to combine the teachings of Lee and An. Lee teaches the benefit of a silicon-rich nitride for creating more charge traps, while An teaches the benefit of a multi-layer charge-trapping structure for optimizing charge storage. It would have been a natural and predictable design choice to combine these concepts to create a multi-layer nitride with varying compositions.

Specifically, a POSA would understand that a silicon-rich (oxygen-lean) layer, as taught by Lee, is effective at trapping charge, while a more stoichiometric or oxygen-rich nitride layer provides better insulation. Creating a structure with an oxygen-rich layer, an anti-tunneling oxide, and an oxygen-lean layer, as claimed in the '240 patent, would be a logical step to balance charge trapping and retention. The anti-tunneling oxide layer is a known feature in memory devices to prevent charge migration between different layers.

Furthermore, integrating a high work function gate electrode with this improved charge-trapping layer would have been an obvious step to further enhance the device's performance. The benefits of high work function gates were well-documented in the prior art, and it was common practice to combine known gate materials with new charge-trapping structures to achieve incremental improvements in memory technology. The combination would have been expected to yield a memory cell with both improved charge trapping from the multi-layer nitride and reduced charge leakage due to the high work function gate, a predictable outcome.

Conclusion

The individual elements of the claims in U.S. Patent No. 9,929,240 were known in the prior art. The specific combination of an oxygen-rich nitride layer, an anti-tunneling oxide, an oxygen-lean nitride layer, and a high work function gate represents a combination of known elements to achieve a predictable result. The motivation to combine these elements would have been readily apparent to a person of ordinary skill in the art in 2007, making the claims of the '240 patent obvious under 35 U.S.C. § 103.

Patent Term and Expiration

The subject patent, U.S. 9,929,240, has a projected expiration date of May 13, 2028. This is based on the standard 20-year term from its earliest non-provisional priority filing date.

• Earliest Non-Provisional Filing Date: May 13, 2008 (from U.S. Patent Application No. 12/152,518, now U.S. Patent No. 8,063,434).
• Patent Term Adjustment (PTA): The United States Patent and Trademark Office (USPTO) granted 0 days of Patent Term Adjustment. There were no prosecution delays on the part of the USPTO that would warrant an extension.
• Patent Term Extension (PTE): There is no evidence of any Patent Term Extension (PTE) under 35 U.S.C. § 156, which typically applies to products requiring pre-market regulatory review and is not applicable here.

Therefore, the calculated expiration date remains unaffected by any adjustments or extensions.

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Continuity and Patent Family

U.S. Patent No. 9,929,240 is part of a large family of patents and applications originating from a provisional application filed in 2007. The patent claims a long chain of priority through multiple parent applications.

Direct Priority Chain:

The '240 patent, which issued from Application No. 15/335,180, has the following direct lineage as detailed in its "Cross-Reference to Related Applications":

• It is a continuation of Application No. 14/811,346 (filed Jul. 28, 2015).
• Which is a continuation of Application No. 14/159,315 (filed Jan. 20, 2014), now U.S. Patent No. 9,093,318.
• Which is a continuation of Application No. 13/539,466 (filed Jul. 1, 2012), now U.S. Patent No. 8,633,537.
• Which is a continuation-in-part of Application No. 13/288,919 (filed Nov. 3, 2011), now U.S. Patent No. 8,859,374.
• Which is a divisional of Application No. 12/152,518 (filed May 13, 2008), now U.S. Patent No. 8,063,434.
• Which claims the benefit of U.S. Provisional Application No. 60/940,160 (filed May 25, 2007).

Additional Known U.S. Family Members:

The following patents and applications are also part of this family, claiming priority back to the '518 application:

• U.S. Patent No. 10,446,656 (from Application No. 15/376,282)
• U.S. Patent No. 10,312,336 (from Application No. 15/864,832)
• U.S. Patent No. 10,903,325 (from Application No. 16/429,464)
• U.S. Patent No. 11,056,565 (from Application No. 16/600,768)
• U.S. Patent No. 11,456,365 (from Application No. 17/157,350)
• U.S. Patent No. 11,721,733 (from Application No. 17/366,934)
• U.S. Patent No. 12,009,401 (from Application No. 17/952,796)
• U.S. Patent Application Publication No. 2024/0332385 A1 (from Application No. 18/739,179)

Defensive Disclosure: US Patent 9,929,240

Publication Date: May 13, 2026
Subject: Variations and extensions of non-volatile memory transistors with multi-layer charge-trapping regions.
Purpose: This document discloses a series of derivative inventions and improvements upon the technology described in US Patent No. 9,929,240 ("the '240 patent"). The purpose of this disclosure is to place these concepts in the public domain, thereby establishing prior art against future patent applications claiming these or similar ideas. The following descriptions are intended to be enabling for a person having ordinary skill in the art (PHOSITA) of semiconductor device physics and fabrication.

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Derivations Based on Independent Claim 1: Memory Device Structure

The core of the '240 patent describes a memory device with a specific Oxide-Nitride-Oxide-Nitride-Oxide (ONONO) gate stack structure. The following disclosures expand upon this structure using alternative materials, operating conditions, and system integrations.

Axis 1: Material & Component Substitution

Derivative 1.1: High-k Dielectric Integration

• Enabling Description: The performance of the ONONO stack can be enhanced by replacing the silicon dioxide (SiO₂) and silicon nitride (Si₃N₄) layers with high-k dielectric materials. The tunnel dielectric (416) is replaced with a 2-4 nm layer of Hafnium Oxide (HfO₂). The oxygen-rich first nitride layer (422a) is replaced with a Hafnium-rich Hafnium Silicate (HfSiO) layer, which provides a moderate trap density. The anti-tunneling layer (422c) is formed by a thin, 1-2 nm layer of Aluminum Oxide (Al₂O₃), which has a large bandgap, providing a superior tunneling barrier. The oxygen-lean second nitride layer (422b) is replaced with a nitrogen-doped Hafnium Silicate (HfSiON) layer, which is engineered to have a high density of deep-level charge traps. The blocking dielectric (420) is replaced with a multi-layer stack of Al₂O₃ and HfO₂ to create a tailored band-offset structure that suppresses back-injection of electrons from the gate. This "high-k" ONONO variant improves charge retention and reduces operating voltages.
• Mermaid Diagram:

  graph TD
      subgraph Gate Stack
          A[High Work Function Gate: TiN/W]
          B[Blocking Dielectric: Al₂O₃/HfO₂ Laminate]
          C[Oxygen-Lean Layer: HfSiON]
          D[Anti-Tunneling Layer: Al₂O₃]
          E[Oxygen-Rich Layer: HfSiO]
          F[Tunnel Dielectric: HfO₂]
      end
      G[Semiconductor Channel: Si, SiGe, or InGaAs]
      A --> B --> C --> D --> E --> F --> G
  

Derivative 1.2: 2D Material Channel Integration

• Enabling Description: The silicon channel region (412) is replaced with a two-dimensional (2D) material, such as a monolayer or few-layer sheet of Molybdenum Disulfide (MoS₂) or Tungsten Diselenide (WSe₂). The ONONO gate stack is deposited directly onto the 2D material. This configuration confines the channel to an atomically thin layer, providing excellent electrostatic control and reducing short-channel effects. The Van der Waals interface between the tunnel oxide and the 2D material minimizes interface traps. This enables ultra-scaled, low-power memory devices. The source/drain regions (410) are formed by metal contacts (e.g., Titanium/Gold) directly on the 2D material, or by locally doping the 2D material using a plasma treatment.
• Mermaid Diagram:

  graph LR
      subgraph Substrate
          subgraph Device
              Gate[Gate Stack (ONONO)] -- Field Effect --> Channel
              Source[Source Contact: Ti/Au] --> Channel[2D Material: MoS₂] --> Drain[Drain Contact: Ti/Au]
          end
          Insulator[Substrate Oxide: SiO₂]
          SiSubstrate[Silicon Substrate]
      end
      Device -- Rests on --> Insulator
      Insulator -- Rests on --> SiSubstrate
  

Derivative 1.3: Ferroelectric-Enhanced Charge Trapping

• Enabling Description: The charge-trapping characteristics of the stack are augmented by replacing the anti-tunneling oxide layer (422c) with a thin, 2-5 nm layer of a ferroelectric material such as Hafnium Zirconium Oxide (HZO) or Barium Titanate (BTO). The inherent polarization of the ferroelectric layer creates a strong internal electric field that assists in the injection and retention of charge in the oxygen-lean nitride layer (422b). By poling the ferroelectric layer with a suitable voltage pulse, the trapping efficiency and retention time can be significantly increased, and the program/erase window widened. The high work function gate electrode aids in stabilizing the desired polarization state of the ferroelectric layer.
• Mermaid Diagram:

  sequenceDiagram
      participant Gate
      participant BlockingOxide
      participant O2LeanNitride
      participant FerroelectricLayer
      participant O2RichNitride
      participant TunnelOxide
      participant Channel
  
      Gate->>BlockingOxide: Apply Program Voltage (V_prog)
      BlockingOxide->>O2LeanNitride: E-field propagates
      O2LeanNitride->>FerroelectricLayer: E-field aligns dipoles
      FerroelectricLayer-->>O2LeanNitride: Internal field enhances injection
      O2RichNitride->>TunnelOxide: E-field present
      TunnelOxide->>Channel: Electrons tunnel into O2-Lean Nitride
      Note right of Channel: Charge is trapped in O2-Lean Layer, assisted by Ferroelectric Polarization
  

Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Temperature Operation for Quantum Computing

• Enabling Description: The ONONO memory device is optimized for operation at cryogenic temperatures (below 4 Kelvin) for use as a classical control or memory element integrated with superconducting quantum bits (qubits). At these temperatures, thermal charge leakage is effectively eliminated. The material properties of the nitride layers (422a, 422b) are specifically tuned by adjusting the N/Si/O ratios to ensure predictable charge trapping and de-trapping via Fowler-Nordheim or direct tunneling, which are less temperature-dependent mechanisms. The high work function gate material is selected from a superconductor, such as Niobium Nitride (NbN), to ensure compatibility with the quantum computing environment and reduce thermal dissipation. The device can store qubit state information or calibration parameters with near-permanent retention as long as the cryogenic environment is maintained.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Unprogrammed
  
      Unprogrammed --> Programmed: V_prog Applied
      note right of Unprogrammed
          Operation at < 4 Kelvin
          Charge injection via Fowler-Nordheim Tunneling
          Zero thermal leakage
      end note
  
      Programmed --> Unprogrammed: V_erase Applied
      Programmed --> Programmed: T < 4K, Power Off (Effectively permanent retention)
      note left of Programmed
          Superconducting Gate (NbN)
          State read via channel conductance
      end note
  

Derivative 2.2: High-Temperature and Radiation-Hardened Operation

• Enabling Description: The device is fabricated on a Silicon-on-Insulator (SOI) or Silicon Carbide (SiC) substrate to enhance its tolerance to high temperatures (>250°C) and high-radiation environments, such as those found in automotive under-the-hood applications, downhole drilling, or space. The dielectric layers in the ONONO stack are formed using high-purity, stoichiometric materials deposited via Atomic Layer Deposition (ALD) to minimize defects that could be activated by temperature or radiation. The oxygen-rich nitride layer (422a) is intentionally thickened to act as a radiation-induced charge trapping shield, protecting the primary charge storage layer (422b). The gate electrode is formed from a refractory metal silicide, like Tungsten Silicide (WSi₂), for thermal stability.
• Mermaid Diagram:

  graph TD
      subgraph Rad-Hard ONONO on SiC
          A(Gate: Tungsten Silicide) --> B(Blocking Oxide: ALD Al₂O₃)
          B --> C(Charge Trapping Layer: High-purity Si₃N₄)
          C --> D(Anti-Tunneling Oxide: ALD SiO₂)
          D --> E(Rad-Shield Layer: Thick SiON)
          E --> F(Tunnel Oxide: ALD SiO₂)
          F --> G(Channel: Silicon Carbide - SiC)
      end
  

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Non-Volatile Radiation Dosimeter

• Enabling Description: The ONONO structure is adapted to function as a passive, non-volatile radiation dosimeter. The gate electrode is replaced with a material with a large cross-section for interacting with high-energy particles (e.g., a Boron-10 enriched layer for neutron detection). When ionizing radiation passes through the gate stack, it generates electron-hole pairs. The resulting charge is permanently trapped within the multi-layer trapping region (422), causing a cumulative and measurable shift in the transistor's threshold voltage (V_th). The amount of V_th shift is directly proportional to the total radiation dose received. Since the charge is stored non-volatilely, the device requires no power to record the exposure. The total dose can be read out at a later time by measuring the V_th.
• Mermaid Diagram:

  flowchart LR
      subgraph In Space
          A[High-Energy Particle] --> B{Interaction with Gate Stack};
          B --> C[e-/h+ Pair Generation];
          C --> D[Charge Trapping in Nitride Layers];
      end
  
      subgraph Ground Readout
          D -- Cumulative V_th Shift --> E[Measure I-V Curve];
          E --> F[Calculate Total Dose];
      end
  
      style A fill:#ffadad
      style F fill:#caffbf
  

Derivative 3.2: AgTech - Soil Nutrient Sensor with Memory

• Enabling Description: The memory device is re-purposed as a chemiresistive sensor with non-volatile memory. The high work function gate electrode is replaced by an ion-selective membrane (ISM) specifically designed to be sensitive to nitrate (NO₃⁻) ions in soil. The ISM is deposited directly onto the blocking oxide (420). When the device is placed in soil, the concentration of nitrate ions modulates the surface potential of the ISM. This change in potential alters the electric field across the gate stack, causing a shift in the transistor's threshold voltage. At periodic intervals, a "write" voltage is applied, forcing charge to tunnel into the charge-trapping layers, effectively storing an analog value of the current nitrate concentration. The sensor can be powered off, retaining this last-measured value indefinitely. This allows for long-term, low-power monitoring of soil health in remote agricultural settings.
• Mermaid Diagram:

  graph TD
      A[Nitrate Ions in Soil] --> B(Ion-Selective Membrane);
      B -- Induces Surface Potential --> C(Blocking Oxide);
      C -- Modulates E-Field --> D(Multi-Layer Charge Trap);
      D -- Shifts V_th --> E(Semiconductor Channel);
      F(Apply 'Write' Pulse) --> D;
      G(Power Down) -- Retains V_th --> H(Readout Later);
  

Derivative 3.3: Consumer Electronics - Analog Neuromorphic Synapse

• Enabling Description: The ONONO transistor is operated as an artificial synapse in a neuromorphic computing circuit. The synaptic weight is represented by the amount of charge stored in the multi-layer trapping region (422), which directly controls the channel conductance (i.e., the neuron's connection strength). "Potentiation" (strengthening the connection) is achieved by applying a series of positive voltage pulses to the gate, incrementally adding charge to the trapping layers. "Depression" (weakening the connection) is accomplished with negative voltage pulses. The dual-layer (oxygen-rich and oxygen-lean) nitride structure allows for both fast, short-term plasticity (charge in the shallower traps of the oxygen-lean layer) and slow, long-term consolidation (charge migrating to the deeper, more stable traps of the oxygen-rich layer), mimicking biological synaptic behavior.
• Mermaid Diagram:

  stateDiagram-v2
      state "Low Conductance (Weak Synapse)" as Weak
      state "High Conductance (Strong Synapse)" as Strong
      state "Intermediate States" as Intermediate
  
      [*] --> Weak
      Weak --> Intermediate : Potentiation Pulse (+V)
      Intermediate --> Strong : More Pulses (+V)
      Strong --> Intermediate : Depression Pulse (-V)
      Intermediate --> Weak : More Pulses (-V)
  
      note right of Intermediate
          Synaptic weight is analog,
          encoded by charge Q_trap.
          O2-lean layer = Short-term memory
          O2-rich layer = Long-term memory
      end note
  

Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Driven Predictive Endurance Management

• Enabling Description: An array of memory cells based on the '240 patent is coupled with an on-chip AI accelerator. The controller for the memory array includes sensors that monitor the threshold voltage (V_th), gate leakage current, and program/erase cycle times for each block of memory. This real-time data is fed into a lightweight, trained neural network. The AI model, having been trained on device degradation physics, predicts the remaining useful life (RUL) of each memory block. It then dynamically adjusts the program/erase voltage levels and pulse widths for aging blocks to minimize further stress, thereby extending the overall endurance of the memory chip. It also proactively re-maps data from blocks predicted to fail soon, preventing data loss.
• Mermaid Diagram:

  graph TD
      subgraph MemoryChip
          A[Memory Array (ONONO Cells)]
          B[On-chip Sensors]
          C[AI-Powered Controller]
          D[Wear-Leveling Logic]
      end
      A -- V_th, I_leak, P/E time --> B
      B -- Telemetry Data --> C
      C -- Predicts RUL, Adjusts V_prog --> A
      C -- Identifies Weak Blocks --> D
      D -- Remaps Data --> A
  

Derivative 4.2: IoT-Enabled Environmental Logging with Secure Attestation

• Enabling Description: The memory device is integrated into a battery-less IoT sensor node that harvests energy from its environment (e.g., solar, RF). The sensor measures a physical parameter (e.g., temperature) and stores the value in the ONONO memory cell. The device's unique charge trapping and detrapping characteristics, which vary slightly from device to device due to manufacturing variations, are used as a Physical Unclonable Function (PUF). At boot-up, a challenge-response protocol is run on the PUF to generate a unique, device-specific cryptographic key. This key is used to sign the stored sensor data before transmission. A blockchain ledger is used to record the signed data, providing an immutable and verifiable record of the environmental conditions, with cryptographic proof that the data originated from that specific, untampered sensor.
• Mermaid Diagram:

  sequenceDiagram
      participant SensorNode
      participant Blockchain
      SensorNode->>SensorNode: Measure Temperature
      SensorNode->>SensorNode: Store Value in ONONO Memory
      SensorNode->>SensorNode: Generate Key from ONONO PUF
      SensorNode->>SensorNode: Sign(Data + Key)
      SensorNode->>Blockchain: Transmit SignedData
      Blockchain->>Blockchain: Verify Signature & Record
  

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Self-Erasing Transient Memory

• Enabling Description: The device is intentionally designed for controlled data transience. The anti-tunneling oxide layer (422c) is replaced with a leaky dielectric material, such as silicon-rich oxide (SRO), or is fabricated with a deliberately high defect density. This creates a defined leakage path between the oxygen-lean and oxygen-rich nitride layers. When programmed, charge is initially stored in the oxygen-lean layer, allowing for normal read operations. However, over a predictable time constant (tunable from minutes to days based on the SRO composition and thickness), this charge will leak through the defective anti-tunneling layer and recombine or be neutralized in the lower stack. This creates a "self-erasing" memory cell, useful for secure applications where data must be automatically deleted after a set period without power.
• Mermaid Diagram:

  graph TD
      A[Programmed State: Charge in O2-Lean Layer] -->|Time| B(Charge Leaks Through Defective Anti-Tunneling Layer)
      B --> C{Charge Recombination}
      C --> D[Erased State: Neutral Charge]
      subgraph Key Feature
          E[Leaky Anti-Tunneling Layer (e.g., SRO)]
      end
  

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Combination Prior Art Scenarios with Open-Source Standards

Combination 1: RISC-V Microcontroller with Integrated ONONO eNVM

• Description: The memory cell architecture described in the '240 patent is implemented as an embedded Non-Volatile Memory (eNVM) block within a system-on-chip (SoC) based on the open-source RISC-V instruction set architecture. A standard RISC-V core (e.g., a 32-bit RV32IMC core) is synthesized alongside a memory controller and an array of the multi-layer charge-trap transistors. The memory controller interfaces with the RISC-V core via a standard bus protocol like AXI or Wishbone. Open-source firmware, running on the RISC-V core, manages the flash memory, implementing a file system or providing a direct memory-mapped interface for program storage (code-flash) or data logging (data-flash). The combination of an open, royalty-free CPU architecture with this specific, high-retention eNVM structure is a logical and obvious step for creating low-cost, secure microcontrollers.

Combination 2: Verilog-A Behavioral Model for ONONO Devices

• Description: A behavioral model of the ONONO memory transistor is created using the Verilog-A hardware description language, an open standard for analog and mixed-signal systems. The model mathematically describes the key physical processes of the device: Fowler-Nordheim and direct tunneling through the tunnel oxide, charge trapping and de-trapping in the dual nitride layers, and inter-layer leakage. The model is parameterized based on the material properties and thicknesses described in the '240 patent (e.g., trap density of the oxygen-lean layer, thickness of the anti-tunneling oxide). This open-source Verilog-A model can be compiled and used in any standard SPICE-based circuit simulator (e.g., NGSPICE, Xyce), allowing engineers to freely design and simulate circuits incorporating this memory technology. This public availability of a simulation model makes the integration of the device into larger systems an obvious design choice.

Combination 3: Micropython Driver for ONONO-based Flash Storage

• Description: A hardware driver module for MicroPython, an open-source implementation of Python 3 for microcontrollers, is developed to manage a storage device built from an array of the '240 patent's memory cells. The driver abstracts the low-level hardware operations of programming, reading, and erasing the ONONO cells into high-level, file-system-like commands accessible from a Python script. The driver would implement wear-leveling algorithms to distribute write/erase cycles evenly across the memory array, and error correction code (ECC) to handle bit flips, especially in harsh operating environments. By integrating support into a high-level, open-source embedded programming language like MicroPython, the use of this specific memory hardware becomes a straightforward and obvious implementation choice for the large community of IoT and embedded systems developers.