Derivative works — US Patent 9929240

Defensive Disclosure: US Patent 9,929,240

Publication Date: May 13, 2026
Subject: Variations and extensions of non-volatile memory transistors with multi-layer charge-trapping regions.
Purpose: This document discloses a series of derivative inventions and improvements upon the technology described in US Patent No. 9,929,240 ("the '240 patent"). The purpose of this disclosure is to place these concepts in the public domain, thereby establishing prior art against future patent applications claiming these or similar ideas. The following descriptions are intended to be enabling for a person having ordinary skill in the art (PHOSITA) of semiconductor device physics and fabrication.

Derivations Based on Independent Claim 1: Memory Device Structure

The core of the '240 patent describes a memory device with a specific Oxide-Nitride-Oxide-Nitride-Oxide (ONONO) gate stack structure. The following disclosures expand upon this structure using alternative materials, operating conditions, and system integrations.

Axis 1: Material & Component Substitution

Derivative 1.1: High-k Dielectric Integration

Enabling Description: The performance of the ONONO stack can be enhanced by replacing the silicon dioxide (SiO₂) and silicon nitride (Si₃N₄) layers with high-k dielectric materials. The tunnel dielectric (416) is replaced with a 2-4 nm layer of Hafnium Oxide (HfO₂). The oxygen-rich first nitride layer (422a) is replaced with a Hafnium-rich Hafnium Silicate (HfSiO) layer, which provides a moderate trap density. The anti-tunneling layer (422c) is formed by a thin, 1-2 nm layer of Aluminum Oxide (Al₂O₃), which has a large bandgap, providing a superior tunneling barrier. The oxygen-lean second nitride layer (422b) is replaced with a nitrogen-doped Hafnium Silicate (HfSiON) layer, which is engineered to have a high density of deep-level charge traps. The blocking dielectric (420) is replaced with a multi-layer stack of Al₂O₃ and HfO₂ to create a tailored band-offset structure that suppresses back-injection of electrons from the gate. This "high-k" ONONO variant improves charge retention and reduces operating voltages.

Mermaid Diagram:

graph TD
    subgraph Gate Stack
        A[High Work Function Gate: TiN/W]
        B[Blocking Dielectric: Al₂O₃/HfO₂ Laminate]
        C[Oxygen-Lean Layer: HfSiON]
        D[Anti-Tunneling Layer: Al₂O₃]
        E[Oxygen-Rich Layer: HfSiO]
        F[Tunnel Dielectric: HfO₂]
    end
    G[Semiconductor Channel: Si, SiGe, or InGaAs]
    A --> B --> C --> D --> E --> F --> G

Derivative 1.2: 2D Material Channel Integration

Enabling Description: The silicon channel region (412) is replaced with a two-dimensional (2D) material, such as a monolayer or few-layer sheet of Molybdenum Disulfide (MoS₂) or Tungsten Diselenide (WSe₂). The ONONO gate stack is deposited directly onto the 2D material. This configuration confines the channel to an atomically thin layer, providing excellent electrostatic control and reducing short-channel effects. The Van der Waals interface between the tunnel oxide and the 2D material minimizes interface traps. This enables ultra-scaled, low-power memory devices. The source/drain regions (410) are formed by metal contacts (e.g., Titanium/Gold) directly on the 2D material, or by locally doping the 2D material using a plasma treatment.

Mermaid Diagram:

graph LR
    subgraph Substrate
        subgraph Device
            Gate[Gate Stack (ONONO)] -- Field Effect --> Channel
            Source[Source Contact: Ti/Au] --> Channel[2D Material: MoS₂] --> Drain[Drain Contact: Ti/Au]
        end
        Insulator[Substrate Oxide: SiO₂]
        SiSubstrate[Silicon Substrate]
    end
    Device -- Rests on --> Insulator
    Insulator -- Rests on --> SiSubstrate

Derivative 1.3: Ferroelectric-Enhanced Charge Trapping

Enabling Description: The charge-trapping characteristics of the stack are augmented by replacing the anti-tunneling oxide layer (422c) with a thin, 2-5 nm layer of a ferroelectric material such as Hafnium Zirconium Oxide (HZO) or Barium Titanate (BTO). The inherent polarization of the ferroelectric layer creates a strong internal electric field that assists in the injection and retention of charge in the oxygen-lean nitride layer (422b). By poling the ferroelectric layer with a suitable voltage pulse, the trapping efficiency and retention time can be significantly increased, and the program/erase window widened. The high work function gate electrode aids in stabilizing the desired polarization state of the ferroelectric layer.

Mermaid Diagram:

sequenceDiagram
    participant Gate
    participant BlockingOxide
    participant O2LeanNitride
    participant FerroelectricLayer
    participant O2RichNitride
    participant TunnelOxide
    participant Channel

    Gate->>BlockingOxide: Apply Program Voltage (V_prog)
    BlockingOxide->>O2LeanNitride: E-field propagates
    O2LeanNitride->>FerroelectricLayer: E-field aligns dipoles
    FerroelectricLayer-->>O2LeanNitride: Internal field enhances injection
    O2RichNitride->>TunnelOxide: E-field present
    TunnelOxide->>Channel: Electrons tunnel into O2-Lean Nitride
    Note right of Channel: Charge is trapped in O2-Lean Layer, assisted by Ferroelectric Polarization

Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Temperature Operation for Quantum Computing

Enabling Description: The ONONO memory device is optimized for operation at cryogenic temperatures (below 4 Kelvin) for use as a classical control or memory element integrated with superconducting quantum bits (qubits). At these temperatures, thermal charge leakage is effectively eliminated. The material properties of the nitride layers (422a, 422b) are specifically tuned by adjusting the N/Si/O ratios to ensure predictable charge trapping and de-trapping via Fowler-Nordheim or direct tunneling, which are less temperature-dependent mechanisms. The high work function gate material is selected from a superconductor, such as Niobium Nitride (NbN), to ensure compatibility with the quantum computing environment and reduce thermal dissipation. The device can store qubit state information or calibration parameters with near-permanent retention as long as the cryogenic environment is maintained.

Mermaid Diagram:

stateDiagram-v2
    [*] --> Unprogrammed

    Unprogrammed --> Programmed: V_prog Applied
    note right of Unprogrammed
        Operation at < 4 Kelvin
        Charge injection via Fowler-Nordheim Tunneling
        Zero thermal leakage
    end note

    Programmed --> Unprogrammed: V_erase Applied
    Programmed --> Programmed: T < 4K, Power Off (Effectively permanent retention)
    note left of Programmed
        Superconducting Gate (NbN)
        State read via channel conductance
    end note

Derivative 2.2: High-Temperature and Radiation-Hardened Operation

Enabling Description: The device is fabricated on a Silicon-on-Insulator (SOI) or Silicon Carbide (SiC) substrate to enhance its tolerance to high temperatures (>250°C) and high-radiation environments, such as those found in automotive under-the-hood applications, downhole drilling, or space. The dielectric layers in the ONONO stack are formed using high-purity, stoichiometric materials deposited via Atomic Layer Deposition (ALD) to minimize defects that could be activated by temperature or radiation. The oxygen-rich nitride layer (422a) is intentionally thickened to act as a radiation-induced charge trapping shield, protecting the primary charge storage layer (422b). The gate electrode is formed from a refractory metal silicide, like Tungsten Silicide (WSi₂), for thermal stability.

Mermaid Diagram:

graph TD
    subgraph Rad-Hard ONONO on SiC
        A(Gate: Tungsten Silicide) --> B(Blocking Oxide: ALD Al₂O₃)
        B --> C(Charge Trapping Layer: High-purity Si₃N₄)
        C --> D(Anti-Tunneling Oxide: ALD SiO₂)
        D --> E(Rad-Shield Layer: Thick SiON)
        E --> F(Tunnel Oxide: ALD SiO₂)
        F --> G(Channel: Silicon Carbide - SiC)
    end

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Non-Volatile Radiation Dosimeter

Enabling Description: The ONONO structure is adapted to function as a passive, non-volatile radiation dosimeter. The gate electrode is replaced with a material with a large cross-section for interacting with high-energy particles (e.g., a Boron-10 enriched layer for neutron detection). When ionizing radiation passes through the gate stack, it generates electron-hole pairs. The resulting charge is permanently trapped within the multi-layer trapping region (422), causing a cumulative and measurable shift in the transistor's threshold voltage (V_th). The amount of V_th shift is directly proportional to the total radiation dose received. Since the charge is stored non-volatilely, the device requires no power to record the exposure. The total dose can be read out at a later time by measuring the V_th.

Mermaid Diagram:

flowchart LR
    subgraph In Space
        A[High-Energy Particle] --> B{Interaction with Gate Stack};
        B --> C[e-/h+ Pair Generation];
        C --> D[Charge Trapping in Nitride Layers];
    end

    subgraph Ground Readout
        D -- Cumulative V_th Shift --> E[Measure I-V Curve];
        E --> F[Calculate Total Dose];
    end

    style A fill:#ffadad
    style F fill:#caffbf

Derivative 3.2: AgTech - Soil Nutrient Sensor with Memory

Enabling Description: The memory device is re-purposed as a chemiresistive sensor with non-volatile memory. The high work function gate electrode is replaced by an ion-selective membrane (ISM) specifically designed to be sensitive to nitrate (NO₃⁻) ions in soil. The ISM is deposited directly onto the blocking oxide (420). When the device is placed in soil, the concentration of nitrate ions modulates the surface potential of the ISM. This change in potential alters the electric field across the gate stack, causing a shift in the transistor's threshold voltage. At periodic intervals, a "write" voltage is applied, forcing charge to tunnel into the charge-trapping layers, effectively storing an analog value of the current nitrate concentration. The sensor can be powered off, retaining this last-measured value indefinitely. This allows for long-term, low-power monitoring of soil health in remote agricultural settings.

Mermaid Diagram:

graph TD
    A[Nitrate Ions in Soil] --> B(Ion-Selective Membrane);
    B -- Induces Surface Potential --> C(Blocking Oxide);
    C -- Modulates E-Field --> D(Multi-Layer Charge Trap);
    D -- Shifts V_th --> E(Semiconductor Channel);
    F(Apply 'Write' Pulse) --> D;
    G(Power Down) -- Retains V_th --> H(Readout Later);

Derivative 3.3: Consumer Electronics - Analog Neuromorphic Synapse

Enabling Description: The ONONO transistor is operated as an artificial synapse in a neuromorphic computing circuit. The synaptic weight is represented by the amount of charge stored in the multi-layer trapping region (422), which directly controls the channel conductance (i.e., the neuron's connection strength). "Potentiation" (strengthening the connection) is achieved by applying a series of positive voltage pulses to the gate, incrementally adding charge to the trapping layers. "Depression" (weakening the connection) is accomplished with negative voltage pulses. The dual-layer (oxygen-rich and oxygen-lean) nitride structure allows for both fast, short-term plasticity (charge in the shallower traps of the oxygen-lean layer) and slow, long-term consolidation (charge migrating to the deeper, more stable traps of the oxygen-rich layer), mimicking biological synaptic behavior.

Mermaid Diagram:

stateDiagram-v2
    state "Low Conductance (Weak Synapse)" as Weak
    state "High Conductance (Strong Synapse)" as Strong
    state "Intermediate States" as Intermediate

    [*] --> Weak
    Weak --> Intermediate : Potentiation Pulse (+V)
    Intermediate --> Strong : More Pulses (+V)
    Strong --> Intermediate : Depression Pulse (-V)
    Intermediate --> Weak : More Pulses (-V)

    note right of Intermediate
        Synaptic weight is analog,
        encoded by charge Q_trap.
        O2-lean layer = Short-term memory
        O2-rich layer = Long-term memory
    end note

Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Driven Predictive Endurance Management

Enabling Description: An array of memory cells based on the '240 patent is coupled with an on-chip AI accelerator. The controller for the memory array includes sensors that monitor the threshold voltage (V_th), gate leakage current, and program/erase cycle times for each block of memory. This real-time data is fed into a lightweight, trained neural network. The AI model, having been trained on device degradation physics, predicts the remaining useful life (RUL) of each memory block. It then dynamically adjusts the program/erase voltage levels and pulse widths for aging blocks to minimize further stress, thereby extending the overall endurance of the memory chip. It also proactively re-maps data from blocks predicted to fail soon, preventing data loss.

Mermaid Diagram:

graph TD
    subgraph MemoryChip
        A[Memory Array (ONONO Cells)]
        B[On-chip Sensors]
        C[AI-Powered Controller]
        D[Wear-Leveling Logic]
    end
    A -- V_th, I_leak, P/E time --> B
    B -- Telemetry Data --> C
    C -- Predicts RUL, Adjusts V_prog --> A
    C -- Identifies Weak Blocks --> D
    D -- Remaps Data --> A

Derivative 4.2: IoT-Enabled Environmental Logging with Secure Attestation

Enabling Description: The memory device is integrated into a battery-less IoT sensor node that harvests energy from its environment (e.g., solar, RF). The sensor measures a physical parameter (e.g., temperature) and stores the value in the ONONO memory cell. The device's unique charge trapping and detrapping characteristics, which vary slightly from device to device due to manufacturing variations, are used as a Physical Unclonable Function (PUF). At boot-up, a challenge-response protocol is run on the PUF to generate a unique, device-specific cryptographic key. This key is used to sign the stored sensor data before transmission. A blockchain ledger is used to record the signed data, providing an immutable and verifiable record of the environmental conditions, with cryptographic proof that the data originated from that specific, untampered sensor.

Mermaid Diagram:

sequenceDiagram
    participant SensorNode
    participant Blockchain
    SensorNode->>SensorNode: Measure Temperature
    SensorNode->>SensorNode: Store Value in ONONO Memory
    SensorNode->>SensorNode: Generate Key from ONONO PUF
    SensorNode->>SensorNode: Sign(Data + Key)
    SensorNode->>Blockchain: Transmit SignedData
    Blockchain->>Blockchain: Verify Signature & Record

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Self-Erasing Transient Memory

Enabling Description: The device is intentionally designed for controlled data transience. The anti-tunneling oxide layer (422c) is replaced with a leaky dielectric material, such as silicon-rich oxide (SRO), or is fabricated with a deliberately high defect density. This creates a defined leakage path between the oxygen-lean and oxygen-rich nitride layers. When programmed, charge is initially stored in the oxygen-lean layer, allowing for normal read operations. However, over a predictable time constant (tunable from minutes to days based on the SRO composition and thickness), this charge will leak through the defective anti-tunneling layer and recombine or be neutralized in the lower stack. This creates a "self-erasing" memory cell, useful for secure applications where data must be automatically deleted after a set period without power.

Mermaid Diagram:

graph TD
    A[Programmed State: Charge in O2-Lean Layer] -->|Time| B(Charge Leaks Through Defective Anti-Tunneling Layer)
    B --> C{Charge Recombination}
    C --> D[Erased State: Neutral Charge]
    subgraph Key Feature
        E[Leaky Anti-Tunneling Layer (e.g., SRO)]
    end

Combination Prior Art Scenarios with Open-Source Standards

Combination 1: RISC-V Microcontroller with Integrated ONONO eNVM

Description: The memory cell architecture described in the '240 patent is implemented as an embedded Non-Volatile Memory (eNVM) block within a system-on-chip (SoC) based on the open-source RISC-V instruction set architecture. A standard RISC-V core (e.g., a 32-bit RV32IMC core) is synthesized alongside a memory controller and an array of the multi-layer charge-trap transistors. The memory controller interfaces with the RISC-V core via a standard bus protocol like AXI or Wishbone. Open-source firmware, running on the RISC-V core, manages the flash memory, implementing a file system or providing a direct memory-mapped interface for program storage (code-flash) or data logging (data-flash). The combination of an open, royalty-free CPU architecture with this specific, high-retention eNVM structure is a logical and obvious step for creating low-cost, secure microcontrollers.

Combination 2: Verilog-A Behavioral Model for ONONO Devices

Description: A behavioral model of the ONONO memory transistor is created using the Verilog-A hardware description language, an open standard for analog and mixed-signal systems. The model mathematically describes the key physical processes of the device: Fowler-Nordheim and direct tunneling through the tunnel oxide, charge trapping and de-trapping in the dual nitride layers, and inter-layer leakage. The model is parameterized based on the material properties and thicknesses described in the '240 patent (e.g., trap density of the oxygen-lean layer, thickness of the anti-tunneling oxide). This open-source Verilog-A model can be compiled and used in any standard SPICE-based circuit simulator (e.g., NGSPICE, Xyce), allowing engineers to freely design and simulate circuits incorporating this memory technology. This public availability of a simulation model makes the integration of the device into larger systems an obvious design choice.

Combination 3: Micropython Driver for ONONO-based Flash Storage

Description: A hardware driver module for MicroPython, an open-source implementation of Python 3 for microcontrollers, is developed to manage a storage device built from an array of the '240 patent's memory cells. The driver abstracts the low-level hardware operations of programming, reading, and erasing the ONONO cells into high-level, file-system-like commands accessible from a Python script. The driver would implement wear-leveling algorithms to distribute write/erase cycles evenly across the memory array, and error correction code (ECC) to handle bit flips, especially in harsh operating environments. By integrating support into a high-level, open-source embedded programming language like MicroPython, the use of this specific memory hardware becomes a straightforward and obvious implementation choice for the large community of IoT and embedded systems developers.