Obviousness

Analysis of Obviousness for U.S. Patent No. 9,929,240

A person of ordinary skill in the art (POSA) at the time of the invention would have found the claims of U.S. Patent No. 9,929,240 obvious based on a combination of prior art references. The key features of the '240 patent—a multi-layer charge-trapping region with specific oxygen concentrations and an anti-tunneling layer, combined with a high work function gate electrode—are all taught or suggested by the prior art for the predictable purpose of improving memory cell performance, particularly data retention and program/erase efficiency.

Key Elements of the Invention

The independent claims of the '240 patent, particularly Claim 1, describe a memory transistor with a gate stack comprising:

1. A tunnel dielectric layer.
2. A multi-layer charge trapping region which includes:
   • An oxygen-rich first nitride layer.
   • An anti-tunneling oxide layer on top of the first nitride layer.
   • An oxygen-lean second nitride layer on top of the anti-tunneling layer.
3. A blocking dielectric layer.
4. A high work function gate electrode.

The core of the claimed invention is the engineered charge-trapping stack, which is essentially an Oxide-Nitride-Oxide-Nitride-Oxide (ONONO) structure, designed to enhance data retention by creating distinct regions for charge trapping and providing a barrier to prevent charge leakage.

Combination of Prior Art and Motivation to Combine

A strong case for obviousness can be made by combining the teachings of U.S. Patent No. 6,858,480 to Lee et al. (Lee), U.S. Patent No. 7,211,854 to An et al. (An), and the general knowledge in the art regarding high work function gate electrodes for non-volatile memory.

• Lee (US 6,858,480), filed in 2003, teaches a method of fabricating a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory device with an improved charge-trapping layer to enhance data retention. Lee specifically discloses creating a silicon-rich silicon nitride layer. The patent describes varying the gas flow rates during the deposition process to control the silicon-to-nitrogen ratio. This directly addresses the concept of engineering the nitride layer for better charge trapping, which is a central theme in the '240 patent. While Lee does not explicitly describe a dual-layer nitride with an intervening oxide, it establishes the principle of modifying nitride composition to improve memory characteristics.

• An (US 7,211,854), filed in 2005, discloses a non-volatile memory device with a charge trap layer that is a multi-layer structure. An describes a charge trap layer that can be composed of different materials or materials with different compositions to improve performance. For instance, An's teachings suggest that stacking different dielectric layers can create deeper and more stable charge traps, which directly anticipates the motivation behind the '240 patent's multi-layer structure. A POSA would understand that by creating layers with different trap densities and energy levels, as suggested by An, one could optimize both programming speed and data retention.

• High Work Function Gate Electrodes: The use of high work function gate electrodes in non-volatile memory was well-established prior to 2007. Materials like p-type doped polysilicon or various metals and metal nitrides (e.g., TaN, TiN) were known to improve erase performance and data retention by creating a higher energy barrier that prevents electrons from leaking out of the charge-trapping layer. The '240 patent itself acknowledges that doped polysilicon is a known material for gate electrodes. The motivation to use a high work function gate is to improve the very performance metrics that the '240 patent seeks to address: programming efficiency and data retention.

Motivation to Combine:

A person of ordinary skill in the art, seeking to improve the data retention of a charge-trap memory device, would have been motivated to combine the teachings of Lee and An. Lee teaches the benefit of a silicon-rich nitride for creating more charge traps, while An teaches the benefit of a multi-layer charge-trapping structure for optimizing charge storage. It would have been a natural and predictable design choice to combine these concepts to create a multi-layer nitride with varying compositions.

Specifically, a POSA would understand that a silicon-rich (oxygen-lean) layer, as taught by Lee, is effective at trapping charge, while a more stoichiometric or oxygen-rich nitride layer provides better insulation. Creating a structure with an oxygen-rich layer, an anti-tunneling oxide, and an oxygen-lean layer, as claimed in the '240 patent, would be a logical step to balance charge trapping and retention. The anti-tunneling oxide layer is a known feature in memory devices to prevent charge migration between different layers.

Furthermore, integrating a high work function gate electrode with this improved charge-trapping layer would have been an obvious step to further enhance the device's performance. The benefits of high work function gates were well-documented in the prior art, and it was common practice to combine known gate materials with new charge-trapping structures to achieve incremental improvements in memory technology. The combination would have been expected to yield a memory cell with both improved charge trapping from the multi-layer nitride and reduced charge leakage due to the high work function gate, a predictable outcome.

Conclusion

The individual elements of the claims in U.S. Patent No. 9,929,240 were known in the prior art. The specific combination of an oxygen-rich nitride layer, an anti-tunneling oxide, an oxygen-lean nitride layer, and a high work function gate represents a combination of known elements to achieve a predictable result. The motivation to combine these elements would have been readily apparent to a person of ordinary skill in the art in 2007, making the claims of the '240 patent obvious under 35 U.S.C. § 103.