Prior art — US Patent 9929240

Analysis of Prior Art for U.S. Patent No. 9,929,240

A critical aspect of patent analysis involves examining the prior art cited during the patent's prosecution and in any subsequent legal challenges. This analysis determines whether the invention claimed in the patent was already known and therefore not novel. Under U.S. patent law, specifically 35 U.S.C. § 102, a patent claim is invalid if every element of that claim is present in a single prior art reference. This is known as "anticipation." What follows is an assessment of the most relevant prior art references cited for U.S. Patent No. 9,929,240, focusing on their potential to anticipate the independent claims.

Key Concepts in the '240 Patent

The core of the invention in the '240 patent is a specific multi-layer charge-trapping structure within a non-volatile memory transistor. The key features, as detailed in the independent claims, are:

A multi-layer charge trapping region: This is the heart of the invention.
Three specific sub-layers:
1. An "oxygen-rich" nitride layer (also referred to as silicon oxynitride).
2. An "anti-tunneling" oxide layer situated on top of the first nitride layer.
3. An "oxygen-lean" nitride layer (or silicon oxynitride) on top of the anti-tunneling layer.
High work function gate electrode: This is typically made of doped polysilicon.
Overall structure: This creates what the patent refers to as an "oxide-nitride-nitride-oxide" (ONNO) or "oxide-nitride-oxide-nitride-oxide" (ONONO) stack when including the tunnel and blocking dielectrics.

Analysis of Prior Art References

The following patents and patent applications were cited as relevant prior art during the prosecution of the '240 patent. Each is evaluated for its potential to anticipate the independent claims (1, 13, and 18) of the '240 patent.

1. U.S. Patent No. 7,494,863 B2

Full Citation: US 7,494,863 B2, "Method for manufacturing a non-volatile memory," issued to Macronix International Co., Ltd.
Publication Date: February 24, 2009 (Filed: January 18, 2007).
Brief Description: This patent describes a method of fabricating a non-volatile memory device with a charge-trapping layer. It focuses on a process to form a charge-trapping structure with a high-K dielectric material. The structure involves a tunnel oxide, a silicon nitride charge-trapping layer, and a high-K dielectric blocking layer.
Potential Anticipation Analysis:
- Does it disclose the key features? The '863 patent discloses a multi-layer gate stack for a charge-trapping memory device. However, it does not explicitly describe the specific three-layer structure of an oxygen-rich nitride layer, an anti-tunneling oxide, and an oxygen-lean nitride layer as required by the '240 patent's claims. While it teaches the use of silicon nitride and high-K dielectrics, it does not detail the specific compositional variations (oxygen-rich vs. oxygen-lean) or the insertion of an "anti-tunneling" oxide layer between two distinct nitride layers.
- Conclusion: The '863 patent is relevant background art but does not appear to anticipate the claims of the '240 patent. It lacks the specific "arranged as in the claim" structure of the multi-layer charge trapping region, which is a crucial limitation.

2. U.S. Patent No. 7,569,899 B2

Full Citation: US 7,569,899 B2, "Non-volatile memory device and method of fabricating the same," issued to Samsung Electronics Co., Ltd.
Publication Date: August 4, 2009 (Filed: November 1, 2007).
Brief Description: This patent details a non-volatile memory device that uses a charge trap layer with silicon nanocrystals embedded within a silicon nitride layer. The goal is to enhance charge trapping efficiency and data retention. The structure includes a tunneling insulating layer, a charge trap layer, and a blocking insulating layer.
Potential Anticipation Analysis:
- Does it disclose the key features? The '899 patent focuses on using silicon nanocrystals to improve the charge-trapping layer. It does not teach the specific layered structure of an oxygen-rich nitride, an anti-tunneling oxide, and an oxygen-lean nitride. The mechanism for charge storage is different, relying on the nanocrystals rather than the specific interfaces and compositions of the multi-layer nitride structure in the '240 patent.
- Conclusion: The '899 patent does not anticipate the claims of the '240 patent as it describes a different type of charge-trapping layer technology.

3. U.S. Patent No. 7,700,427 B2

Full Citation: US 7,700,427 B2, "Method of forming a non-volatile memory device," issued to Powerchip Semiconductor Corp.
Publication Date: April 20, 2010 (Filed: April 11, 2008).
Brief Description: This patent describes a method for forming a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type memory device. The process involves creating a charge trapping layer and then performing a thermal oxidation process to form a blocking oxide. The focus is on improving the quality of the interfaces between the layers.
Potential Anticipation Analysis:
- Does it disclose the key features? The '427 patent describes a standard ONO (Oxide-Nitride-Oxide) stack. It does not disclose the '240 patent's novel three-layer charge-trapping region with an oxygen-rich nitride, an anti-tunneling oxide, and an oxygen-lean nitride. The fundamental structure of the charge-trapping region is different.
- Conclusion: The '427 patent is related as it deals with SONOS-type memory, but it does not disclose the specific multi-layer charge-trapping structure and therefore does not anticipate the claims of the '240 patent.

4. U.S. Patent No. 8,633,537 B2

Full Citation: US 8,633,537 B2, "Memory transistor with multiple charge storing layers and a high work function gate electrode," issued to Cypress Semiconductor Corporation.
Publication Date: January 21, 2014 (Filed: July 1, 2012).
Brief Description: This patent is a direct parent to the '240 patent in the same family, sharing the same title and inventors. It describes the same core invention of a memory transistor with a multi-layer charge trapping region, including an oxygen-rich nitride layer, an oxygen-lean nitride layer, and potentially an anti-tunneling layer.
Potential Anticipation Analysis:
- Does it disclose the key features? As a parent patent in the same family, it discloses the same inventive concept. However, under 35 U.S.C. § 102, a patent cannot be anticipated by its own parent application from which it claims priority. This reference is part of the claimed invention's lineage, not prior art against it in the traditional sense for an anticipation rejection. It is cited for informational and continuity purposes.
- Conclusion: The '537 patent does not anticipate the '240 patent because it is part of the same patent family and does not predate the effective filing date.

5. U.S. Patent Application Publication No. US 2007/0096194 A1

Full Citation: US 2007/0096194 A1, "Nonvolatile semiconductor memory device," by artist: Lue.
Publication Date: May 3, 2007 (Filed: October 31, 2005).
Brief Description: This publication describes a non-volatile memory device with a charge-trapping structure that includes a "band-engineered" silicon nitride layer. The idea is to have different compositions within the nitride layer to create potential wells for more effective charge trapping.
Potential Anticipation Analysis:
- Does it disclose the key features? This reference comes conceptually close. It discusses varying the composition of the nitride layer to improve performance. However, it does not explicitly disclose the specific three-layer structure of an "oxygen-rich" nitride, a distinct "anti-tunneling" oxide layer, and an "oxygen-lean" nitride. While it mentions varying silicon and nitrogen ratios, the inclusion of the central oxide layer as a distinct anti-tunneling barrier between the two nitride layers is a key element of the '240 patent's claims that appears to be absent here.
- Conclusion: This is likely the most relevant prior art. While it discusses the general concept of a non-uniform charge trapping layer, it does not appear to explicitly teach all the elements of the '240 patent's independent claims in a single embodiment, particularly the distinct anti-tunneling oxide layer. Therefore, it would likely not be considered to anticipate the claims, although it could be relevant in an obviousness analysis under 35 U.S.C. § 103.

Summary of Prior Art Analysis

The prior art cited for US Patent 9,929,240 primarily relates to non-volatile memory devices with charge-trapping layers. While these references describe various ways to construct and improve such devices, none appear to explicitly disclose the complete combination of elements required by the independent claims of the '240 patent. The key innovation in the '240 patent is the specific three-layer charge-trapping region consisting of an oxygen-rich nitride layer, an anti-tunneling oxide layer, and an oxygen-lean nitride layer. This specific combination is not found in the cited prior art, and therefore, these references do not appear to anticipate the claims of US 9,929,240. An argument for anticipation would require showing that one of these references inherently or expressly discloses every single element of the claimed invention, arranged in the same way. Based on the available information, this seems unlikely.