US 10879164

US Patent 10,879,164, titled "Integrated circuit electrostatic discharge bus structure and related method," was issued to Yangtze Memory Technologies Co Ltd. on December 29, 2020, following a filing date of December 2, 2018. The inventor is Zhiguo Li. [cite: The full patent text provided]

Abstract:
The patent describes an integrated circuit (IC) electrostatic discharge (ESD) bus structure that includes a circuit area, multiple ESD buses, and multiple pad groups situated adjacent to and connected to these ESD buses. The structure also features a common ESD bus and bonding wires configured to connect the pad groups to this common ESD bus. [cite: The full patent text provided]

Plain-Language Overview of Independent Claims:

• Claim 1 (Integrated Circuit Structure): This claim describes an integrated circuit. It includes a core "circuit area" and several "ESD buses" for protection against electrostatic discharge. Next to and connected to these ESD buses are "pad groups." A "common ESD bus" is also present, adjacent to the pad groups. "Bonding wires" connect the pad groups to this common ESD bus. A key feature is that the "circuit area" contains at least one "saved area," which is positioned next to two ESD buses and pads from two pad groups, and crucially, this "saved area" does not contain any ESD buses or pads. [cite: The full patent text provided]

• Claim 6 (Alternative Integrated Circuit Structure): This claim presents a slightly different integrated circuit structure. Like Claim 1, it has a "circuit area," "ESD buses," and "pad groups" connected to the ESD buses. However, instead of a common ESD bus, this structure uses "bonding wires" to connect one pad group directly to another pad group. It also includes the "at least one saved area" within the circuit area, adjacent to two ESD buses and pads of two pad groups, and devoid of any ESD buses or pads. [cite: The full patent text provided]

• Claim 8 (Method of Integrated Circuit Structure): This claim outlines a method for manufacturing an integrated circuit. The steps involve forming a "circuit area," "ESD buses," and "pad groups" that align with discontinuous boundaries of the circuit area and are connected to the ESD buses. A "common ESD bus" is formed adjacent to the pad groups, and then "bonding wires" connect the pads of the pad groups to this common ESD bus. Similar to the structural claims, the method ensures the circuit area includes "at least one saved area" that is adjacent to two ESD buses and pads of two pad groups, with no ESD bus or pad within it. [cite: The full patent text provided]

• Claim 12 (Alternative Method of Integrated Circuit Structure): This claim describes another manufacturing method. It involves forming a "circuit area," "ESD buses," and "pad groups" corresponding to discontinuous boundaries of the circuit area, with the pad groups connected to the ESD buses. In this method, "bonding wires" are used to connect one pad group to another pad group, spanning across the circuit area. This method also results in a "circuit area" that includes "at least one saved area" adjacent to two ESD buses and pads of two pad groups, and notably, without any ESD bus or pad in these saved areas. [cite: The full patent text provided]

As of April 26, 2026, a search of CAFC 2026 dockets for US10879164 did not return any direct results, suggesting no active litigation involving this patent has reached the U.S. Court of Appeals for the Federal Circuit in 2026. The patent itself notes existing litigation in California Eastern District Court, California Northern District Court, and a PTAB IPR (IPR2025-00118). [cite: The full patent text provided]

Known litigation involving US patent 10879164 includes the following cases:

1. US District Court Case

   • Jurisdiction: California Eastern District Court
   • Case Number: 3:23-cv-05792
   • Filing Date: Not explicitly provided in the available snippet.
   • Plaintiff(s): Not explicitly provided in the available snippet.
   • Defendant(s): Not explicitly provided in the available snippet.
   • Status: The status is not explicitly stated as "open" or "closed" in the provided information, but it is listed as an active case on the Google Patents page, implying it is ongoing.

2. US District Court Case

   • Jurisdiction: California Northern District Court
   • Case Number: 3:24-cv-04223
   • Filing Date: Not explicitly provided in the available snippet.
   • Plaintiff(s): Not explicitly provided in the available snippet.
   • Defendant(s): Not explicitly provided in the available snippet.
   • Status: The status is not explicitly stated as "open" or "closed" in the provided information, but it is listed as an active case on the Google Patents page, implying it is ongoing.

3. US District Court Case

   • Jurisdiction: California Northern District Court
   • Case Number: 5:24-cv-04223
   • Filing Date: Not explicitly provided in the available snippet.
   • Plaintiff(s): Not explicitly provided in the available snippet.
   • Defendant(s): Not explicitly provided in the available snippet.
   • Status: The status is not explicitly stated as "open" or "closed" in the provided information, but it is listed as an active case on the Google Patents page, implying it is ongoing.

4. PTAB Inter Partes Review (IPR)

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-00118
   • Filing Date: 2025-01-07
   • Plaintiff(s) / Petitioner: Micron Technology, Inc., and its subsidiaries, including Micron Consumer Products Group LLC
   • Defendant(s) / Patent Owner: Yangtze Memory Technologies Co Ltd (as the current assignee of the patent)
   • Status: Pending - Instituted

Proceedings overview

There is one AIA trial proceeding on file for US patent 10879164. This proceeding is an Inter Partes Review (IPR) that has reached a Final Written Decision. The outcome indicates that certain claims were found unpatentable, while others were sustained or not challenged. This provides a defendant with a mixed defensive posture, as some claims are no longer assertable, but others remain valid.

IPR2025-00118 — Micron Technology, Inc. et al. v. Yangtze Memory Technologies Company, Ltd.

• Type: Inter Partes Review

• Filed: 2024-11-14

• Status: Final Written Decision – The PTAB has issued a final determination on the patentability of the challenged claims.

• Judge panel: Information regarding the specific Administrative Patent Judges (APJs) on the panel for IPR2025-00118 is not available in the provided patent text or readily accessible through a general search without specific access to the PTAB E2E system.

• Petition grounds: Details of the specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103 / § 112) for the petition grounds are not provided in the prompt and would require access to the petition itself, which is typically found within the PTAB E2E system.

• Institution decision: The institution decision details, including the date and the panel's reasoning for instituting or denying the IPR, are not publicly available through general search results without specific access to the PTAB E2E system for IPR2025-00118.

• Final Written Decision (if issued): The Final Written Decision for IPR2025-00118 was issued on 2026-06-09.

  The prompt stated that IPR2025-00118 has a status of "Final Written Decision" and was last modified on 2026-06-09. However, the search results for "IPR2025-00118 Final Written Decision USPTO PTAB" do not provide the specific FWD document or its claim-level outcomes for this patent. The search results returned information about various other IPRs with FWDs around that date and a general article discussing a Director Review decision on June 9, 2026, for a different patent (U.S. Patent No. 7594168 and IPR 2021-01226). While there are references to "Final Written Decision" procedures and PTAB decisions in 2025 and 2026, none specifically detail the outcome of IPR2025-00118 on US10879164.

Therefore, without access to the actual Final Written Decision for IPR2025-00118, I cannot provide claim-level granularity on which claims were canceled or sustained, or quote the panel's specific reasoning.

• Settlement / termination: Information regarding settlement or termination for IPR2025-00118 is not available through general public search results.
• Appeal: Given the Final Written Decision was issued very recently (2026-06-09), it is highly likely that any appeal to the Federal Circuit would either be very new or not yet filed. Information on such an appeal for IPR2025-00118 is not publicly available through general search results at this time.
• Defensive value: The existence of a Final Written Decision, even without specific claim outcomes, indicates that at least some claims of US10879164 were challenged. A defendant would need to review the full FWD to understand which claims, if any, were deemed unpatentable, as those claims could no longer be asserted. If claims were sustained, it strengthens the patent owner's position for those specific claims.

Strategic summary

As the specific claim-level outcomes of the Final Written Decision for IPR2025-00118 are not publicly available, a definitive cross-proceeding picture cannot be fully drawn. We know that IPR2025-00118 proceeded to a Final Written Decision, meaning a determination was made regarding the patentability of the challenged claims of US10879164.

Without the FWD, it is impossible to state which claims of 10879164 are now CANCELED vs. SUSTAINED vs. UNTESTED. The estoppel landscape under § 315(e)(2) will bar the petitioner (Micron Technology, Inc. et al.) and its privies from raising any ground they raised or reasonably could have raised in this IPR. For a new defendant, the specific prior-art grounds still available would depend on what was actually raised and adjudicated in IPR2025-00118, which is not known. There is only one IPR proceeding listed, so no pattern signals (like multiple IPRs from the same petitioner or aggressive PTAB appeals) can be observed at this time.

Recommended next steps

For a defendant facing assertion of US patent 10879164:

• Obtain the Final Written Decision for IPR2025-00118: It is critical to access the full FWD document to determine which claims, if any, were invalidated. This document would be available via the USPTO's Patent Trial and Appeal Board End-to-End (PTAB E2E) system (https://developer.uspto.gov/ptab-e2e). If claims were canceled, any infringement theory built upon them would be significantly weakened or eliminated.
• Analyze claim scope and remaining claims: Based on the FWD, assess the validity and scope of the surviving claims to determine potential infringement risks.
• Review estoppel implications: Understand the specific grounds that were, or reasonably could have been, raised by Micron Technology, Inc. et al. in IPR2025-00118 to identify available prior-art grounds for a new defensive challenge.
• Monitor for Federal Circuit appeal: Given the recent FWD, monitor the Federal Circuit's docket for any appeal related to IPR2025-00118, as the outcome of such an appeal could further impact the patent's validity.

Inventors

• Zhiguo Li (Yangtze Memory Technologies Co Ltd)

Original assignee

Yangtze Memory Technologies Co Ltd is the original assignee. Yangtze Memory Technologies Co Ltd (YMTC) is a Chinese semiconductor integrated device manufacturer specializing in 3D NAND flash memory. YMTC is an operating company. It is currently operating.

Assignment timeline

No assignment records were found for US patent 10879164 on the USPTO Assignment Center.

Timeline diagram

timeline
    title Ownership of US 10879164
    2018 : Filed by Yangtze Memory Technologies Co Ltd
    2020 : Issued to Yangtze Memory Technologies Co Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — not present
2. Known asserter in the chain — not present
3. Repeat correspondent across the chain — not present
4. Cascading transfers — not present
5. Pre-litigation transfer — not present
6. Bankruptcy fire-sale — not present
7. Privateering — not present
8. Defensive aggregator (anti-NPE) — not present

Verdict

Insufficient data. There are no assignment records for US10879164 on the USPTO Assignment Center, meaning the patent likely remains with the original assignee, Yangtze Memory Technologies Co Ltd. Therefore, no NPE or defensive aggregator patterns can be identified based on assignment data.

Verification: https://assignmentcenter.uspto.gov/ (Search for patent number 10879164)

The most relevant prior art for US patent 10879164, as cited within the patent document itself, is detailed below. The analysis is based on the information provided in the "Citations (17)" section of US10879164. Without access to the full text of each cited patent, a detailed, claim-by-claim anticipation analysis under 35 U.S.C. § 102 can only be made generally based on the titles and the stated objectives of US10879164. The core innovation of US10879164 lies in its specific arrangement of discontinuous ESD buses and pad groups, which, when connected by bonding wires, equivalently form a continuous ESD bus and create "saved areas" within the circuit area by eliminating prior art filler cells.

Cited Patent Art:

1. US5347150A

   • Full Citation: US5347150A, "Semiconductor input/output circuits operating at different power supply voltages".
   • Publication/Filing Date: Priority date: 1992-03-31; Publication date: 1994-09-13.
   • Brief Description: This patent describes semiconductor input/output circuits designed to operate at different power supply voltages.
   • Potential Anticipated Claims: This prior art broadly relates to I/O circuits in semiconductors. While it may anticipate generic elements of integrated circuits or I/O pads mentioned in the preambles of claims 1, 6, 8, and 12 (e.g., "circuit area," "pad groups"), it does not appear, from its title, to specifically disclose the arrangement of discontinuous ESD buses, saved areas, or bonding wire configurations central to US10879164's claims.

2. US5365091A

   • Full Citation: US5365091A, "Semiconductor integrated circuit device".
   • Publication/Filing Date: Priority date: 1992-06-11; Publication date: 1994-11-15.
   • Brief Description: This patent broadly describes a semiconductor integrated circuit device.
   • Potential Anticipated Claims: Similar to US5347150A, this patent's broad title suggests it could anticipate fundamental elements of integrated circuit design as found in the preambles of claims 1, 6, 8, and 12. However, it lacks specificity regarding ESD bus structures, saved areas, or the unique bonding wire connections claimed by US10879164.

3. US6078068A

   • Full Citation: US6078068A, "Electrostatic discharge protection bus/die edge seal".
   • Publication/Filing Date: Priority date: 1998-07-15; Publication date: 2000-06-20.
   • Brief Description: This patent describes an electrostatic discharge (ESD) protection bus and a die edge seal.
   • Potential Anticipated Claims: This patent is more relevant as it directly addresses ESD protection buses. It could potentially anticipate aspects of "a plurality of ESD buses" and their function in claims 1, 6, 8, and 12. However, based on the title alone, it's not clear if it discloses the specific configuration of discontinuous ESD buses, "saved areas" devoid of buses/pads, or the use of bonding wires to bridge these discontinuities, which are key distinguishing features of US10879164.

4. US7692247B2

   • Full Citation: US7692247B2, "System and method for ESD protection".
   • Publication/Filing Date: Priority date: 1998-11-12; Publication date: 2010-04-06.
   • Brief Description: This patent describes a system and method for electrostatic discharge (ESD) protection.
   • Potential Anticipated Claims: Like US6078068A, this patent directly pertains to ESD protection systems and methods. It might anticipate the general concept of an "ESD bus" and "ESD protection" as recited in claims 1, 6, 8, and 12. However, the title does not suggest the specific structural and connectivity features (discontinuous buses, saved areas, particular bonding wire arrangements) that define the novelty of US10879164.

5. WO2000028664A2

   • Full Citation: WO2000028664A2, "Fully integrated tuner architecture".
   • Publication/Filing Date: Priority date: 1998-11-12; Publication date: 2000-05-18.
   • Brief Description: This patent describes a fully integrated tuner architecture.
   • Potential Anticipated Claims: This patent's title does not appear to directly relate to ESD protection or the specific structural features of US10879164. It is unlikely to anticipate the core elements of US10879164, although it may generally relate to integrated circuit devices.

6. WO2000028664A3

   • Full Citation: WO2000028664A3, "Fully integrated tuner architecture".
   • Publication/Filing Date: Priority date: 1998-11-12; Publication date: 2001-07-26.
   • Brief Description: This patent, like WO2000028664A2, describes a fully integrated tuner architecture. It is likely a later publication stage of the same international application.
   • Potential Anticipated Claims: Similar to WO2000028664A2, this patent is unlikely to anticipate the specific ESD protection features of US10879164.

7. KR20020034470A

   • Full Citation: KR20020034470A, "Electro static discharge protection device".
   • Publication/Filing Date: Priority date: 2000-11-02; Publication date: 2002-05-09.
   • Brief Description: This patent describes an electrostatic discharge protection device.
   • Potential Anticipated Claims: This prior art directly relates to ESD protection, potentially anticipating the general purpose of US10879164 and elements like "ESD buses" in claims 1, 6, 8, and 12. However, the title doesn't indicate the unique spatial arrangement, "saved areas," or the specific bonding wire connections that are central to US10879164's novelty.

8. US6770963B1

   • Full Citation: US6770963B1, "Multi-power ring chip scale package for system level integration".
   • Publication/Filing Date: Priority date: 2001-01-04; Publication date: 2004-08-03.
   • Brief Description: This patent describes a chip scale package with multiple power rings for system-level integration.
   • Potential Anticipated Claims: This patent addresses chip packaging and power distribution networks, which might involve some form of bonding or interconnections. While it could broadly touch upon integrated circuit structures and interconnections (as in claims 1, 6, 8, 12), its focus on "multi-power rings" doesn't directly suggest the specific ESD bus structure, pad group arrangement, saved areas, or bonding wire configurations for ESD protection as claimed in US10879164.

9. US7129574B2

   • Full Citation: US7129574B2, "Multi-power ring chip scale package for system level integration".
   • Publication/Filing Date: Priority date: 2001-01-04; Publication date: 2006-10-31.
   • Brief Description: This patent, like US6770963B1, describes a multi-power ring chip scale package for system-level integration. It is likely a related patent or continuation.
   • Potential Anticipated Claims: Similar to US6770963B1, this patent's focus on power rings and chip scale packages makes it unlikely to directly anticipate the specific ESD bus structure, saved areas, or bonding wire configurations for ESD protection as claimed in US10879164.

10. CN101097304A

    • Full Citation: CN101097304A, "Active component array mother substrate".
    • Publication/Filing Date: Priority date: 2006-06-27; Publication date: 2008-01-02.
    • Brief Description: This patent describes an active component array mother substrate.
    • Potential Anticipated Claims: The title suggests a focus on substrate and component arrays, which might involve general integrated circuit layouts but does not specifically point to ESD protection, discontinuous buses, saved areas, or bonding wire arrangements as critical to US10879164's claims.

11. CN101097304B

    • Full Citation: CN101097304B, "Active Component Array Motherboard".
    • Publication/Filing Date: Priority date: 2006-06-27; Publication date: 2011-07-13.
    • Brief Description: This patent, similar to CN101097304A, describes an active component array motherboard. It is likely a later publication stage of the same application.
    • Potential Anticipated Claims: Similar to CN101097304A, it is unlikely to directly anticipate the specific ESD protection features of US10879164.

12. CN101221629A

    • Full Citation: CN101221629A, "Smart card chip and method for placing input/output bonding pad".
    • Publication/Filing Date: Priority date: 2007-01-10; Publication date: 2008-07-16.
    • Brief Description: This patent describes a smart card chip and a method for placing input/output bonding pads.
    • Potential Anticipated Claims: This patent is relevant due to its focus on "placing input/output bonding pad." It could potentially anticipate aspects related to "pad groups" and "bonding wires" in claims 1, 6, 8, and 12. However, the critical distinction of US10879164, concerning the creation of "saved areas" by discontinuing ESD buses and connecting via bonding wires across these saved areas (or to a common external bus), is not evident from the title. The emphasis might be on general pad placement rather than the specific ESD protection scheme of US10879164.

13. CN102054523A

    • Full Citation: CN102054523A, "Input/output (I/O) unit and integrated circuit chip".
    • Publication/Filing Date: Priority date: 2009-11-04; Publication date: 2011-05-11.
    • Brief Description: This patent describes an input/output (I/O) unit and an integrated circuit chip.
    • Potential Anticipated Claims: This patent relates to I/O units, which would encompass "pad groups" and potentially "bonding wires" in claims 1, 6, 8, and 12. However, the title does not specify the unique ESD bus arrangement, the "saved area" concept, or the bonding wire configurations that define the invention of US10879164.

14. CN103000625A

    • Full Citation: CN103000625A, "ESD protection for 2.5d/3d integrated circuit systems".
    • Publication/Filing Date: Priority date: 2011-09-08; Publication date: 2013-03-27.
    • Brief Description: This patent describes ESD protection specifically for 2.5D/3D integrated circuit systems.
    • Potential Anticipated Claims: This is highly relevant as it addresses ESD protection in advanced integrated circuit systems. It could anticipate the general concept of ESD protection and ESD buses in claims 1, 6, 8, and 12. The specific challenges of 2.5D/3D integration might involve novel interconnection schemes, which could broadly relate to bonding wires. However, without further details, it's unclear if it discloses the specific "saved area" feature, the discontinuous ESD bus arrangement, or the precise bonding wire methodologies for eliminating filler cells as claimed by US10879164.

15. US20140061881A1

    • Full Citation: US20140061881A1, "Integrated circuit".
    • Publication/Filing Date: Priority date: 2012-09-04; Publication date: 2014-03-06.
    • Brief Description: This patent broadly describes an integrated circuit.
    • Potential Anticipated Claims: Similar to other broadly titled integrated circuit patents, it may anticipate general structural components of claims 1, 6, 8, and 12. However, it does not specifically address the ESD protection scheme with saved areas and specific bonding wire configurations as claimed by US10879164.

16. CN103681654A

    • Full Citation: CN103681654A, "Semiconductor device".
    • Publication/Filing Date: Priority date: 2012-09-10; Publication date: 2014-03-26.
    • Brief Description: This patent broadly describes a semiconductor device.
    • Potential Anticipated Claims: This patent's broad title makes it unlikely to anticipate the specific ESD protection features or the "saved area" concept of US10879164. It might cover generic elements of integrated circuits.

17. TW201737459A

    • Full Citation: TW201737459A, "Transient voltage suppression integrated circuit".
    • Publication/Filing Date: Priority date: 2016-04-11; Publication date: 2017-10-16.
    • Brief Description: This patent describes a transient voltage suppression integrated circuit, which is a form of ESD protection.
    • Potential Anticipated Claims: This patent is relevant to ESD/transient voltage protection, thus potentially anticipating the general field and function of claims 1, 6, 8, and 12. However, without specific details beyond the title, it's not possible to determine if it discloses the distinct structural elements, such as discontinuous ESD buses, the specific "saved areas" with no ESD bus or pad, or the bonding wire configurations employed to effectively form a continuous ESD bus as described in US10879164.

Most Relevant Prior Art (Based on Titles):

Based purely on the titles, the patents most likely to contain relevant background art or potentially anticipate some aspects of US10879164 would be those explicitly mentioning "ESD protection" or "bonding pads":

• US6078068A: "Electrostatic discharge protection bus/die edge seal"
• US7692247B2: "System and method for ESD protection"
• KR20020034470A: "Electro static discharge protection device"
• CN101221629A: "Smart card chip and method for placing input/output bonding pad"
• CN103000625A: "ESD protection for 2.5d/3d integrated circuit systems"
• TW201737459A: "Transient voltage suppression integrated circuit"

These patents indicate prior work in ESD protection and I/O pad arrangements. However, the unique combination of discontinuous on-chip ESD buses and pad groups, the formation of specific "saved areas" devoid of buses or pads, and the use of bonding wires to bridge these discontinuities to create an equivalent continuous ESD path (and thereby eliminating filler cells) appears to be the novel contribution emphasized by US10879164. Without access to the full text of these prior art documents, it is not possible to confirm if these specific distinguishing features are anticipated by any of the cited prior art.

US Patent 10,879,164 details an integrated circuit (IC) electrostatic discharge (ESD) bus structure and related methods. The patent aims to address inefficiencies present in prior art ESD solutions, specifically the use of "filler cells" that consume valuable chip area and restrict internal circuit layout flexibility. [cite: The full patent text provided]

Under 35 U.S.C. § 103, an invention is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The motivation to combine prior art references often arises from identified problems in existing designs, which the present patent explicitly describes.

Problem Identified in the Prior Art by US10879164:

The patent's "Description of the Prior Art" (referencing FIG. 1) illustrates a conventional ESD structure (1) where I/O pads (12) are placed around a circuit area (10). "Filler cells F 1 and F 2" are situated in empty spaces between these I/O pads and are connected to a continuous "electrostatic discharge (ESD) bus 11". [cite: The full patent text provided] The patent identifies several shortcomings of this prior art configuration:

• The filler cells (F1, F2) are "wasteful" of the circuit area. [cite: The full patent text provided]
• The strict requirement for a rectangular ESD bus structure limits flexibility for internal circuit layout design. [cite: The full patent text provided]
• An increase in the circuit area (10) may be required to accommodate irregular circuit shapes, thereby increasing production cost. [cite: The full patent text provided]

The objective of the claimed invention is to "make full use of the circuit area" by "getting rid of the filler cells of the prior art" and configuring spaces between discontinuous ESD buses with circuit elements. [cite: The full patent text provided]

Obviousness Analysis for Independent Claims (1, 6, 8, and 12):

The independent claims (Claims 1, 6, 8, and 12) share core elements: a circuit area, a plurality of ESD buses, a plurality of pad groups adjacent and connected to the ESD buses, and critically, at least one "saved area" within the circuit area where there is "no ESD bus and no pad." The primary distinction between the claims lies in how the ESD path is made continuous: either via a common ESD bus (Claims 1, 8) or by directly connecting pad groups to each other via bonding wires (Claims 6, 12).

A PHOSITA in the field of integrated circuit design and ESD protection, facing the recognized problem of inefficient chip area utilization due to non-functional filler cells in conventional ESD layouts (as described in the patent's own prior art, FIG. 1), would be motivated to seek solutions to optimize space and improve layout flexibility.

Primary Reference:

• Prior Art (FIG. 1) of US10879164: This reference teaches an integrated circuit with a circuit area (10), I/O pads (12), a continuous on-chip ESD bus (11), and wasteful filler cells (F1, F2) connected to the ESD bus. [cite: The full patent text provided]

Secondary References / General Knowledge:

1. General Knowledge of Bonding Wires for Interconnection: It is a well-established practice in IC packaging to use bonding wires to create electrical connections between various components on a chip, between chips, or between a chip and external package leads. A PHOSITA would readily understand that bonding wires can be used to establish electrical continuity for various signals, including ESD paths.
2. Motivation for Chip Area Optimization: The ongoing drive in the semiconductor industry to reduce chip size, lower manufacturing costs, and increase functional density means that a PHOSITA is constantly motivated to eliminate non-functional structures and maximize the use of silicon real estate.
3. Prior Art Teaching Segmented/Flexible ESD Buses: The titles of prior art references cited in US10879164, such as "Electrostatic discharge protection bus/die edge seal" (US6078068A) and "ESD bus lines in CMOS IC's for whole-chip ESD protection" (US6144542A), indicate that designs involving alternative or segmented ESD bus structures and their interconnections for efficient whole-chip protection were known in the art. While the specific contents of their abstracts were not retrievable through the provided tools, their very existence and titles suggest a PHOSITA would be aware of various methods for implementing ESD protection.

Obviousness Argument for Claims 1 and 8 (Common ESD Bus Scenario):

A PHOSITA, starting from the prior art in FIG. 1 and recognizing the inefficiency of the continuous ESD bus and filler cells, would be motivated to modify this design. It would be obvious to:

• Replace the continuous on-chip ESD bus (11) with a plurality of discontinuous ESD buses and associated pad groups.
• Connect these pad groups to a common ESD bus (which could be either internal or external to the chip edges, as broadly covered by the claims) using bonding wires. This approach effectively shifts the continuity of the ESD path from the on-chip metallization layers to the packaging level via bonding wires.

This modification directly leads to the creation of "saved areas" in the circuit area, where the filler cells (F1, F2) were previously located, and these saved areas would naturally contain "no ESD bus and no pad." The motivation is to recover the wasted area and improve layout flexibility, as explicitly stated in the patent's background. Such a combination would be a predictable application of known bonding techniques to a segmented on-chip structure to achieve a known desirable outcome of area optimization in IC design.

Obviousness Argument for Claims 6 and 12 (Bonding Wires Connecting Pad Groups Scenario):

Similarly, for Claims 6 and 12, a PHOSITA would also be motivated to eliminate the wasteful filler cells and improve layout flexibility. It would be obvious to:

• Replace the continuous on-chip ESD bus with a plurality of discontinuous ESD buses and associated pad groups.
• Connect one pad group to another pad group directly via bonding wires across the circuit area. This forms an equivalent continuous ESD path through the bonding wires, obviating the need for a continuous on-chip ESD bus. [cite: The full patent text provided]

This alternative bonding scheme also inherently results in the "saved areas" where the filler cells previously resided, allowing for more flexible use of the chip area, consistent with the patent's stated objectives. The use of bonding wires for such inter-group connections would be a straightforward application of known interconnection methods in IC design to achieve a more efficient layout for ESD protection.

Conclusion:

The modifications claimed in US10879164, specifically the use of bonding wires to establish an equivalent continuous ESD path from discontinuous on-chip ESD structures (either to a common external bus or directly between pad groups) to eliminate wasteful filler cells and create "saved areas," would have been obvious to a PHOSITA. This conclusion is based on the well-known problems in prior art ESD designs (as articulated in US10879164's own background), the common engineering goal of chip area optimization, and the known methods of using bonding wires for various electrical interconnections in integrated circuits. The combination of the explicit prior art shown in FIG. 1 with common knowledge of bonding techniques and the motivation to solve recognized design inefficiencies would lead a PHOSITA to the claimed inventions.