US 6144542

I'll search for authoritative information on this patent number, including any 2026 CAFC activity.

Let me run targeted searches for any litigation or CAFC docket activity involving this patent.

Let me do one final targeted check for any 2026 appeal docket specifically naming this patent.

Search results and patent summary — US 6,144,542

Important caveat up front: I searched for USPTO records, litigation, and any 2026 Court of Appeals for the Federal Circuit (CAFC) docket activity naming patent 6,144,542. I found no evidence of any CAFC 2026 docket, appeal, or pending litigation involving this patent. This is consistent with the patent's recorded status: "Expired – Lifetime," with an anticipated expiration of 2018-12-15, meaning the patent term ended roughly seven years before the current date. Because the patent is expired, it is not a plausible subject of 2026 infringement appeals. I did not locate a CAFC docket number for this patent, and I cannot fabricate one. If a specific 2026 CAFC case is suspected, a docket number, case caption, or party name would be needed to verify it.

Note on identifier interpretation (per your strict rule): The identifier you gave, 6144542, maps literally to US 6,144,542 A. A search also surfaced an unrelated Japanese patent, JP 6144542 B2 (a "中堀掘削機" / core-boring excavator held by 株式会社シロタ), and an unrelated Lithuanian registry entry — those are different documents and are not the subject here.

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Bibliographic data (US 6,144,542 A)

Source for bibliographic fields: Google Patents page for US6144542A (https://patents.google.com/patent/US6144542/en) and the full patent text supplied in the prompt; mirrored listing at https://uspto.report/patent/grant/6144542.

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Abstract (as issued)

"In this invention, a new whole-chip ESD protection scheme with the ESD buses has been proposed to solve the ESD protection issue of the CMOS IC having a large number of separated power lines. Multiple ESD buses, which are formed by the wide metal lines, have been added into the CMOS IC having a large number of separated power lines. The bi-directional ESD-connection cells are connected between the separated power lines and the ESD buses, but not between the separated power lines. The ESD current on the CMOS IC with more separated power lines are all conducted into the ESD buses, therefore the ESD current can be conducted by the ESD buses away from the internal circuits and quickly discharged through the designed ESD protection devices to ground. By using this new whole-chip ESD protection scheme with the ESD buses, the CMOS IC having more separated power lines can be still safely protected against ESD damages."

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Plain-language overview of the invention

The patent addresses a known weakness in CMOS chips that use multiple separated power/ground lines (common in mixed-voltage, noise-sensitive designs). The prior art (Figs. 1–2) chained diode strings directly between adjacent power lines. With many separate supplies, an ESD strike had to traverse a long chain of diode strings to reach ground, causing slow discharge and possible internal damage.

The invention replaces that "ladder" of inter-power-line diode strings with dedicated, low-impedance ESD buses (wide metal lines) running around the chip, plus bi-directional ESD-connection cells that tie each local power/ground line to a bus, and ESD clamp devices that sit between the buses. During normal operation the cells/clamps stay off (no power loss); during an ESD event they rapidly steer the discharge current onto the bus network and out to ground — allegedly requiring the current to pass through at most two connection cells and one clamp regardless of how many supplies exist.

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Independent claims (plain language)

There are three independent claims in the 37-claim set: claim 1, claim 10, and claim 25. (The remaining 34 claims are dependents that specify the connection-cell and clamp-device structures — PSCR/NSCR cells, and NCLSCR/PCLSCR clamps with optional series diodes.)

Claim 1 — Apparatus (multiple circuits, two ESD buses).
An anti-ESD apparatus for an IC comprising:

• multiple internal circuits, each with an input pad, an output pad, and a pair of power lines (a first power line and a second power line);
• multiple first ESD bi-directional connection devices and multiple second ESD bi-directional connection devices;
• a first ESD bus coupled to the first connection devices, and a second ESD bus coupled to the second connection devices; and
• an ESD clamp device coupled between the first and second ESD buses, for discharging current routed from the internal circuits through the first connection devices onto the first bus and through the second connection devices onto the second bus.

In short: plural power domains, each domain's supply rails tied to one of two common ESD buses via bi-directional cells, with a clamp bridging the two buses.

Claim 10 — Apparatus (two circuit groups / mixed voltage, three ESD buses).
This is the mixed-voltage extension. It comprises:

• multiple first internal circuits (first/second power lines) and multiple second internal circuits (third/fourth power lines);
• four sets of ESD bi-directional connection devices (first through fourth), each connecting a respective group's power line to a bus;
• a first ESD bus coupled to the first set;
• a second ESD bus coupled to both the second and third sets;
• a third ESD bus coupled to the fourth set; and
• multiple ESD clamp devices coupling the first, second, and third buses together, to discharge current from the internal circuits through the first connection devices to the first bus and through the second/third connection devices to the second bus.

In short: two voltage domains sharing a common (typically ground) middle bus, with three buses total, bridged by multiple clamps. Dependent claims 23–24 tie this to specific supplies (2.5 V / 0 V and ~5 V / 0 V — note the slight inconsistency in the claim language, which describes the third line as "about a 5-Volt").

Claim 25 — Method (ESD discharging).
A method for electrostatic discharge of an IC, comprising the steps of:

1. conducting an ESD current from an internal circuit into a power line of that internal circuit;
2. conducting the ESD current into an ESD bi-directional connection device;
3. conducting the ESD current into a first ESD bus of the IC;
4. conducting the ESD current into an ESD clamp device (to discharge it); and
5. conducting the ESD current into a second ESD bus of the IC, to unify the voltage level of the first and second ESD buses.

Dependent claims 26–27 add that each bus is a metal line routed around the periphery of the IC; claims 28–33 specify the cell/clamp circuit topologies; claims 34–37 cover single-bus cell variants (NSCR or PSCR device stacks in parallel with a diode, optionally with a series diode per SCR).

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Uncertainty / limitations

• No CAFC 2026 docket found. I could not identify any 2026 Federal Circuit matter tied to 6,144,542. Given the patent expired in 2018, that absence is expected, but I cannot prove a negative exhaustively from public search alone. Treat the "no 2026 CAFC activity" statement as "not found," not as certified absence.
• Assignee of record is TSMC per the assignment filed at issue; I did not find evidence of a later recorded reassignment, but I did not exhaustively check the USPTO assignment database for the full chain of title.
• Claim language quirks (e.g., "cathode" typo'd as "cathode/cat hode," and "an a node" in claim 5) are reproduced literally from the issued text; they are not transcription errors on my part.
• Bibliographic values are drawn from the Google Patents record and the patent text provided in your prompt; where those are the authoritative source for this analysis, I relied on them directly.

I'll search for litigation involving US patent 6144542.

Let me search more targeted litigation databases.

Summary of Findings

Based on my searches of patent litigation resources (including CourtListener/RECAP, Unified Patents litigation portal, Docket Alarm, Justia Dockets, and general web sources), I found no litigation involving U.S. Patent No. 6,144,542. I could not identify any district court case, ITC investigation, or PTAB proceeding in which US 6,144,542 was asserted, challenged, or otherwise at issue.

Patent identification (for confirmation — no auto-correction applied)

Why litigation appears to be absent

1. Patent term already expired. The Google Patents record shows an anticipated expiration of 2018-12-15 (20 years from the 1998 filing date) and a status of "Expired – Lifetime." A patent that has been expired for more than seven years cannot be the basis for ongoing infringement litigation, and no past suits surfaced.
2. Assignee profile. The patent was held by TSMC, a semiconductor foundry that historically has used its patent portfolio defensively/cross-licensing rather than as a plaintiff in assertion campaigns. I found no record of TSMC asserting this patent.
3. No third-party assertion found. The patent is not among the patents in the TSMC-vs-NPE cases that did appear in my searches (e.g., Advanced Integrated Circuit Process LLC v. TSMC, Alidouble Inc. v. TSMC), nor did any assertion-entity campaign referencing it appear.

Important caveats / limitations

• Negative finding, not a certified clearance. "No litigation found" reflects the sources I could reach via web search; it is not proof that no litigation ever existed. Litigation from the 2000–2018 window involving this patent could exist in sealed records, in state courts, or in databases not surfaced by these searches.
• Confusion-risk adjacent results. My searches returned other cases and documents that are not this patent and should not be attributed to it — for example, a Japanese patent "特許第6144542号" (a Japanese excavation-machine patent), and U.S. cases involving different patents such as the '542 patent (U.S. Patent No. 6,144,542 confusion with "the 542 Patent" in the MTL v. SanDisk complaint, which concerned an unrelated '542 patent). I deliberately did not treat these as litigation of US 6,144,542.
• Recommendation for verification. To confirm a true negative, I would recommend direct queries against:
  • Unified Patents Portal – https://portal.unifiedpatents.com/litigation
  • CourtListener/RECAP – https://www.courtlistener.com (search docket text for "6,144,542" and "6144542")
  • USPTO PTAB – https://ptacts.uspto.gov (for any IPR/PGR involving the patent)
  • PACER and Docket Navigator (paid) for district court and ITC records.

Conclusion: No known litigation involving US Patent No. 6,144,542 was identified. If you need a litigation-grade clearance, I would need you to authorize a direct database pull (Unified Patents / Docket Navigator / PACER), which provides more complete coverage than open web search. I did not fabricate any case details, as none were found.

Proceedings overview

Total AIA trial proceedings on U.S. Patent No. 6,144,542: zero. The structured "PTAB proceedings on file" block (USPTO Open Data Portal ingest) returns no IPR, PGR, or CBM proceeding, and targeted web searching surfaced none either. There is therefore no breakdown to report — no active trial, no claims-invalidated outcome, no settlement, no institution-denial decision, and no Federal Circuit appeal of any PTAB decision, because no proceeding ever reached the Board. The defensive bottom line for a defendant is the mirror image of a "hardened patent": 6,144,542 is not a PTAB-tested patent at all — it is an untested, now-expired TSMC patent. That cuts both ways. Nothing is invalidated, but nothing is confirmed by the Board either, and the absence of any IPR in the fourteen years the patent was enforceable is itself a strong signal that no one ever needed to clear it as an assertion risk.

This aligns with, and does not contradict, the previously generated sections of this analysis: the litigation summary found no district court, ITC, or PTAB activity, and the PTAB block reports an empty set. The two are consistent.

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No proceedings — verification by proceeding type

Because the requested per-proceeding template presupposes at least one docket number and I will not invent one, here is the by-type check instead:

Similarly-numbered patents — do not attribute these to 6,144,542

Web searching for "542 patent" + "IPR" is heavily polluted, and the results were all false positives. Flagging them so no one imports the wrong outcome onto TSMC's patent:

• The Genzyme rAAV "542 patent" (a gene-therapy patent asserted in Genzyme v. Novartis, D. Del. No. 21-1736-RGA; later the subject of IPR2025 petitions by Sarepta, e.g., petitions at https://ptacts.uspto.gov/ptacts/public-informations/petitions/1558103 and .../1558104). An unrelated case — the exhibits state the '542 patent there issued in 2015 and was challenged in two IPRs filed in early 2023, both of which were denied institution on the merits. None of that is 6,144,542, which issued in 2000.
• U.S. Reissue Patent RE45,542 — Kingston Technology Co. v. Memory Technologies, LLC, IPR2019-00644. Different number, different patent, different owner.
• U.S. Patent No. 7,341,542 — IPR2017-00493. Unrelated (exercise equipment).
• JP 特許第6144542号 (JP 6144542) — a Japanese excavation-machine ("中堀掘削機") patent. Coincidental number collision.
• U.S. Application Serial No. 15/297,542 — an unrelated application discussed in a cert petition.

I explicitly did not let any of these contaminate the finding.

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Strategic summary

Claim status of 6,144,542: all 37 claims stand UNTESTED. There is no FWD, no certificate of cancellation, and no reexamination certificate. Nothing supports a statement that any of independent claims 1, 10, or 25 (the apparatus and method independents) — or any dependent claim 2–9, 11–24, 26–37 — has been canceled or confirmed by the Office. Anyone who tells you "the '542 claims are invalidated" or "the '542 claims survived IPR" is almost certainly talking about one of the look-alike patents above. If you are drafting an invalidity position, you are starting from a clean PTAB slate and relying on your own prior art, not on an estoppel record.

Estoppel landscape: effectively empty. There is no § 315(e)(2) estoppel because there is no petitioner and no FWD. Two practical consequences follow. First, no one is estopped from anything — there is no "reasonably could have raised" bar tied to this patent. Second, and more importantly, IPR is a poor fit now: the patent expired on 2018-12-15 ("Expired – Lifetime," anticipated expiration per the Google Patents record), which means (a) the term of enforceable exclusionary conduct is over, and (b) any suit would be limited to past conduct, subject to the six-year damages lookback of 35 U.S.C. § 286 — i.e., infringement occurring roughly between 2012-12-15 and 2018-12-15. A § 315(b) one-year-bar clock only starts on service of a complaint, and none was found. PGR and CBM are off the table for the reasons in the table above. So the realistic defensive posture is "do not spend IPR money on this patent" — the leverage, if any, is on the § 286 time bar and on the patent's 1998-vintage prior art, litigated in court if a demand ever appears.

Pattern signals: none. No petitioner filed once, let alone repeatedly. No Unified Patents or other defensive aggregator appears anywhere in the chain — the patent record shows only the original TSMC assignment (Taiwan Semiconductor Manufacturing Co., Ltd., assignors Ker, Ming-Dou and Chang, Hun-Hsien) and no subsequent reassignment to an assertion entity. TSMC has not appealed anything, because there was nothing to appeal. This is the profile of a purely internal, defensive corporate patent that was never monetized — consistent with the litigation summary's independent finding of no assertion activity.

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Recommended next steps

If you are a defendant and someone has put 6,144,542 in a demand letter or complaint:

1. Demand the correct identification document. Request the plaintiff state the patent number, title, and issue date. A demand citing 6,144,542 with any reference to gene therapy, AAV, rAAV, Elevidys, Zolgensma, or Genzyme is a misidentification — the real target is the Genzyme '542 patent, and the Genzyme/Sarepta IPR record (institution denied on the merits in two 2023-filed IPRs) is your starting evidence. See https://ptacts.uspto.gov/ptacts/public-informations/petitions/1558103 and .../1558104.
2. Check § 286 and expiration. For 6,144,542: filing 1998-12-15, grant 2000-11-07, expiration 2018-12-15. Any damages theory must be confined to a window that closed in 2018, and the patent cannot support injunctive relief today.
3. Verify the record yourself before acting. Run the number in USPTO Patent Public Search (https://ppubs.uspto.gov) and USPTO PTAB E2E / PTABIS (https://ptacts.uspto.gov) using both formats — 6,144,542 and 6144542 — and in CourtListener (https://www.courtlistener.com) docket-text search. There is no FWD to link to, because none exists; the correct citation is the text of the patent itself at https://patents.google.com/patent/US6144542/en, including the 37-claim set.
4. If you want a formal negative clearance for a litigation or diligence file, the open web is not sufficient. Authorize a Docket Navigator / PACER / Unified Patents pull. My finding is a negative finding from public search plus an empty ODP record, not a certified clearance.

If you are evaluating this patent as prior art or as a portfolio asset: note that it is a frequently cited reference (Google Patents lists 111 citing documents, including Broadcom, Analog Devices, Macronix, and TSMC follow-on filings), so its disclosure is doing work as prior art even though its claims were never tested. That citation traffic is the patent's real legacy — not any PTAB outcome.

Caveats I will not paper over: I found no proceeding, but "none found" from web search and an ODP ingest is not proof of a universal negative. A pre-AIA inter partes reexamination or an ex parte reexamination from the 2000–2018 window could in principle exist in a file wrapper not surfaced here; the absence of a reexamination certificate on the face of the Google Patents record argues against it, but a full Patent Center file-wrapper pull would be the confirmatory step. I did not fabricate any proceeding number, judge panel, FWD disposition, or appeal docket.

I'll attempt to pull the assignment record from the primary sources and cross-reference.

Let me dig for the actual reel/frame record and any post-issuance chain.

Let me make one more targeted attempt at the reel/frame and any post-issuance records.

Ownership & Assignment Analysis — US 6,144,542

Source limitation up front (read this first): The USPTO Patent Assignment Search / Assignment Center is a JavaScript-rendered application whose per-patent result tables are not indexed by search engines, and no third-party mirror (uspto.report, Justia, Google Patents "Legal Events") surfaced a reel/frame number for this patent. I was therefore able to confirm which transactions exist (via the USPTO-derived reassignment record echoed on Google Patents) but not the reel/frame, correspondent-of-record, or recorded date for them. I am not going to invent reel/frame numbers or attorney names. Where a field is unverified, I say so explicitly. The single verified entry is the original inventor→TSMC assignment; no post-issuance assignment of any kind surfaced.

Cross-referenced: Google Patents legal events (US6144542, https://patents.google.com/patent/US6144542/en), everypatent.com bibliographic record, Patent Leaderboard inventor profile, and the ISCAS 2000 co-authored paper for inventor affiliation.

Inventors

Notes / patterns:

• This is a classic academic–foundry collaboration, not a startup inventor team. Ker (NCTU) supplied the ESD circuit architecture for which he is widely cited; Chang (TSMC) was the foundry-side co-inventor. Their joint publication record (CICC 1998 "Novel cascode NCLSCR/PCLSCR design…"; J. Electrostatics 1997/1999) maps almost 1:1 onto this patent's disclosure.
• No unusual departure pattern. Chang remained at TSMC well past the 12-month window — he appears as a TSMC-affiliated co-author in 2000 and Patent Leaderboard credits him with 17 TSMC-assigned US patents through May 2006. There is no evidence of inventors exiting the assignee within 12 months, which is the fire-sale precursor the task asks me to look for. Not present.

Original assignee

• Entity on the issued patent: Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC), Hsinchu, TW.
• Line of business: the world's largest dedicated semiconductor foundry — pure-play wafer fabrication (not a products-at-retail company; it sells foundry capacity, and this patent covers on-chip ESD‑protection circuitry implemented in its customers' CMOS designs).
• Did they ship a product embodying the claims? Indirectly, and this matters for the NPE analysis: TSMC does not sell packaged ESD circuits, but the claimed ESD-bus/SCR scheme is design IP that would be embodied in the CMOS ICs TSMC fabricates for customers. It is a process/design-IP asset held by a large operating foundry, not a discrete product SKU.
• Current status: Operating. TSMC remains an active, publicly traded foundry (NYSE: TSM). No merger, dissolution, or bankruptcy touching this patent was found. It has not been an NPE-style plaintiff on this patent.

Assignment timeline

Chronological, with the verification status of each field made explicit:

• 1998-12-15 (executed) / recorded date not retrievable — Reel/Frame: NOT RETRIEVABLE from indexed sources
  • Conveyance: Assignment (inventor-to-assignee; the standard pre-issuance "ASSIGNMENT OF ASSIGNOR'S INTEREST" type)
  • Assignor: KER, MING-DON; CHANG, HUN-HSIEN
  • Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
  • Correspondent: not verified. (For context only — the prosecution attorney of record printed on the face of the patent is Nath & Associates, Harold L. Novick, per everypatent.com. That is the patent-prosecution attorney, not confirmed as the assignment-recording correspondent, so I am not treating it as a correspondent-of-record finding.)
  • Context: Original assignment of inventors' rights to the employer/foundry, executed on the same day the application was filed (filing date 1998-12-15). This is a routine employment/collaboration assignment, not a transfer-to-asserter.
  • Source: Google Patents "Legal Events" / reassignment entry, 1998-12-15: "Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. … Assignors: CHANG, HUN-HSIEN, KER, MING-DON" (this field reproduces USPTO reassignment data).

No further recorded assignments were found. Google Patents shows only the single 1998-12-15 assignment and thereafter only the 2000-11-07 grant and the 2018-12-15 anticipated expiration. There is no second link, no LLC, no security interest, no merger, no release, and no change of name. Per the task's own rule, this absence is itself the finding: the original assignee (TSMC) appears to remain the owner of record.

Timeline diagram

timeline
    title Ownership of US 6144542
    1998 : Filed by Ker and Chang
         : Assigned to TSMC
    2000 : Patent issued
    2018 : Term expired

(The 1998 row carries two stacked events per the requested colon convention. No post-issuance events exist to plot.)

NPE / troll-pattern signals

Verdict

Insufficient data (per the task's own definition: "no records, or only the original assignment").

The record contains exactly one transaction — the 1998-12-15 inventor→TSMC assignment (Assignors: KER, MING-DON; CHANG, HUN-HSIEN; Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.), reproduced from USPTO reassignment data via Google Patents — followed by the 2000-11-07 grant and the 2018-12-15 term expiration. There is no post-issuance assignment, no shell-entity transfer, no known asserter, and no defensive-aggregator termination. Functionally this means TSMC, an operating foundry, remained the owner of record and never asserted or divested the patent; but because a full-chain reconstruction requires more than the single original link, the correct formal call is "Insufficient data," not "NPE."

Verification / how to close the gaps. My one material gap is the reel/frame and recorded date for the 1998-12-15 assignment, which I could not pull from indexed sources. To confirm directly:

• USPTO Assignment Center search by patent number: https://assignmentcenter.uspto.gov/ (enter 6144542 under "Patent Number")
• Legacy USPTO Assignment Search: https://assignment.uspto.gov/patent/index.html
• USPTO Patent Center for the file wrapper (assignment papers are in the application file): https://patentcenter.uspto.gov

Caveat (negative finding, not a certified clearance): "No post-issuance assignment found" reflects the sources reachable here; a 1998-era paper-filed assignment could exist that has not been indexed into the electronic reassignment database. If you need a litigation-grade chain-of-title, authorize a direct Assignment Center / Patent Center pull and, if needed, order the certified assignment abstract.

No contradiction with the earlier section: this ownership analysis is consistent with the prior litigation summary (no litigation identified) — an unasserted patent that never left its original operating assignee is exactly the profile you would expect to see no suits against.

I'll search for authoritative USPTO and patent records for each reference. Let me start with the target patent and its cited U.S. patents.

I have data on several references. Let me search for the remaining cited U.S. patents.

Task A — USPTO record for 6144542 (verified, exact number only)

I searched for the literal identifier 6144542 and confirmed the record is US 6,144,542 A — not the similarly-numbered Japanese patent (JP 6144542 B2) or other look-alikes. The record matches what was already established in the earlier sections of this analysis (Google Patents / Justia / uspto.report / EveryPatent all return the same document):

Sources: https://patents.justia.com/patent/6144542 ; https://uspto.report/patent/grant/6144542 ; https://patents.google.com/patent/US6144542/en ; http://www.everypatent.com/comp/pat6144542.html

Cross-reference / no contradiction: The prior sections correctly noted the patent is expired (2018) and that no 2026 CAFC docket exists. Nothing in this search contradicts that. I do not repeat that litigation material here.

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Task B — Methodology and an important caveat on "citations" for 6144542

The instruction "look at each patent citation for 6144542" is ambiguous between two different citation sets, so I separate them explicitly:

• Backward citations (the prior art the applicant cited ON the '542 patent) — these are the relevant prior art and are the subject of Task B. They appear in the patent's Background section as references [1]–[16] (text reproduced in the prompt and at https://patents.justia.com/patent/6144542). Of these, [8]–[15] are U.S. patents; [1]–[7] and [16] are non-patent literature.
• Forward citations ("Cited By," 111 documents) — these cite the '542 patent. Because they post-date the 1998 priority date, they are not prior art and I do not treat them as such. (E.g., US 6,385,116; US 6,638,492; US 6,674,129; US 7,193,251; and the Analog Devices family.)

Caveat on § 102 vs. § 103: Anticipation under 35 U.S.C. § 102 requires a single reference to disclose every element of a claim, arranged as in the claim. My review of the cited references indicates that none of them alone plainly anticipates independent claims 1, 10, or 25; their realistic exposure is under § 103 (obviousness) or as evidence of the state of the art. I flag this honestly rather than asserting anticipation that the references do not support. I was also cut off by a tool-step limit before I could pull full text of four of the eight U.S. references (5,426,323; 5,530,612; 5,610,791; 5,625,280); those entries are marked [not fully verified].

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Task C — U.S. patent references cited on the '542 patent

[8] US 5,616,943 — Electrostatic discharge protection system for mixed voltage application specific integrated circuit design

• Full citation: H. P. Nguyen and J. D. Walker, U.S. Pat. No. 5,616,943. Inventors: Hoang P. Nguyen; John D. Walker. Assignee: AT&T Global Information Solutions Company.
• Dates: Filed 1994-06-13 (Ser. 08/259,240; CIP of Ser. 08/129,224, filed 1993-09-29); issued 1997-04-01. A continuation issued as US 6,515,839. European counterpart: EP 0 688 079 B1.
• Description: A mixed-voltage ASIC ESD system using several over-voltage device types to create conduction paths between different power lines — shunt diodes between the ground lines of different supplies and between pads and supply lines; SCR protection between pads and ground; and thick-field devices between different V_DD lines. Describes isolated power/ground buses for I/O vs. core, and a "pseudo-V_DD bus."
• Relevance / potential § 102: The closest cited art on point for independent claim 10 (two circuit groups, mixed voltage, four power lines, multiple ESD conduction devices) and relevant to claim 1's "plural power domains." It discloses ESD conduction between power lines, which is the very arrangement the '542 patent describes as its prior art (Figs. 1–2). However, the record I retrieved does not show a disclosure of two dedicated ESD buses bridged by a bi-directional ESD connection cell architecture; the '943 devices bridge power lines directly. Positions: high § 103 relevance to claims 1 and 10; not a clean § 102 anticipation on the reviewed text.
• Source: https://patentimages.storage.googleapis.com/5d/2b/37/65e36b18d3556c/US6515839.pdf ; https://www.patentleaderboard.com/patent/5616943

[9] US 5,196,981 — ESD protection scheme

• Full citation: J. R. Kuo, U.S. Pat. No. 5,196,981. Inventor: James R. Kuo. Assignee: National Semiconductor Corporation (Santa Clara, CA).
• Dates: Filed 1990-12-28 (Ser. 635,874); issued 1993-03-23.
• Description: Energy-dissipation circuitry providing an ESD path between any combination of two pins of an IC (multi-channel transceiver example). Combines conventional shunt diodes with a secondary circuit: an NPN bipolar transistor between Vcc and logic ground, a Zener + resistor divider driving its base, a reverse-path Schottky diode, and back-to-back Schottky diode pairs between separate ground pads / supply pads (e.g., logic ground to BTL grounds, Vcc to quiet Vcc).
• Relevance / potential § 102: This is generic multi-ground/multi-supply pin-to-pin ESD handling. It is not directed to multiple internal circuits with dedicated high-conductivity ESD buses, and discloses no "ESD connection cell" or "ESD clamp between buses." Positions: background art; not anticipatory of claims 1/10/25.
• Source: http://patentimages.storage.googleapis.com/79/1f/57/c415803742c9f6/US5196981.pdf ; http://www.everypatent.com/comp/pat5196981.html

[10] US 5,290,724 — Method of forming an electrostatic discharge protection circuit

• Full citation: J. G. Leach, U.S. Pat. No. 5,290,724. Inventor: Jerald G. Leach. Assignee: Texas Instruments Incorporated.
• Dates: From Ser. 08/948,074, filed 1992-09-21 (continuation of Ser. 677,028, 1991-03-28, abandoned); issued March 1994 (per the patent's own citation and the related U.S. Pat. No. 5,591,992, which is a division thereof). Related division: US 5,591,992 (filed 1995-06-07).
• Description: ESD protection using cascaded bipolar transistors in series with a field-effect transistor between first and second bond pads; also an output buffer divided into sections, with an ESD protection circuit triggerable by a substrate voltage, and resistive connections from the buffer sections to a bond pad.
• Relevance / potential § 102: Device/triggering-level art (substrate-triggered BJT/SCR, split output buffer). It does not teach a multi-domain ESD bus topology. Positions: background art; not anticipatory of claims 1/10/25.
• Source: http://www.everypatent.com/comp/pat5290724.html ; https://patentimages.storage.googleapis.com/76/fa/92/c373e84e49b816/US5591992.pdf

[11] US 5,301,084 — Electrostatic discharge protection for CMOS integrated circuits

• Full citation: W. Miller (as cited in the '542 patent), U.S. Pat. No. 5,301,084, "Electrostatic discharge protection for CMOS integrated circuits." (Public records list the inventor as Bernard D. Miller; assignee AT&T.)
• Dates: Cited as April 1994; grant day not independently verified in my search [partially verified].
• Description: A CMOS ESD network built around multiple conductive supply/ground rings. Claim 15 (retrieved) recites a V_CC power bus plus first (V_SS), second (D_VCC) and third (D_VSS) spaced rings, with clamp devices coupled between rings (bus↔ring, ring↔ring), plus lateral bipolar transistors to route ESD between rings. A resistor–capacitor-coupled MOS clamp "kick-starts" a lateral bipolar at low, non-destructive breakdown.
• Relevance / potential § 102: This is the most structurally analogous cited patent to the '542 bus concept, because it teaches distributed rings/buses with clamps connected between rings — the "ESD clamp device coupled between the first ESD bus and the second ESD bus" element of claim 1. What it does not show is the claimed bi-directional ESD connection device placed between each separated power line and the bus (its inter-ring elements are clamps/lateral devices, not the PSCR/NSCR bi-directional cells). Positions: strongest § 103 candidate against claim 1's bus+clamp sub-combination; not a clean § 102 anticipation of claim 1 as a whole.
• Source: http://www.everypatent.com/comp/pat5301084.html

[12] US 5,426,323 — Integrated semiconductor circuit with ESD protection

• Full citation: W. Reczek and H. Terletzki, U.S. Pat. No. 5,426,323.
• Dates: Cited as June 1995 [not fully verified — full text not retrieved before tool-step limit].
• Description: Per its title and the context in which the applicant cited it (alongside [8] and [11], in the sentence about using diodes, MOS, BJTs or field-oxide devices to connect separated power lines), it concerns on-chip ESD protection of a semiconductor circuit, generally in a multi-supply context. I could not verify its specific disclosure.
• Relevance / potential § 102: Category "diodes/MOS/BJT/field-oxide devices used to connect separated power lines" per the applicant's own characterization. Positions: background art; anticipation assessment withheld pending full-text review.

[13] US 5,530,612 — Electrostatic discharge protection circuits using biased and terminated PNP transistor chains

• Full citation: T. J. Maloney, U.S. Pat. No. 5,530,612.
• Dates: Cited as June 1996 [not fully verified].
• Description: ESD protection using biased/terminated PNP transistor chains (i.e., diode/transistor-chain clamps), the family of structures the applicant cites for coupling separated power lines.
• Relevance / potential § 102: Addresses clamp/element design for power-supply ESD coupling, not a bus topology. Positions: background art; not anticipatory of claims 1/10/25.

[14] US 5,610,791 — Power sequence independent electrostatic discharge protection circuits

• Full citation: S. H. Voldman, U.S. Pat. No. 5,610,791.
• Dates: Cited as March 1997 [not fully verified].
• Description: ESD protection that functions independent of power-up/power-down sequence across multiple supplies — i.e., cross-domain ESD robustness.
• Relevance / potential § 102: Concepts relevant to mixed/multiple-supply ESD, but no dedicated ESD bus with bi-directional cells. Positions: background art.

[15] US 5,625,280 — Voltage regulator bypass circuit

• Full citation: S. H. Voldman, U.S. Pat. No. 5,625,280.
• Dates: Cited as April 1997 [not fully verified].
• Description: A bypass circuit associated with a voltage regulator (on-chip supply) — cited for multi-supply ESD handling.
• Relevance / potential § 102: Peripherally related supply-domain art. Positions: background art.

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Task D — Non-patent references cited on the '542 patent (also prior art, dated pre-1998)

Because the applicant cited these alongside the patents, they must be assessed too.

§ 102 note on the NPL: References [3] and [4] are the applicants'/inventors' own prior publications and are the most likely to be cited against broad concept-level claims. If either discloses "plural internal circuits, each with input/output pads and separated supply rails, with dedicated conductive ESD paths coupling the rails to a common conductor and a clamp therebetween," it could support a § 102(a)/(b) rejection of at least the concept embodied in claim 1 (and the method of claim 25) — but on the titles/abstracts alone I cannot establish element-by-element completeness. This needs full-text verification of Refs. [3] and [4], which is the single highest-value follow-up.

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Task E — Additional prior art surfaced during this search (not on the '542 face, but relevant)

These are not "citations of 6144542," but a complete § 102/§ 103 picture for this patent should include them:

1. EP 0 740 344 B1 — "Method and apparatus for coupling multiple independent on-chip V_DD busses to an ESD core clamp." Filed 1995-04-24; EP grant published 2002-07-24; assignee Conexant Systems. It expressly proposes "a single clamp circuit … for IC's with multiple V_DD busses by coupling the various V_DD busses to an ESD clamped V_DD bus or pseudo-V_DD bus via diodes" — i.e., multiple supply buses → a common ESD-clamped bus with one clamp. This is arguably the closest structural prior art to the '542 two-bus + single-clamp concept. Notably, this same document cites the IRW "Whole Chip Protection" report (the '542 patent's own Ref. [3]). Source: https://patentimages.storage.googleapis.com/c9/57/ed/106d9b5ffea19e/EP0740344B1.pdf
2. US 6,515,839 — continuation of US 5,616,943 (Nguyen/Walker); same mixed-voltage multi-supply ESD conduction-path disclosure. Source: https://patentimages.storage.googleapis.com/5d/2b/37/65e36b18d3556c/US6515839.pdf
3. US 6,737,346 / US 5,548,135-type bus-clamp art surfaced (ESD circuits connected to internal bus lines and clamping transients between bus lines) — relevant to claim 1's bus+clamp element, but I could not confidently verify the exact document number from the retrieved page, so I flag it as [unverified] rather than cite it.

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Task F — Bottom line for the analyst

• Exact-number search succeeded: 6144542 = US 6,144,542 A (TSMC, Ker & Chang), expired 2018. No confusion with the Japanese JP 6144542.
• The applicant cited 8 U.S. patents as prior art ([8]–[15]). None of the eight, on the text I retrieved, discloses the full claimed dedicated-ESD-bus + bi-directional-connection-cell + inter-bus-clamp architecture:
  • US 5,301,084 (Miller) is the strongest single-reference § 103 candidate against claim 1's "ring/bus + clamp-between-buses" element.
  • US 5,616,943 (Nguyen/Walker) is the strongest § 103 candidate against claim 10 (mixed-voltage, multiple power lines).
  • US 5,196,981 (Kuo) and US 5,290,724 (Leach) are generic multi-pin/multi-ground and device-level art.
  • [12]–[15] (Reczek/Terletzki; Maloney; Voldman ×2) are supply/clamp-design art; [not fully verified] — retrieve full text before relying on any § 102 position.
• The applicant's own NPL Refs. [3] (1994 IRW) and [4] (1997 CICC) are the most dangerous true prior art for a § 102 analysis of the broad concept and should be pulled in full text.
• Best external prior art identified: EP 0 740 344 B1 (Conexant), which teaches multiple V_DD buses coupled via diodes to a single ESD-clamped bus — directly on the '542 claim 1/10 concept, though its coupling element (diodes) differs from the claimed bi-directional SCR cells.
• § 102 vs § 103 honesty: On the reviewed evidence I could not establish that any single reference anticipates independent claims 1, 10, or 25; the references appear to support § 103 rejections (and, for [3]/[4], possible § 102 once full text is checked). I have not fabricated element-level disclosures for references whose full text I could not retrieve.

Unverified items to close out: full text of US 5,426,323, US 5,530,612, US 5,610,791, US 5,625,280; exact grant date of US 5,301,084; and full text of NPL Refs. [3] and [4].

I'll ground this § 103 analysis by verifying the content of the key prior-art references cited in the patent's own Background section. Let me run targeted searches.

Let me check whether pre-1998 art teaches a shared/discharge "ESD bus" concept, and verify the remaining cited references.

Obviousness Analysis — U.S. Patent No. 6,144,542 under 35 U.S.C. § 103

Built on the previously generated Patent Summary and Litigation Summary. I do not repeat their content except where needed to anchor the analysis.

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0. Two threshold notes (contradictions / caveats flagged)

1. Date contradiction (flagged per instructions). The system context states "Today's date is 2026-10-01." The current task header states "Current Date: April 26, 2026." These are inconsistent. Because the patent expired 2018-12-15 (expiration is >7 years past under either date), the discrepancy does not affect the § 103 analysis. I proceed on the assumption that "today" is a 2026 date and that the filing/priority date of 1998-12-15 is the critical date for prior-art qualification.
2. Scope of "Prior Art section." The Google Patents page's "Prior Art" block contains only keywords (esd, coupled, bus, devices, nscr), the prior-art date (1998-12-15), and a "Cited By (111)" list. Critically, the 111 "Cited By" documents are forward citations and are NOT § 102/§ 103 prior art against this patent. The operative prior art is the set the patent's own Background cites — [1]–[16] — plus any art that independently qualifies by date (I identify one such highly material, apparently-uncited reference below). I treat it accordingly.

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1. Legal framework applied

• 35 U.S.C. § 103 (pre-AIA, since the application was filed 1998-12-15): a claim is obvious if the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention.
• Graham v. John Deere factors: scope/content of the prior art; differences; level of ordinary skill; secondary considerations.
• KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007): predictable variations, "obvious to try," a finite number of identified, predictable solutions, and design incentives/"market demand" can supply the reason to combine. A combination of known elements is obvious where the improvement is merely the predictable use of prior-art elements according to their established functions.
• MPEP § 2143 rationales relied on below: (A) combining prior-art elements according to known methods to yield predictable results; (B) simple substitution of one known element for another; (C) use of a known technique to improve a similar device in the same way; (D) applying a known technique to a known device ready for improvement; (E) "obvious to try"; (F) design incentives / market forces.
• Level of ordinary skill (assumed): a B.S. in EE (or equivalent) with ~2–3 years of IC/ESD circuit-design experience, or an M.S. with ~1 year, familiar with SCR/MOS ESD devices, power-rail clamps, and mixed-voltage chip design. This is a mature, well-populated art with extensive EOS/ESD Symposium literature.

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2. Prior art of record and effective dates

Additional qualifying art identified (not among refs [1]–[16]):

Ref [X] issued >1 year before the 1998-12-15 filing and is therefore § 102(b)/§ 103 prior art. It does not appear among references [1]–[16] or in the "Cited By (111)" list, so it does not appear to have been before the examiner. I flag this because it materially shifts the obviousness picture — but I am careful to note that my characterization of [X] is drawn from live search results, and if any specific limitation of Claim 1 is genuinely absent from [X], it must be supplied by the secondary references.

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3. What is actually new — element-by-element

3.1 Independent claim 1 (apparatus; plural circuits + two ESD buses + clamp)

Difference over the art: the two-bus topology in which separate connection cells tie the high rail to bus-1 and the low rail to bus-2, with a clamp bridging the two buses, and the bidirectional character of the cells. Every individual element is in the art; the combination is the point of novelty.

3.2 Independent claim 10 (two circuit groups, mixed voltage, three buses, plural clamps)

Adds: first/second internal-circuit groups on (first, second) and (third, fourth) power lines; four sets of connection cells; three buses (bus-1 high/low group; bus-2 common; bus-3 high group); plural clamps interconnecting all three. This is the mixed-voltage extension. Taught by:

• [X] and/or [8] (multiple, different supplies with coupling devices and a common return),
• [13] (mixed 3.3/5 V supplies with diode-string coupling), [14]/[15] (multi-rail), and
• [4] (Ker 1997 CICC) (mixed-mode multi-supply whole-chip scheme — inventor's own prior art).

Dependent claims 23–24 tie the buses to specific rails (2.5 V/0 V; ~5 V/0 V) — a mere recitation of the typical mixed-voltage partition the art already describes (e.g., [13]'s 3.3/5 V, [X]/[16]'s mixed supplies). Note the earlier-flagged claim-language inconsistency ("about a 5-Volt" vs. "is charged about a 5-Volt"); it does not change the § 103 picture.

3.3 Independent claim 25 (method)

Steps: internal circuit → power line → bi-directional connection device → first ESD bus → ESD clamp → second ESD bus ("to unify voltage level…"). This is the operational description of the apparatus of claim 1 (indeed, the patent's Fig. 3 narrative describes exactly this current path). [X] + [8]/[13] supply the steps; the "unify voltage level" step is the ordinary consequence of equalizing the two buses through the clamp — a predictable result. Dependent claims 26–27 (buses are metal lines routed around the chip) recite the known practice of using wide metal power/ESD routing (big diodes and wide metal lines are required — verbatim from [X]'s description).

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4. Proposed § 103 grounds (combinations + motivation)

Ground 1 — Claim 1 obvious over Worley [X] in view of Maloney [13] and Nguyen & Walker [8]

• [X] teaches a common ESD bus (V_esd) to which all power pads couple through devices, with one shared clamp on the bus — i.e., the "conduct ESD current onto a dedicated bus rather than daisy-chaining between rails" concept, with an express area-efficiency motivation.
• [13] and the admitted Figs. 1-2 art teach bi-directional coupling between separated power lines (including ground-to-ground).
• [8] teaches coupling ground lines of different supplies and placing protection devices between different power terminals.

Reason to combine (KSR/MPEP 2143 A, C, D, F): (i) both [X] and the patent address the same problem (ESD in chips with multiple independent supplies) and the same field (on-chip ESD); (ii) [X]'s stated goal — reducing the number/size of clamps and providing a robust, low-impedance discharge path — is the very purpose the patent states; (iii) using a low-impedance metal bus as the current conduit is a known technique applied to a known structure awaiting improvement; (iv) substituting bi-directional coupling cells (known from [13]/Figs. 1-2) for [X]'s unidirectional diodes to handle both polarities of pin-to-pin stress is a simple, predictable substitution of a known element for its known function. Result: plural rails → bus-1 (high side) and bus-2 (ground side) via bi-directional cells, with a clamp across the buses — claim 1.

Ground 2 — Claim 1 obvious over Nguyen & Walker [8] in view of Worley [X] (or [16]) and Dabral [6]

[8] supplies the mixed-voltage, multi-supply platform with protection devices between different power terminals; [X] supplies the shared bus + single clamp architecture and its motivation; [6] supplies coupling diodes for ESD and noise immunity. Same rationales.

Ground 3 — Claims 6–9, 19–22, 30–33 (clamp topologies) obvious

The clamp sub-claims recite cascoded SCRs (NCLSCR/PCLSCR), an ESD-detection circuit, an inverter driving PCLSCR gates, and series diodes to reduce device count.

• The problem (keep the clamp off when the normal bus-to-bus difference could otherwise hold an SCR in its low-impedance state; block latch-up) and its solution (stack the SCR holding voltages; add series diodes) are predictable engineering, and the patent itself supplies the governing equation n ≧ V_diff / V_hold (≈1 V/SCR; ≈1.7 V/SCR+diode).
• Cascoding/stacking to withstand a stated voltage is a known, finite, predictable technique (cf. stacked/diode-string clamps in [13] and stacked MOSFET clamps generally; SCR ESD devices in [8] and WO 95/10855).
• [13] teaches using biased/terminated diode strings as power-supply clamps precisely by stacking PNP/diode stages to partition voltage — the same "add diodes to the string to reduce the number of active devices" idea claimed in 8/9/21/22.

⇒ MPEP 2143 (B),(C),(E): simple substitution + obvious-to-try among a finite set of known ESD-clamp topologies.

Ground 4 — Claims 2–5, 11–18, 28–29, 34–37 (bi-directional cell topologies) obvious

The cells recite PSCR or NSCR pairs (SCR-based bi-directional connection devices) and, for the single-bus variant, an NSCR/PSCR stack in parallel with a diode. The patent's own Background admits that the art already used "diodes, MOS's, BJT's, or field-oxide devices … to connect the separated power lines of a CMOS IC" (citing [9]–[16]). SCR-based ESD devices were generic in the art ([8] uses SCR; WO 95/10855 STSCR; [16] forward-diode/MOSFET philosophy). Selecting an SCR (rather than a diode/BJT/thick-oxide device) as the bi-directional element, and stacking to withstand V_DD−V_SS during normal operation, is a predictable design choice with a finite set of candidates. Ground: [X]/[8]/[13] in view of the admitted knowledge of SCR/BJT/MOS/field-oxide ESD elements [9]–[16].

Ground 5 — Claim 10 (three buses, mixed voltage) obvious

[X] (multi-supply coupling to a shared bus) + [8] (multi-supply, protection devices between different terminals) + [13] (mixed 3.3/5 V diode-string coupling) + the admitted [1]–[4] whole-chip/multi-supply art. Three buses are simply the natural scaling of the two-bus scheme to two high-voltage domains sharing a common ground bus — a predictable variation (KSR "finite number of identified, predictable solutions").

Ground 6 — Claim 25 (method) obvious

[X] + [8]/[13] + the ordinary operation of the clamp. The steps are the operational counterpart of the apparatus; the terminal step (conducting current to the second bus "to unify voltage level") describes the inherent, expected equalization across the clamp. MPEP 2143 (A): combining these elements yields nothing more than the predictable sum of their known functions.

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5. Motivation-to-combine narrative (consolidated)

A PHOSITA in December 1998 had, in hand:
(i) the problem — multi-supply/mixed-voltage CMOS ICs are ESD-fragile, and diode-string "ladders" between every adjacent rail scale poorly ([1]–[4], [13]);
(ii) an area- and performance-driven solution space already pointing at a shared bus + shared clamp ([X], [16], [7]);
(iii) mixed-voltage multi-rail coupling devices ([8], [13], [14], [15]); and
(iv) a well-stocked toolbox of bi-directional coupling elements and clamps ([6], [9]–[12]).

Combining (ii)+(iii)+(iv) to arrive at "plural rails → bi-directional cells → dedicated buses → clamp across the buses" is the predictable use of known elements for their known functions, with the same design incentive (fewer series elements → shorter discharge path; area efficiency; noise isolation) that both the art and the patent articulate. Under KSR, that is enough.

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6. Potential rebuttals and counter-arguments I would expect (and my assessment)

• "Prior art teaches away — Figs. 1-2 use inter-rail diode strings, not buses; and the art criticizes added devices." Weak. The patent's Background's criticism is of the diode-string-ladder limitation (too many series elements), which is itself the motivation to move to a bus — i.e., it points in the direction of the invention, not away. [X] expressly counsels the bus.
• "Bi-directional vs. unidirectional cells is a structural difference." Met by [13]'s explicit bidirectional Vsso–Vss coupling and the admitted Figs. 1-2 bi-directional diode strings.
• "Two dedicated ESD buses are not shown." This is the strongest non-obviousness argument, and it turns on whether the common ground/V_SS network in [X]/[8] (and/or the bus in the single-bus embodiment of the patent itself, Fig. 12) is fairly read as the "second ESD bus." This is a genuine claim-scope/art-mapping question; reasonable minds could differ, and I flag it as the crux.
• Secondary considerations. I found no evidence of commercial success, copying, licenses, or industry praise with a nexus to these claims, and no litigation (consistent with the Litigation Summary and the 2018 expiry). Absent such evidence, it cannot rebut the prima facie case. If a patentee were to raise long-felt need, the counter is that the need was already recognized and partially solved in the art ([1]–[4], [X], [8]).

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7. Conclusion

• Claims 1, 10, 25 (independent) and the great majority of dependents are, in my assessment, vulnerable under § 103, most strongly via Worley U.S. 5,654,862 [X] in view of Maloney U.S. 5,530,612 [13] and Nguyen & Walker U.S. 5,616,943 [8], with the admitted prior art (Figs. 1-2) and Dabral [6] as further support.
• [X] (U.S. 5,654,862) is the single most damaging reference because it independently discloses the core concept — a shared ESD bus fed by per-rail coupling devices and terminated by one clamp — with an express area-efficiency motivation, and it appears not to have been before the examiner (it is absent from refs [1]–[16] and from the "Cited By" list).
• The most defensible non-obviousness position for a patent owner is the two-dedicated-ESD-buses requirement of claim 1 (and its three-bus analogue in claim 10): whether the common ground network in the art constitutes a "second ESD bus" connected through "second bi-directional connection devices" is the pivotal, contestable mapping.
• Confidence: Moderate-to-high on the direction of the § 103 conclusion (the claimed architecture is a predictable combination of known elements). Lower confidence on the exact reference mapping for the "second ESD bus" without full text of each reference; I have not read the complete specifications of [X], [8], [13], or the un-verified refs [9]–[12], and I have not reproduced any claim charts that would require word-for-word quotations I cannot confirm.

Limitations / what I did not do: I did not conduct a full prior-art search beyond the record and the targeted lookups above; I did not verify Kuo [9], Leach [10], Miller [11], or Reczek [12] in detail; and I did not perform claim charts element-by-element against complete reference texts. Any of those could change the strength of a specific ground. I did not fabricate reference content; where I characterize a reference (e.g., [X]), it is grounded in the search results cited inline.

Sources: Google Patents, US6144542A (https://patents.google.com/patent/[US6144542](/patent/US6144542)/en); Justia, US6144542 (https://patents.justia.com/patent/6144542); US5654862/EP0740344 (https://uspto.report/patent/grant/5654862; http://www.everypatent.com/comp/pat5654862.html; http://data.epo.org/publication-server/rest/v1.2/patents/EP0740344NWA2/document.html); US5616943/EP0688079 (http://www.everypatent.com/comp/pat5616943.html); US5530612 (https://patents.justia.com/patent/5530612); Maloney & Dabral, EOS/ESD 1995 (https://www.mendeley.com/catalogue/3300e7c1-af22-3c35-8f73-bec9cb635f3a/); Worley et al., EOS/ESD 1995 (https://www.semanticscholar.org/paper/0b1f801f62e3e71a9df4d48729d02006b400ea41).