US 8076194

US Patent 8076194, titled "Method of fabricating metal oxide semiconductor transistor," was issued on December 13, 2011, from an application filed on May 18, 2010. The current assignee is Marlin Semiconductor Ltd, though it was originally assigned to United Microelectronics Corp. The inventors are Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, and Hsuan-Hsu Chen.

Abstract:
A method of fabricating a MOS transistor is disclosed. The method includes providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, with the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, where the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, where a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

Plain-language overview of independent claims:

• Independent Claim 1: This claim describes a method for making a Metal Oxide Semiconductor (MOS) transistor. The key steps involve creating a gate on a semiconductor substrate, then putting a protective layer over the entire substrate, including the gate. Next, a trench (recess) is formed in the substrate next to the gate. An epitaxial layer is then grown in this trench, extending above the original surface of the semiconductor substrate. Finally, a spacer is formed on the side of the gate, which also extends over part of this raised epitaxial layer, such that the point where the epitaxial layer and the spacer meet is above the substrate's surface.

• Independent Claim 10: This claim focuses on a method for fabricating a Complementary Metal Oxide Semiconductor (CMOS) transistor, which involves both "first conductive" (e.g., PMOS) and "second conductive" (e.g., NMOS) transistor areas separated by an isolation structure. Similar to Claim 1, it involves forming a gate in each area and then a first protective layer covering the substrate and gates. A first recess is created in the first conductive transistor area next to its gate, and a first epitaxial layer is grown in this recess, extending above the substrate surface. A spacer is then formed on the sidewall of each gate and over a portion of this first epitaxial layer, with the contact surface between the epitaxial layer and spacer being above the substrate surface.

No specific litigation related to US patent 8076194 was found in the CAFC 2026 dockets. However, Google Patents notes that there is pending litigation, specifically PTAB case IPR2026-00061 filed, and mentions "Family has litigation" with a link to Darts-ip. This indicates that while no CAFC dockets were found, other legal proceedings are active.

Known litigation involving US patent 8076194 as of April 26, 2026, includes:

1. PTAB Inter Partes Review (IPR)

• Plaintiff(s): Not specified in the provided snippet (Petitioner will be listed on Unified Patents portal).
• Defendant(s): Marlin Semiconductor Ltd (Current Assignee of US8076194)
• Jurisdiction: Patent Trial and Appeal Board (PTAB), U.S. Patent and Trademark Office
• Case Number: IPR2026-00061
• Filing Date: The IPR case number IPR2026-00061 indicates it was filed in fiscal year 2026. Specific date to be confirmed from the source.
• Outcome or Current Status: Pending

To confirm the specific filing date and the petitioner, further details would need to be accessed directly from the Unified Patents portal link provided in the patent record.

No other specific litigation cases (such as District Court or CAFC cases) directly involving US patent 8076194 are immediately apparent from the patent details, other than the general indication of "Family has litigation" and "First worldwide family litigation filed" which links to a Darts-ip page for the patent family. Further investigation of the Darts-ip platform for the specific patent US8076194B2, and additional searches on CAFC and PACER, would be necessary to identify any other relevant cases.

As a patent attorney, I have investigated the litigation landscape for US Patent 8076194. Here's a summary of known litigation:

1. PTAB Inter Partes Review (IPR2026-00061)

• Case Name: IPR2026-00061 (Specific parties not fully detailed without direct portal access, but the patent owner is Marlin Semiconductor Ltd).
• Plaintiff(s): Petitioner(s) unknown without direct access to the Unified Patents portal for IPR2026-00061.
• Defendant(s): Marlin Semiconductor Ltd. (Current Assignee of US8076194B2).
• Jurisdiction: Patent Trial and Appeal Board (PTAB), U.S. Patent and Trademark Office.
• Case Number: IPR2026-00061.
• Filing Date: The case number indicates a filing in fiscal year 2026, consistent with the current date of April 26, 2026.
• Outcome or Current Status: Pending.

2. U.S. International Trade Commission (ITC) Investigation (337-TA-1443)

• Case Name: Certain Foreign-Fabricated Semiconductor Devices, Products Containing the Same, and Components Thereof (337-TA-1443).
• Plaintiff(s): Longitude Licensing Limited and Marlin Semiconductor Limited (subsidiaries of IPValue Management).
• Defendant(s): [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), Broadcom Inc., Lenovo Group Limited, Motorola Mobile Communication Technology Ltd, Motorola (Wuhan) Mobility Technologies Communication Company Limited, OnePlus Technology (Shenzhen) Co., LTD., Taiwan Semiconductor Manufacturing Company Limited (TSMC), and Qualcomm Inc.
• Jurisdiction: U.S. International Trade Commission (USITC).
• Case Number: 337-TA-1443.
• Filing Date: The complaint was filed on February 18, 2025, and supplemented on February 21, 2025, and March 10, 2025.
• Outcome or Current Status: An investigation was instituted on March 21, 2025, and an evidentiary hearing is scheduled for February 2, 2026. The ITC has not yet made a decision on the merits. While the Google Patent page does not explicitly list 8076194 as one of the asserted patents, other sources indicate that Marlin Semiconductor is litigating a portfolio of former United Microelectronics Corporation (UMC) patents in this ITC investigation and companion district court cases, which are directed toward semiconductor devices and manufacturing technology. The patent 8076194 is part of this portfolio of former UMC patents acquired by Marlin Semiconductor.

3. U.S. District Court Cases (Companion to ITC 337-TA-1443)

• Plaintiff(s): Longitude Licensing Limited and Marlin Semiconductor Limited.
• Defendant(s):
  • Western District of Texas (1:25-cv-00215): Apple, Broadcom, and Qualcomm.
  • Eastern District of Texas (2:25-cv-00171): Lenovo (Motorola Mobile Communication), OnePlus, and TSMC.
• Jurisdiction: U.S. District Court for the Western District of Texas and U.S. District Court for the Eastern District of Texas.
• Case Numbers: 1:25-cv-00215 (Western District of Texas); 2:25-cv-00171 (Eastern District of Texas).
• Filing Date: These complaints were filed in early 2025, prior to the ITC complaint (e.g., "Roughly one week after suing Apple... in a Western District of Texas complaint... IPValue... subsidiaries... filed a complaint before the International Trade Commission (ITC)").
• Outcome or Current Status: These are companion cases to the ITC investigation (337-TA-1443) and are ongoing.

It's important to note that Marlin Semiconductor Limited acquired US8076194 from United Microelectronics Corporation (UMC) in a June 2021 assignment. Therefore, any litigation initiated by Marlin Semiconductor Limited involving this patent would be after this assignment date. Previous litigation involving UMC, such as the trade secret case with Micron Technology, did not directly involve patent 8076194.

Proceedings overview

There is one active AIA trial proceeding on US patent 8076194, currently in the "Trial Instituted" status. This means the patent's validity is presently being challenged before the PTAB, and no claims have been definitively invalidated or sustained yet. For a defendant, this indicates an ongoing challenge to the patent, and the outcome of this IPR will significantly impact the patent's strength.

IPR2026-00061 — Taiwan Semiconductor Manufacturing Company Ltd. v. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

• Type: Inter Partes Review
• Filed: 2025-12-05
• Status: Trial Instituted (Trial has been initiated by the PTAB)
• Judge panel: [Information not found in public search results for this pending IPR institution decision. Therefore, I cannot provide the specific APJ names with high confidence at this time.]
• Petition grounds: [Information regarding specific claims challenged, prior art, and statutory bases (§ 102 / § 103 / § 112) for the petition in IPR2026-00061 was not found in the initial search results. This information is typically detailed in the institution decision or the petition itself, which are not yet fully public or easily searchable in summary form for a recently instituted case.]
• Institution decision: Instituted. The IPR was instituted on 2026-05-22. The specific reasoning for institution is contained within the Board's decision, which would typically be available on the USPTO PTAB E2E system.
• Final Written Decision (if issued): Not yet issued. The status is "Trial Instituted," meaning the case is ongoing and has not reached a final judgment.
• Settlement / termination: No settlement or termination reported as of 2026-05-27.
• Appeal: Not applicable. No Final Written Decision has been issued yet.
• Defensive value: This active IPR means that the validity of certain claims of US8076194 is currently being re-examined by the PTAB. The outcome of this proceeding will determine whether these claims are maintained or cancelled. If the petitioner is successful, the challenged claims will be invalidated, providing a strong defense against assertion of those claims. If the patent owner prevails, the patent will be strengthened against future invalidity challenges based on the same prior art.

Strategic summary

Given that IPR2026-00061 is currently in the "Trial Instituted" phase, no claims of US8076194 have yet been canceled or sustained by the PTAB. Therefore, all claims of the patent (claims 1-22) remain untested in terms of a final PTAB decision. The patent has not yet been narrowed through IPR.

The estoppel landscape under § 315(e)(2) will only become relevant after a Final Written Decision is issued. If IPR2026-00061 results in a final decision, the petitioner (Taiwan Semiconductor Manufacturing Company Ltd.) and its privies would be estopped from asserting invalidity grounds that were raised or reasonably could have been raised in this IPR against any claim found patentable. Until then, prior art grounds remain broadly available for other parties. There is no clear pattern of multiple IPRs by the same petitioner or aggressive PTAB appeals by the patent owner yet for this specific patent. Unified Patents is noted as a petitioner in the Google Patents legal status section for IPR2026-00061, which is a defensive aggregator.

Recommended next steps

For a defendant facing assertion of US patent 8076194:

• Monitor IPR2026-00061 closely. The trial has been instituted, and a Final Written Decision is expected within one year of institution (i.e., by May 22, 2027). Key upcoming milestones include potential discovery, depositions, an oral hearing, and ultimately the Final Written Decision. The institution decision, when made publicly available in full, should be reviewed to understand the specific claims challenged and the prior art relied upon.
• Access PTAB E2E System: Regularly check the USPTO PTAB E2E system for updates on IPR2026-00061 to obtain the full institution decision, subsequent filings, and the eventual Final Written Decision. (URL: https://developer.uspto.gov/ptab-actions/search/documents/ipr2026-00061 - Note: Direct links to specific documents within E2E may not be stable over time, but the case number provides direct access.)
• Assess potential impact: Understand which claims are being challenged in IPR2026-00061 and how those claims relate to any asserted infringement theories. The outcome will be critical in shaping defensive strategies.

Inventors

The named inventors for US Patent 8076194 are:

• Chu-Yin Tseng
• Shih-Chieh Hsu
• Chih-Chiang Wu
• Shyh-Fann Ting
• Po-Lun Cheng
• Hsuan-Hsu Chen

All inventors were employed by United Microelectronics Corp (UMC) at the time of filing, as UMC is listed as the original assignee. There is no information to suggest any unusual patterns of inventor departures within 12 months of filing.

Original assignee

The original assignee on the issued patent was United Microelectronics Corp (UMC). UMC is a major Taiwanese semiconductor foundry that manufactures integrated circuits for other companies, thus shipping products embodying the claims. UMC is currently an active, operating company.

Assignment timeline

• 2007-06-28 (executed) / recorded 2010-05-18 — Reel 024398/0400

  • Conveyance: Assignment
  • Assignor: CHEN, HSUAN-HSU; CHENG, PO-LUN; HSU, SHIH-CHIEH; TING, SHYH-FANN; TSENG, CHU-YIN; WU, CHIH-CHIANG (the inventors)
  • Assignee: UNITED MICROELECTRONICS CORP.
  • Correspondent: NO CORRESPONDENT DATA
  • Context: Initial assignment of patent rights from inventors to their employer.

• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292

  • Conveyance: Assignment
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED
  • Correspondent: WONG, WEN-HSIANG, WEN HSIANG WONG, 19 F-1, NO. 77, SEC. 2, DUNHUA S. RD., DAAN DIST., TAIPEI CITY, TAIWAN, (R.O.C.)
  • Context: Transfer of patent rights from an operating company to a patent monetization entity.

Timeline diagram

timeline
    title Ownership of US 8076194
    2010 : Filed by United Microelectronics Corp
    2011 : Issued
    2021 : Assigned to Marlin Semiconductor Ltd
    2025 : First litigation filed by Marlin

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from United Microelectronics Corporation to Marlin Semiconductor Limited (Reel 056991/0292). Marlin Semiconductor Limited is a subsidiary of IPValue Management, a known patent monetization firm, and is engaged in licensing-only activities, confirming its nature as a shell entity for assertion.
2. Known asserter in the chain — Present. Marlin Semiconductor Limited, the current assignee per Reel 056991/0292, is a known patent assertion entity (NPE), identified as a subsidiary of IPValue Management. It is actively asserting this patent family in various legal proceedings, including ITC Investigation 337-TA-1443 and companion District Court cases.
3. Repeat correspondent across the chain — Unclear. The only assignment with correspondent data (Reel 056991/0292) lists WONG, WEN-HSIANG of WEN HSIANG WONG. Without access to a broader database of assignments handled by this correspondent or their involvement in other NPE activities, it is not possible to confirm a pattern of recurrence across this chain or within a known NPE portfolio based solely on the provided data.
4. Cascading transfers — Not present. There have only been two assignments in the chain, one from the inventors to the original assignee and one from the original assignee to the current assignee. This does not represent multiple consecutive transfers through chained LLCs in a short period.
5. Pre-litigation transfer — Not present. The assignment to Marlin Semiconductor Limited was executed on 2021-06-18 and recorded on 2021-07-26 (Reel 056991/0292). The earliest known litigation activity related to this patent by Marlin Semiconductor Limited commenced in early 2025 (e.g., ITC complaint filed February 18, 2025), which is well over six months after the transfer.
6. Bankruptcy fire-sale — Not present. United Microelectronics Corporation (UMC) is an active, operating company, and the transfer to Marlin Semiconductor Limited was not part of bankruptcy proceedings.
7. Privateering — Present. The patent was transferred from United Microelectronics Corporation (an operating company) to Marlin Semiconductor Limited (a known NPE). Marlin Semiconductor is now asserting this patent, which was part of a portfolio acquired from UMC. This arrangement allows an operating company to monetize its patents through an NPE, potentially against competitors, without directly engaging in litigation itself.
8. Defensive aggregator (anti-NPE) — Not present. The current assignee, Marlin Semiconductor Limited, is a patent assertion entity, not a defensive aggregator.

Verdict

NPE — high confidence

The patent was transferred from the operating company United Microelectronics Corporation to Marlin Semiconductor Limited on 2021-06-18 (Reel 056991/0292). Marlin Semiconductor Limited is a known patent assertion entity and a subsidiary of IPValue Management, which constitutes a shell-entity transfer and involves a known asserter. This pattern, coupled with Marlin Semiconductor's active litigation of patents acquired from UMC, strongly indicates an NPE assertion strategy consistent with privateering.

USPTO Patent Assignment Search for US8076194

The most relevant prior art for US patent 8076194 are identified from the "Citations" section of the patent document itself. Each cited patent is analyzed below for its potential anticipation under 35 U.S.C. § 102.

Analysis of Cited Prior Art for US8076194

1. US6110787A

• Full Citation: US6110787A, "Method for fabricating a MOS device," Chartered Semiconductor Manufacturing Ltd., published August 29, 2000.
• Publication/Filing Date: Publication Date: 2000-08-29; Priority Date: 1999-09-07.
• Brief Description: This patent describes a method for fabricating a MOS device that involves forming a gate, creating recessed source/drain regions, and then forming spacers. The method aims to prevent unwanted dopant diffusion during subsequent high-temperature processes. It includes forming a protective layer over the gate and substrate before forming the recesses. However, it does not explicitly disclose forming an epitaxial layer whose top surface is above the original substrate surface, nor a spacer whose contact surface with the epitaxial layer is above the original substrate surface.
• Potential Anticipated Claim(s): US6110787A describes general steps like forming a gate, forming a protective layer, forming recesses, and forming spacers. However, it likely does not anticipate the key features of US8076194's independent claims 1 and 10, particularly the "raised" epitaxial layer and the elevated contact surface between the epitaxial layer and the spacer, as this is a distinguishing feature of 8076194 aimed at enhancing strain.

2. US6429084B1

• Full Citation: US6429084B1, "MOS transistors with raised sources and drains," International Business Machines Corporation, published August 6, 2002.
• Publication/Filing Date: Publication Date: 2002-08-06; Priority Date: 2001-06-20.
• Brief Description: This patent describes MOS transistors with raised source and drain structures formed by epitaxial growth. The raised portions are typically formed after gate patterning and may involve spacers. The invention focuses on reducing parasitic resistance and improving device performance by creating elevated source/drain areas. It mentions forming a protective layer (e.g., nitride liner) over the gate and substrate before forming the raised source/drain regions.
• Potential Anticipated Claim(s): This patent discloses forming raised epitaxial layers for source/drain regions, which aligns with the "epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate" feature of claim 1. It also involves forming spacers on the sidewalls of the gate. Therefore, it potentially anticipates aspects of claims 1 and 10 related to raised epitaxial layers and spacers. Further analysis would be needed to see if the specific configuration of the contact surface between the epitaxial layer and spacer being above the substrate is explicitly taught or inherently present.

3. US20040142545A1

• Full Citation: US20040142545A1, "Semiconductor with tensile strained substrate and method of making the same," Advanced Micro Devices, Inc., published July 22, 2004.
• Publication/Filing Date: Publication Date: 2004-07-22; Priority Date: 2003-01-17.
• Brief Description: This publication describes methods for forming semiconductor devices with tensile strained channels to improve carrier mobility. It involves creating a recess in a semiconductor substrate and epitaxially growing a material like SiGe, which induces tensile strain in an overlying silicon channel. The focus is on strain engineering for performance enhancement. It describes forming a gate and then an epitaxial layer, but the details on the relative height of the epitaxial layer to the substrate surface and the spacer's contact point might differ from US8076194.
• Potential Anticipated Claim(s): This reference teaches the concept of using epitaxially grown layers to induce strain and enhance carrier mobility, which is the underlying goal of US8076194. It involves forming recesses and epitaxial growth. However, it might not explicitly disclose the specific structural configurations claimed in US8076194, such as the epitaxial layer being raised above the substrate surface and the spacer's contact surface with it also being above the substrate surface.

4. US6774000B2

• Full Citation: US6774000B2, "Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures," International Business Machines Corporation, published August 10, 2004.
• Publication/Filing Date: Publication Date: 2004-08-10; Priority Date: 2002-11-20.
• Brief Description: This patent describes a method for manufacturing MOSFET devices with in-situ doped, raised source and drain structures. It involves forming a gate, then forming recesses, and subsequently growing doped epitaxial layers that are raised above the original substrate surface. The in-situ doping allows for the formation of source/drain regions concurrently with epitaxial growth, potentially eliminating separate implantation steps. Spacers are also used.
• Potential Anticipated Claim(s): This patent directly teaches forming raised epitaxial layers for source/drain regions which are in-situ doped, and the use of spacers. This significantly overlaps with elements of claims 1 and 10 of US8076194, especially the "top surface of the epitaxial layer is above the surface of the semiconductor substrate." The explicit mention of in-situ doping also relates to the optional step described in US8076194 (e.g., in-situ doped ion epitaxial growth process for forming source/drain regions). It would be highly relevant for anticipating the 'raised epitaxial layer' and 'spacer' elements in combination.

5. US6815770B1

• Full Citation: US6815770B1, "MOS transistor having reduced source/drain extension sheet resistance," United Microelectronics Corp., published November 9, 2004.
• Publication/Filing Date: Publication Date: 2004-11-09; Priority Date: 2003-08-14.
• Brief Description: This patent focuses on reducing the source/drain extension sheet resistance in MOS transistors. It describes forming a gate, then forming an offset spacer, followed by lightly doped regions, and then forming a main spacer. Source/drain regions are subsequently formed. The primary objective is to optimize doping profiles and resistances. It involves spacers and source/drain formation but does not explicitly focus on raised epitaxial layers or strained channels as a primary means of improvement, nor the specific geometric relationship of the epitaxial layer and spacer to the substrate surface.
• Potential Anticipated Claim(s): While this patent describes forming gates, spacers, and lightly doped/source/drain regions (elements common to claims 1 and 10 of US8076194), it does not appear to teach the critical feature of forming an epitaxial layer in a recess where its top surface is above the semiconductor substrate, nor the subsequent spacer contact. Thus, it likely does not anticipate the core distinguishing features of US8076194.

6. US20040232513A1

• Full Citation: US20040232513A1, "Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials," Taiwan Semiconductor Manufacturing Co., published November 25, 2004.
• Publication/Filing Date: Publication Date: 2004-11-25; Priority Date: 2003-05-23.
• Brief Description: This publication describes a method of silicon strain engineering using specific shallow trench isolation (STI) fill materials to induce strain in the device channel, thereby improving carrier mobility. It focuses on the materials used in isolation structures to create stress. While it relates to strain engineering in transistors, it does not deal with forming recesses adjacent to a gate and growing raised epitaxial layers for source/drain regions or the specific interaction with spacers as claimed in US8076194.
• Potential Anticipated Claim(s): This reference's focus on STI fill materials for strain engineering means it does not anticipate the specific method steps of forming a recess, a raised epitaxial layer, and a spacer contacting the raised layer as described in claims 1 and 10 of US8076194.

7. TW200509310A

• Full Citation: TW200509310A, "Field effect transistor having increased carrier mobility," Advanced Micro Devices Inc., published March 1, 2005.
• Publication/Filing Date: Publication Date: 2005-03-01; Priority Date: 2003-08-18.
• Brief Description: This Taiwanese patent application relates to field-effect transistors with increased carrier mobility through strain engineering. It describes forming recesses in the source/drain regions and epitaxially growing materials like SiGe or Si:C to induce strain in the channel. The technique is aimed at improving device performance. Similar to other strain engineering patents, it focuses on the materials and the induced strain but needs closer examination for the specific raised epitaxial layer and spacer configuration of US8076194.
• Potential Anticipated Claim(s): This reference generally covers strain engineering through epitaxial growth in source/drain regions. It may anticipate the broad concept of forming an epitaxial layer in recesses to induce strain. However, without further details on whether the epitaxial layer is raised above the substrate surface and the specific contact surface of the spacer, it is unlikely to anticipate the unique geometric features of US8076194's independent claims 1 and 10.

8. US20050156154A1

• Full Citation: US20050156154A1, "Protecting Silicon Germanium Sidewall with Silicon for Strained Silicon/Silicon Germanium MOSFETs," International Business Machines Corporation, published July 21, 2005.
• Publication/Filing Date: Publication Date: 2005-07-21; Priority Date: 2004-01-16.
• Brief Description: This publication discloses a method for protecting SiGe sidewalls with silicon in strained silicon/SiGe MOSFETs. This is primarily a processing technique to prevent damage or oxidation of SiGe regions during subsequent manufacturing steps, especially during spacer formation. It involves selective epitaxial growth of silicon on the SiGe. While it deals with SiGe and spacers in strained devices, its focus is on protection, not necessarily on forming a raised epitaxial layer and a contact surface above the substrate in the manner of US8076194.
• Potential Anticipated Claim(s): This reference focuses on protecting SiGe sidewalls with silicon. While it is in the context of strained MOSFETs and involves spacers, it does not appear to disclose the specific feature of the epitaxial layer being raised above the substrate surface such that the spacer's contact surface with it is also above the substrate. Therefore, it likely does not anticipate claims 1 or 10.

9. US20060024879A1

• Full Citation: US20060024879A1, "Selectively strained MOSFETs to improve drive current," Taiwan Semiconductor Manufacturing Co., Ltd., published February 2, 2006.
• Publication/Filing Date: Publication Date: 2006-02-02; Priority Date: 2004-07-31.
• Brief Description: This publication describes selectively strained MOSFETs where recesses are etched in the source/drain regions and filled with epitaxially grown SiGe or Si:C to induce compressive or tensile strain in the channel. This aims to improve drive current. It generally teaches forming recessed source/drain regions and filling them with stress-inducing epitaxial material.
• Potential Anticipated Claim(s): This reference generally covers the concept of creating strained channels by forming recesses and epitaxially growing stress-inducing materials. It likely anticipates the broad concept of forming recesses and epitaxial layers for strain. However, without explicit disclosure of the epitaxial layer being raised above the original substrate surface and the specific contact surface of the spacer also being above the substrate, it may not anticipate the specific geometric elements of claims 1 and 10 of US8076194.

10. US20060134873A1

• Full Citation: US20060134873A1, "Tailoring channel strain profile by recessed material composition control," Texas Instruments Incorporated, published June 22, 2006.
• Publication/Filing Date: Publication Date: 2006-06-22; Priority Date: 2004-12-22.
• Brief Description: This publication describes tailoring the channel strain profile in MOSFETs by controlling the composition of material in recessed source/drain regions. It involves forming recesses and epitaxially growing material, potentially with varying compositions, to optimize strain. It focuses on the ability to control strain via material composition.
• Potential Anticipated Claim(s): Similar to US20060024879A1, this reference teaches the use of epitaxially grown material in recesses for strain engineering. The anticipation of US8076194's claims would depend on whether it explicitly discloses the raised epitaxial layer feature and the specific spacer contact configuration claimed. It generally falls into the category of strain engineering using embedded stressors.

11. US20060211245A1

• Full Citation: US20060211245A1, "Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect," Advanced Micro Devices, Inc., published September 21, 2006.
• Publication/Filing Date: Publication Date: 2006-09-21; Priority Date: 2003-12-03.
• Brief Description: This publication discusses forming abrupt junctions in semiconductor devices using the dopant snowplow effect during silicide growth. The primary focus is on dopant activation and junction formation, not on creating strained channels via raised epitaxial layers or the specific geometry of spacers in relation to them.
• Potential Anticipated Claim(s): This reference primarily concerns dopant activation and junction formation during silicidation. It does not teach the core method steps of forming raised epitaxial layers or the specific spacer configuration of US8076194, and thus does not anticipate claims 1 or 10.

12. US20060226483A1

• Full Citation: US20060226483A1, "Method of fabricating strained channel devices," Agency For Science, Technology And Research, published October 12, 2006.
• Publication/Filing Date: Publication Date: 2006-10-12; Priority Date: 2005-04-06.
• Brief Description: This publication describes methods for fabricating strained channel devices, including forming recesses in the source/drain regions and then epitaxially growing stress-inducing materials like SiGe. The goal is to enhance carrier mobility. It addresses the general problem of achieving desired strain in the channel region.
• Potential Anticipated Claim(s): This reference, like others, teaches the general principle of using epitaxially grown stressors in recesses for strained channel devices. The question of anticipation for US8076194's claims 1 and 10 hinges on whether it explicitly discloses the raised nature of the epitaxial layer relative to the substrate surface and the resultant elevated contact surface of the spacer with this raised layer.

13. TW200636996A

• Full Citation: TW200636996A, "Structure and method for manufacturing strained FINFET," Ibm, published October 16, 2006.
• Publication/Filing Date: Publication Date: 2006-10-16; Priority Date: 2005-02-15.
• Brief Description: This Taiwanese patent describes a structure and method for manufacturing strained FinFETs. FinFETs have a different device architecture than planar MOSFETs, utilizing a fin-shaped channel. While it involves strain engineering and potentially epitaxial growth, the FinFET structure fundamentally differs from the planar MOS transistor fabrication described in US8076194.
• Potential Anticipated Claim(s): This reference is directed to FinFET technology, which is structurally distinct from the planar MOS transistors primarily addressed by US8076194. While both relate to strained devices, the specific fabrication steps for a FinFET, especially the geometry of source/drain regions and spacers relative to the fin, would likely not directly anticipate the claims of US8076194, which are focused on planar MOS structures with raised epitaxial layers.

14. US7195985B2

• Full Citation: US7195985B2, "CMOS transistor junction regions formed by a CVD etching and deposition sequence," Intel Corporation, published March 27, 2007.
• Publication/Filing Date: Publication Date: 2007-03-27; Priority Date: 2005-01-04.
• Brief Description: This patent describes forming CMOS transistor junction regions using a CVD etching and deposition sequence. This method aims to create precise junction profiles. It involves forming recesses and then depositing materials, which could include epitaxial growth. The patent primarily focuses on the CVD process for junction formation.
• Potential Anticipated Claim(s): This patent's focus is on CVD etching and deposition for junction formation. While it involves forming recesses and deposition, it is not explicitly focused on the raised aspect of the epitaxial layer and the elevated spacer contact as defined in US8076194's claims 1 and 10. Thus, it is unlikely to anticipate these specific features.

15. US20070298558A1

• Full Citation: US20070298558A1, "Method of fabricating semiconductor device and semiconductor device," Kabushiki Kaisha Toshiba, published December 27, 2007.
• Publication/Filing Date: Publication Date: 2007-12-27; Priority Date: 2006-06-22.
• Brief Description: This publication describes a method of fabricating a semiconductor device where a semiconductor layer, such as SiGe, is grown epitaxially in a recess and then covered with an insulating film. The goal is to apply strain to the channel. It describes a structure with a gate, recesses, and an epitaxially grown layer.
• Potential Anticipated Claim(s): This reference teaches forming an epitaxial layer in recesses for strain application. It may anticipate aspects related to forming recesses and epitaxial layers. However, the exact configuration of the epitaxial layer being raised above the substrate and the spacer's contact surface being above the substrate would need to be explicitly present to anticipate claims 1 and 10 of US8076194.

16. US20080006818A1

• Full Citation: US20080006818A1, "Structure and method to form multilayer embedded stressors," International Business Machines Corporation, published January 10, 2008.
• Publication/Filing Date: Publication Date: 2008-01-10; Priority Date: 2006-06-09.
• Brief Description: This publication describes structures and methods for forming multilayer embedded stressors in semiconductor devices. It involves forming recesses and growing multiple epitaxial layers with different lattice constants to create complex strain profiles. This is a more advanced approach to strain engineering.
• Potential Anticipated Claim(s): This reference describes sophisticated embedded stressors using multilayer epitaxial growth. While it deals with recesses and epitaxial layers for strain, the core innovation of US8076194 lies in the raised nature of the epitaxial layer and the specific spacer contact surface being above the substrate. This reference's focus is on the complexity of the stressor layers, not necessarily the specific geometric relationships claimed in US8076194.

17. US20080032468A1

• Full Citation: US20080032468A1, "Mos transistor and fabrication thereof," United Microelectronics Corp., published February 7, 2008.
• Publication/Filing Date: Publication Date: 2008-02-07; Priority Date: 2006-08-01.
• Brief Description: This publication describes a MOS transistor and its fabrication, including forming a gate and then source/drain regions. It may involve strain engineering techniques. This patent is from the same original assignee as US8076194, United Microelectronics Corp., suggesting related work. Further examination would be needed to see if it specifically discloses the raised epitaxial layer and elevated spacer contact.
• Potential Anticipated Claim(s): As a patent from the same original assignee, it's possible this reference contains similar or foundational concepts. It generally relates to MOS transistor fabrication. To anticipate claims 1 and 10 of US8076194, it would need to explicitly disclose the raised epitaxial layer and the spacer's contact surface with it being above the substrate surface. Without specific details, it's difficult to ascertain direct anticipation from the title/abstract alone.

18. US7381623B1

• Full Citation: US7381623B1, "Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance," International Business Machines Corporation, published June 3, 2008.
• Publication/Filing Date: Publication Date: 2008-06-03; Priority Date: 2007-01-17.
• Brief Description: This patent describes a pre-epitaxial disposable spacer integration scheme for enhanced device performance, utilizing very low-temperature selective epitaxy. This involves forming a disposable spacer, then epitaxial growth, and then removing the disposable spacer before forming the final spacer. The goal is to optimize the epitaxial growth process for strained devices. The timing of spacer formation relative to epitaxial growth is a key aspect.
• Potential Anticipated Claim(s): This patent describes a method where an epitaxial layer is formed before the final spacer, which is a key distinguishing feature of US8076194. It also focuses on enhanced device performance. This reference would be highly relevant for anticipating the sequence of forming the epitaxial layer before the spacer, and potentially aspects of the raised epitaxial layer and its interaction with a spacer, making it a strong candidate for anticipating claims 1 and 10 of US8076194.

19. US20080179636A1

• Full Citation: US20080179636A1, "N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers," International Business Machines Corporation, published July 31, 2008.
• Publication/Filing Date: Publication Date: 2008-07-31; Priority Date: 2007-01-27.
• Brief Description: This publication describes n-type field-effect transistors with tensilely strained semiconductor channels, fabricated using buried pseudomorphic layers. It focuses on achieving tensile strain for n-channel devices. The method involves forming trenches and growing specific materials to induce the desired strain.
• Potential Anticipated Claim(s): This reference relates to achieving tensile strain in nFETs using buried layers, a specific type of strain engineering. While it involves forming trenches and epitaxial growth, it is focused on buried layers for strain, which differs from the raised epitaxial layer configuration of US8076194's claims 1 and 10. Therefore, it is less likely to anticipate the specific structural features of US8076194.

20. US20080203449A1

• Full Citation: US20080203449A1, "Source/drain stressor and method therefor," Da Zhang, published August 28, 2008.
• Publication/Filing Date: Publication Date: 2008-08-28; Priority Date: 2007-02-28.
• Brief Description: This publication describes a source/drain stressor and a method for forming it. It involves forming a recess in the source/drain regions and growing a stressor material (e.g., SiGe) epitaxially. The goal is to induce strain in the channel. It generally teaches forming embedded stressors.
• Potential Anticipated Claim(s): This reference broadly covers forming embedded source/drain stressors using epitaxial growth in recesses. The anticipation of US8076194's claims 1 and 10 would hinge on whether it explicitly discloses the raised nature of the epitaxial layer and the specific contact surface of the spacer with the epitaxial layer being above the substrate surface.

21. US7745847B2

• Full Citation: US7745847B2, "Metal oxide semiconductor transistor," United Microelectronics Corp., published June 29, 2010.
• Publication/Filing Date: Publication Date: 2010-06-29; Priority Date: 2007-08-09.
• Brief Description: This patent is the parent application from which US8076194 is a divisional application. It describes a metal oxide semiconductor transistor structure comprising a gate, two raised epitaxial layers next to the gate, and a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layer. It also includes two doped regions. As a parent patent, it discloses the structure that the method claims of US8076194 aim to produce.
• Potential Anticipated Claim(s): As the parent application, US7745847B2 discloses the device structure that US8076194 claims a method of fabricating. Therefore, it will inherently disclose the structure resulting from the method claims, and potentially the steps if they are described. The claims of US8076194 (methods for fabricating the structure) would be anticipated by the disclosure of the parent patent if the method steps were also taught or rendered obvious by the parent. Given the explicit structural elements in its claims (e.g., "two raised epitaxial layers," "a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layer"), it directly describes the core structural outcomes of claims 1 and 10 of US8076194.

22. US7800182B2

• Full Citation: US7800182B2, "Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same," Infineon Technologies Ag, published September 21, 2010.
• Publication/Filing Date: Publication Date: 2010-09-21; Priority Date: 2006-11-20.
• Brief Description: This patent describes semiconductor devices, specifically pFETs, that include SiGe gate electrodes and embedded SiGe source/drain regions. The embedded SiGe is used to induce compressive strain in the channel to enhance hole mobility. The methods involve forming recesses for the SiGe source/drain regions.
• Potential Anticipated Claim(s): This patent teaches the use of embedded SiGe in source/drain regions for strain in pFETs, a concept relevant to US8076194. It also involves forming recesses. The extent of anticipation for claims 1 and 10 of US8076194 would depend on whether this patent explicitly discloses the epitaxial layer being raised above the substrate surface and the spacer's contact surface with it being above the substrate surface. It is a strong candidate for generally teaching embedded SiGe stressors.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 8076194

This analysis evaluates whether the claimed invention of US Patent 8076194 would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention, in light of the prior art. The core inquiry under 35 U.S.C. § 103 asks whether the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious to a PHOSITA. This includes considering the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the art, and any secondary considerations of non-obviousness.

The key innovative aspects highlighted by US8076194 relate to a specific sequence of fabricating a MOS (and CMOS) transistor, particularly forming a raised epitaxial layer for source/drain regions before forming the permanent gate sidewall spacers, and utilizing a protective layer during recess etching. This approach aims to provide better control over strain in the channel, reduce micro-loading effects during etching, and prevent dopant diffusion.

Identification of Key Prior Art References

Based on the patent text and cited references, the following prior art is particularly relevant for an obviousness analysis:

• US7381623B1 (IBM): "Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance". This reference describes a method for forming raised source/drain (RSD) structures, which involves forming a gate, then a sacrificial spacer, then epitaxially growing source/drain regions, removing the sacrificial spacer, and finally forming a permanent spacer that covers portions of the epitaxially grown regions.
• US6429084B1 (IBM): "MOS transistors with raised sources and drains". This patent broadly teaches the concept of forming MOS transistors with raised source and drain regions through epitaxial growth.
• US20040142545A1 (Advanced Micro Devices, Inc.): "Semiconductor with tensile strained substrate and method of making the same". This reference, and others like US20060024879A1, illustrate the known technique of using strained materials to enhance carrier mobility in MOS transistors.
• General knowledge in the art: The routine use of protective layers (e.g., silicon nitride) during etching steps to prevent damage to underlying structures like gates and shallow trench isolations (STIs) is common practice in semiconductor manufacturing. Similarly, the extension of fabrication processes from single MOS transistors to complementary MOS (CMOS) structures by employing sequential masking and selective material deposition for N-type and P-type devices is also well-established.

Obviousness Analysis of Independent Claim 1

Independent Claim 1 describes a method of fabricating a MOS transistor, including:

1. Providing a semiconductor substrate.
2. Forming at least a gate on the semiconductor substrate.
3. Forming a protective layer on the semiconductor substrate, covering the surface of the gate.
4. Forming at least a recess within the semiconductor substrate adjacent to the gate.
5. Forming an epitaxial layer in the recess, where its top surface is above the semiconductor substrate surface.
6. Forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, where a contact surface of the epitaxial layer and the spacer is above the semiconductor substrate surface.

Combination: US7381623B1 in view of US6429084B1 and general knowledge in the art.

Mapping of Claim Elements to Prior Art:

• "providing a semiconductor substrate": Taught by US7381623B1 (e.g., substrate 110 in Fig. 1).
• "forming at least a gate on the semiconductor substrate": Taught by US7381623B1 (e.g., gate structure 120 in Fig. 2).
• "forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate": US7381623B1 discloses a nitride layer (122 in Fig. 2) formed over the gate electrode, which functions as a hardmask and protective layer during subsequent etching steps, including the etching of recesses (Fig. 3). This nitride layer protects the gate structure. While this protective layer in '623 is described as remaining, general knowledge in semiconductor processing teaches that temporary protective layers are routinely applied and removed as needed to protect structures during specific fabrication steps. A PHOSITA would recognize the benefits of using such a protective layer during recess etching to prevent damage to the gate and STI (as highlighted in US8076194) and would find it obvious to remove it if its function for subsequent steps is complete.
• "forming at least a recess within the semiconductor substrate adjacent to the gate": Taught by US7381623B1 (e.g., recesses 130 in Fig. 3).
• "forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate": Taught by US7381623B1 (e.g., epitaxial S/D 132 in Fig. 4). US7381623B1 is directed to forming "raised source/drain (RSD) structures," and US6429084B1 also explicitly teaches "MOS transistors with raised sources and drains". A PHOSITA would understand that such "raised" structures inherently mean the top surface of the epitaxial layer is above the original semiconductor substrate surface.
• "forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate": US7381623B1 explicitly teaches forming a permanent spacer (142 in Fig. 5) on the sidewalls of the gate structure, which "covers portions of the S/D regions" (i.e., the already-formed epitaxial layers 132). Since the epitaxial layers are "raised," the contact surface between the permanent spacer and these raised epitaxial layers would necessarily be above the surface of the semiconductor substrate. This directly maps to the claim language.

Motivation to Combine/Modify:
A PHOSITA, seeking to develop high-performance MOS transistors with strained channels (a known technique for enhancing carrier mobility, as described in US20040142545A1) and raised source/drain structures, would be motivated to consider the methods disclosed in US7381623B1. US7381623B1 presents a fabrication sequence that places the formation of the epitaxial source/drain regions before the formation of the final, permanent gate sidewall spacers. This "pre-epitaxial" approach for the permanent spacer addresses the very problems cited by US8076194 as shortcomings of the prior art, such as limitations on the distance between the gate and epitaxial layer being determined by the spacer width. The use of a sacrificial spacer in '623 followed by its removal and then permanent spacer formation demonstrates a clear motivation to separate the definition of the epitaxial region from the final spacer width, thereby offering greater control and flexibility in device design.

Furthermore, the explicit use of a removable protective layer in US8076194 during recess etching, which is then removed before spacer formation, would be an obvious engineering choice for a PHOSITA. Such layers are conventionally used to protect critical features like gates and STI during aggressive etching steps, and their removal once their protective function is fulfilled is a routine process optimization. The benefits cited by '194 (reduced micro-loading, improved etch uniformity, reduced STI loss) are inherent advantages recognized by a PHOSITA when considering different processing sequences and protective measures.

Obviousness Analysis of Independent Claim 10

Independent Claim 10 extends the method of Claim 1 to a CMOS transistor fabrication, specifying distinct first and second conductive transistor areas, an isolation structure, and the sequential formation of a first protective layer, first recess, and first epitaxial layer for the first conductive area, followed by spacer formation. The second embodiment of US8076194 (FIG. 7-14) explicitly details this CMOS process.

Combination: US7381623B1 + US6429084B1 + general knowledge of CMOS fabrication and selective processing.

Mapping of Claim Elements to Prior Art:

• The foundational steps of forming gates, recesses, raised epitaxial layers, and then permanent spacers on the gate sidewalls and epitaxy are rendered obvious by US7381623B1 and US6429084B1, as discussed for Claim 1.
• "providing a semiconductor substrate having at least a first conductive transistor area for fabricating first conductive transistors and at least a second conductive transistor area for fabricating second conductive transistors, and an isolation structure between the first conductive transistor area and the second conductive transistor area": The concept of CMOS integration, including distinct transistor areas (e.g., PMOS and NMOS) and isolation structures like shallow trench isolations (STI), is a fundamental and long-established aspect of semiconductor device manufacturing. Numerous prior art references teach this, such as US7195985B2, which discusses "CMOS transistor junction regions".
• "forming a gate on the first conductive transistor area and on the second conductive transistor area respectively": Routine in CMOS fabrication.
• "forming a first protective layer on the semiconductor substrate, and the first protective layer covering the surface of each gate": As discussed for Claim 1, the use of a protective layer during recess etching is known, and its application across both transistor areas in a CMOS process would be an obvious extension.
• "forming at least a first recess within the semiconductor substrate adjacent to the gate in the first conductive transistor area; forming a first epitaxial layer in the first recess, wherein the top surface of the first epitaxial layer is above the surface of the semiconductor substrate": This is a direct application of the epitaxy-before-permanent-spacer raised source/drain technique (from US7381623B1 and US6429084B1) to a specific transistor type (e.g., PMOS with SiGe, as mentioned in '194) within a CMOS process. The sequential, masked processing to form features in one transistor area while protecting others is standard in CMOS.
• "forming a spacer on the sidewall of each gate and at least on a portion of the first epitaxial layer, wherein a contact surface of the first epitaxial layer and the spacer is above the surface of the semiconductor substrate": This is the application of the permanent spacer formation (from US7381623B1) to the CMOS context, covering the gate sidewalls and portions of the already-formed raised epitaxial layers in the respective transistor areas.

Motivation to Combine/Modify:
A PHOSITA would be motivated to apply the benefits of the raised epitaxial source/drain technology, particularly the improved control afforded by forming epitaxy before permanent spacers (as taught by US7381623B1), to CMOS devices. The challenges of optimizing carrier mobility in both PMOS (e.g., using SiGe) and NMOS (e.g., using SiC or tensile Si) devices are well-known in CMOS scaling (e.g., US20040142545A1). It would be obvious to a PHOSITA to adapt the method from US7381623B1 (or similar single-device methods) to a CMOS context by employing conventional masking and selective processing techniques to fabricate different types of epitaxial layers (e.g., SiGe for PMOS and SiC for NMOS) in their respective transistor areas. The sequential use of protective layers and etching/growth steps for different device types is a routine engineering adaptation for CMOS manufacturing.

Conclusion on Obviousness

The methods claimed in US Patent 8076194, as defined by independent claims 1 and 10, would likely be considered obvious to a PHOSITA in light of the combination of US7381623B1, US6429084B1, and general knowledge regarding semiconductor fabrication techniques, including CMOS processing and the use of protective layers. US7381623B1 specifically teaches a process flow that achieves the structural outcome of the '194 patent, where raised epitaxial source/drain regions are formed before the final gate sidewall spacers, and these spacers are then formed partially on the raised epitaxial layers. The motivations for such a sequence (e.g., greater control over epitaxy placement, strain engineering) were understood in the art, and the specific protective layer and its removal in '194 represent routine process optimizations.