US 7745847

Summary of US Patent 7745847

Title: Metal oxide semiconductor transistor

Assignee: Marlin Semiconductor Ltd (as of 2021-07-26; originally United Microelectronics Corp)

Inventors: Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, Hsuan-Hsu Chen

Filing Date: 2007-08-09

Issue Date: 2010-06-29

Abstract: The patent describes a method for fabricating a metal oxide semiconductor transistor. This method involves providing a semiconductor substrate, forming at least one gate on the substrate, and then forming a protective layer over the substrate and the gate. Subsequently, at least one recess is formed in the semiconductor substrate adjacent to the gate, into which an epitaxial layer is then formed. A lightly doped region is formed in the semiconductor substrate adjacent to the gate, and finally, a spacer is formed on the sidewall of the gate.

Plain-language overview of independent claims:

Independent Claim 1: This claim describes a physical structure of a MOS transistor. It includes:

• A gate built on a semiconductor substrate.
• Two raised epitaxial layers located within the semiconductor substrate, positioned on either side of the gate, and extending above the surface of the semiconductor substrate.
• A spacer situated on the sidewall of the gate. This spacer extends partially over the raised epitaxial layers, and the point where the epitaxial layers touch the bottom of the spacer is also above the semiconductor substrate's surface.
• Two doped regions, each formed in the semiconductor substrate next to the corresponding sides of the gate.

The primary distinguishing feature of this claim appears to be the presence of "raised" epitaxial layers that are positioned next to the gate and extend above the substrate surface, with the spacer extending over a portion of these raised layers. The "contact surface" between the raised epitaxial layers and the bottom of the spacer is also above the substrate surface.

Independent Claim 1 (Method): (Note: The patent abstract and description refer to methods of fabricating a MOS transistor, but the claims section only explicitly lists claim 1 as a "MOS transistor structure" followed by dependent claims. The initial summary of the invention also lists two method claims. However, given the prompt to interpret the claims literally, and the provided full text of the claims, only a single independent claim related to a structure is presented. If there were independent method claims, they would typically be numbered separately or clearly indicated as method claims within the claims section. It is possible the "method" claims mentioned in the summary are high-level descriptions that are further detailed in the dependent claims or throughout the specification but not explicitly presented as independent claims in the final granted patent claims section, or the provided text is an excerpt.)

Based on the provided patent text, there is only one independent claim listed in the "Claims" section, which is a structural claim. The descriptions of "another method for fabricating a CMOS transistor" and "a method of fabricating a MOS transistor" in the "Summary of the Invention" section appear to describe conceptual inventions or embodiments, but they are not presented as separate independent claims in the actual "Claims" list provided. Therefore, I will only provide an overview of the explicit independent claim 1.

CAFC 2026 Dockets: A search of CAFC 2026 dockets for US patent 7745847 did not yield any specific results for this patent number. The search results provided general information about CAFC dockets and some recent patent cases, but none directly mention US7745847.

Known litigation involving US patent 7745847 includes cases filed in District Courts and the International Trade Commission.

Here's a list of known litigation cases involving US patent 7745847:

• Texas Western District Court

  • Case number: 1:25-cv-00215
  • Status: Critical
  • Plaintiff(s), Defendant(s), and Filing Date: Not publicly available from the provided information.

• International Trade Commission

  • Case number: 337-TA-3809
  • Status: Litigation
  • Plaintiff(s), Defendant(s), and Filing Date: Not publicly available from the provided information.

• Texas Eastern District Court

  • Case number: 2:25-cv-00171
  • Status: Litigation
  • Plaintiff(s), Defendant(s), and Filing Date: Not publicly available from the provided information.

• International Trade Commission

  • Case number: 337-TA-1443
  • Status: Litigation
  • Plaintiff(s), Defendant(s), and Filing Date: Not publicly available from the provided information.

CAFC (Court of Appeals for the Federal Circuit) and PACER:
As of April 26, 2026, there is no authoritative information found regarding specific CAFC dockets for US7745847 in 2026. For cases filed after March 1, 2012, case information and documents are available through PACER. For cases filed before March 1, 2012, records are stored with the National Archives and Records Administration, but the Clerk's Office maintains copies of some documents on-site. The Federal Circuit also publishes opinions and select orders online, with most orders issued after 2012 available via PACER.

Proceedings overview

There is one AIA trial proceeding on file for US patent 7745847, currently in an instituted (pending) status. This indicates that the patent has been challenged, and the PTAB has agreed to review at least some of the claims. For a defendant, this means the patent is not yet hardened, and an active challenge against it is underway.

IPR2025-00847 — Taiwan Semiconductor Manufacturing Company Limited, Apple, Inc., Broadcom, Inc., and Qualcomm, Inc. v. Marlin Semiconductor Limited

• Type: Inter Partes Review
• Filed: 2025-04-17
• Status: Pending - Instituted
• Judge panel: Not publicly available from the provided information.
• Petition grounds: Not publicly available from the provided information. The petition grounds would typically specify which claims are challenged, the prior art asserted, and the statutory basis (e.g., § 102 for anticipation, § 103 for obviousness).
• Institution decision: Instituted. The exact date of institution and the panel's reasoning are not publicly available from the provided information, but the proceeding has moved past the petition stage to trial.
• Final Written Decision (if issued): Not yet issued, as the proceeding is still pending.
• Settlement / termination: Not applicable yet.
• Appeal: Not applicable yet.
• Defensive value: This active IPR means that the validity of US7745847 is currently being challenged at the PTAB. While the specific claims under review and the strength of the petitioner's arguments are not detailed, the institution of the IPR suggests that the petitioners have demonstrated a reasonable likelihood of success on at least one challenged claim. A defendant facing assertion of this patent could potentially leverage the ongoing IPR, depending on its scope and eventual outcome, or even consider joining the IPR if circumstances allow.

Strategic summary

As of the current date, US patent 7745847 is undergoing an Inter Partes Review (IPR2025-00847). The status indicates that the PTAB has instituted a trial, meaning the validity of at least some claims of the patent is being examined. Until a Final Written Decision (FWD) is issued, it is not possible to definitively state which claims are CANCELED or SUSTAINED. All claims of the patent currently remain UNTESTED by a final PTAB decision.

The estoppel landscape under 35 U.S.C. § 315(e)(2) will only become relevant after a Final Written Decision is issued. If claims are challenged and a final decision is reached, the petitioners (Taiwan Semiconductor Manufacturing Company Limited, Apple, Inc., Broadcom, Inc., and Qualcomm, Inc.) and their privies would be estopped from asserting grounds they raised or reasonably could have raised in the IPR. Currently, all prior-art grounds remain available to a potential defendant not privy to the ongoing IPR.

The involvement of multiple large technology companies (Taiwan Semiconductor Manufacturing Company Limited, Apple, Inc., Broadcom, Inc., and Qualcomm, Inc.) as petitioners suggests a significant interest in challenging the patent. This could signal that the patent is being asserted against them or that they foresee potential assertions. The PTAB case was filed through Unified Patents' PTAB Data, indicating a possible defensive aggregator strategy to challenge the patent.

Recommended next steps

For a defendant currently being asserted against, it is crucial to monitor IPR2025-00847 closely.

• Track IPR Milestones: Identify key upcoming dates, such as the deadline for the Patent Owner's Response, the Petitioner's Reply, and the oral hearing. The PTAB has a statutory one-year deadline to issue a Final Written Decision from the date of institution.
• Obtain Institution Decision: Seek to obtain and analyze the PTAB's Institution Decision for IPR2025-00847. This document will detail the specific claims challenged, the prior art cited, and the PTAB's reasoning for instituting the review. This information is critical for assessing the strength of the challenge and its potential impact on any assertion against you.
• Evaluate Intervention/Joinder: Depending on the specific claims being asserted against you and the grounds of the instituted IPR, evaluate the possibility and strategic value of intervening in the IPR or filing a joinder motion, if applicable.
• Review Patent Owner's Arguments: Analyze the Patent Owner's response to the IPR petition to understand their defense strategies and arguments for patentability.

Inventors

• Chu-Yin Tseng (United Microelectronics Corp.)
• Shih-Chieh Hsu (United Microelectronics Corp.)
• Chih-Chiang Wu (United Microelectronics Corp.)
• Shyh-Fann Ting (United Microelectronics Corp.)
• Po-Lun Cheng (United Microelectronics Corp.)
• Hsuan-Hsu Chen (United Microelectronics Corp.)

All inventors were likely employees of United Microelectronics Corp. at the time of filing, as is common practice for patent assignment to the employer.

Original assignee

The original assignee on the issued patent is United Microelectronics Corp (UMC). UMC is a leading global semiconductor foundry company based in Taiwan. They provide IC fabrication services focusing on logic and various specialty technologies for major sectors of the electronics industry, including mobile and wireless communications, smart IoT, computing and data processing, and automotive. UMC is an operating company and is currently active and listed on the Taiwan Stock Exchange and the New York Stock Exchange.

Assignment timeline

• 2007-06-28 (executed) / recorded 2007-08-09 — Reel 019675/0422
  • Conveyance: Assignment
  • Assignor: CHEN, HSUAN-HSU; CHENG, PO-LUN; HSU, SHIH-CHIEH; TING, SHYH-FANN; TSENG, CHU-YIN; WU, CHIH-CHIANG (all inventors)
  • Assignee: UNITED MICROELECTRONICS CORP., TAIWAN
  • Correspondent: Not listed on recorded document.
  • Context: Original assignment from inventors to employer.
• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292
  • Conveyance: Assignment
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED, IRELAND
  • Correspondent: MATTHEW R. MUDD of FOLEY & LARDNER LLP, WASHINGTON, DC.
  • Context: Transfer of patent portfolio from operating company to a licensing entity.

Timeline diagram

timeline
    title Ownership of US 7745847
    2007 : Assigned to United Microelectronics Corp
    2010 : Issued
    2021 : Assigned to Marlin Semiconductor Ltd
    2025 : IPR filed by TSMC/Apple
         : ITC investigation initiated
         : Lawsuits filed by Marlin Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — present. In 2021, the patent was assigned from United Microelectronics Corporation (an operating company) to Marlin Semiconductor Limited, which is described as being "primarily engaged in holding or owning securities of companies other than banks, for the sole purpose of exercising some degree of control over the activities of the companies whose securities they hold" and an entity of IPValue Management, a patent monetization firm. Marlin Semiconductor Limited was formerly named "Sandyford Semiconductor Limited" and has an overlap in personnel with Longitude Licensing, another IPValue subsidiary. This aligns with the pattern of transferring patents to a licensing-only LLC.

2. Known asserter in the chain — present. Marlin Semiconductor Limited is an affiliate of IPValue Management. IPValue Management is a patent monetization firm. RPX, a defensive patent aggregator that tracks NPE activity, identifies Marlin Semiconductor Limited as one of the portfolios of IPValue Management, a monetization firm. Unified Patents also tracks NPEs and their litigation activities.

3. Repeat correspondent across the chain — not present. The initial assignment from inventors to UMC does not list a correspondent. The subsequent assignment to Marlin Semiconductor Limited lists MATTHEW R. MUDD of FOLEY & LARDNER LLP. There isn't enough information from the provided text to determine if this correspondent recurs across this chain or on other tracked patents.

4. Cascading transfers — not present. There are only two assignments recorded for this patent, and they are not consecutive transfers through chained LLCs in a short period.

5. Pre-litigation transfer — present. The patent was assigned to Marlin Semiconductor Limited on June 18, 2021 (executed) / July 26, 2021 (recorded). Litigation by Marlin Semiconductor Limited (an IPValue subsidiary) against Apple, Broadcom, Qualcomm, Lenovo, OnePlus, and TSMC using this patent, among others, began in the Western District of Texas and Eastern District of Texas in February 2025. An ITC investigation was also initiated in March 2025 based on a complaint filed by Longitude Licensing Ltd. and Marlin Semiconductor Limited. This transfer occurred approximately 3.5 years prior to litigation, which is outside the typical 6-month window for a "pre-litigation transfer" signal, but it is a transfer to a known monetization firm which then proceeds with litigation.

6. Bankruptcy fire-sale — not present. United Microelectronics Corp. is an active and operating company.

7. Privateering — unclear. While Marlin Semiconductor Limited is an affiliate of IPValue, a patent monetization firm, and the patent was transferred from an operating company (UMC), there is no explicit information detailing an arrangement where UMC is using Marlin Semiconductor to assert on its behalf against competitors.

8. Defensive aggregator (anti-NPE) — not present. The chain ends with Marlin Semiconductor Limited, an entity associated with patent monetization, not a defensive aggregator like RPX, AST, LOT Network, Unified Patents, or Open Invention Network. Notably, Taiwan Semiconductor Manufacturing Company (TSMC) and Apple Inc. have filed an Inter Partes Review (IPR) against Marlin Semiconductor Ltd. regarding this patent.

Verdict

NPE — high confidence. This verdict is based on multiple strong signals. The patent was transferred from an operating company, United Microelectronics Corp., to Marlin Semiconductor Limited in 2021 (Reel 056991/0292). Marlin Semiconductor Limited is identified as a shell entity and an affiliate of IPValue Management, a known patent monetization firm. Furthermore, Marlin Semiconductor Limited has initiated litigation involving this patent against multiple companies in 2025. These facts strongly indicate an NPE pattern.

Verification: https://assignmentcenter.uspto.gov/

The following is an analysis of the prior art cited in US patent 7745847, focusing on potential anticipation of its claims under 35 U.S.C. § 102. The effective filing date of US7745847 is 2007-08-09. All cited references predate this filing date.

The analysis of potential anticipation is primarily based on the titles of the cited patents, as detailed abstracts or full texts of the cited prior art were not retrieved by direct search for this task.

Claims of US7745847 for Reference:

The independent claim for the structure in US7745847 is Claim 1:

1. A MOS transistor structure, comprising:
   • a gate formed on a semiconductor substrate;
   • two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate;
   • a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate; and
   • two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate.

Dependent claims (2-11) elaborate on features of the gate, the type of MOS transistor (PMOS/NMOS), the material of the epitaxial layer (SiGe/SiC), details of the spacer (offset, oxide liner/nitride, L-shaped), the alignment of epitaxial layers and spacer, and the presence of lightly doped drains.

Most Relevant Prior Art for US7745847

1. US6110787A

   • Full Citation: US6110787A, "Method for fabricating a MOS device"
   • Publication/Filing Date: Publication: 2000-08-29; Priority: 1999-09-07
   • Brief Description: This patent describes a general method for fabricating a MOS device.
   • Potential Anticipation: Based solely on the title, this patent describes a method for fabricating a MOS device. Without further details on whether it includes raised epitaxial layers next to the gate with spacers extending laterally upon them and above the substrate surface, it is unlikely to fully anticipate the structural Claim 1. It might anticipate the broader concept of forming a gate on a substrate and doped regions, which are common elements of MOS transistors.

2. US6429084B1

   • Full Citation: US6429084B1, "MOS transistors with raised sources and drains"
   • Publication/Filing Date: Publication: 2002-08-06; Priority: 2001-06-20
   • Brief Description: This patent describes MOS transistors featuring raised sources and drains.
   • Potential Anticipation: This patent is highly relevant as it explicitly mentions "raised sources and drains," which aligns with the "two raised epitaxial layers" of US7745847's Claim 1. If these raised sources and drains are formed epitaxially and positioned next to the gate, and if the spacers interact with them in a manner where the bottom of the spacer is above the substrate surface, it could potentially anticipate Claim 1 and its dependent claims related to the nature of the epitaxial layers (e.g., Claim 3, 4, 5, 6) and general structure (Claim 2). The specific lateral extension and height details would need a deeper review of the full patent.

3. US6774000B2

   • Full Citation: US6774000B2, "Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures"
   • Publication/Filing Date: Publication: 2004-08-10; Priority: 2002-11-20
   • Brief Description: This patent details a manufacturing method for MOSFET devices that includes in-situ doped, raised source and drain structures.
   • Potential Anticipation: Similar to US6429084B1, this patent is highly relevant due to "raised source and drain structures." The "in-situ doped" aspect also directly relates to the optional in-situ doping mentioned in US7745847's description for forming source/drain regions. This could potentially anticipate Claim 1 (due to raised epitaxial layers/source-drain structures), Claim 2 (general gate structure), and particularly Claims 3, 4, 5, 6, and 11 (related to the doping and type of transistor/epitaxial material if those materials are disclosed). The method claim of US7745847, while not asked for here, would also find this highly relevant.

4. US6815770B1

   • Full Citation: US6815770B1, "MOS transistor having reduced source/drain extension sheet resistance"
   • Publication/Filing Date: Publication: 2004-11-09; Priority: 2003-08-14
   • Brief Description: This patent describes a MOS transistor design focused on reducing source/drain extension sheet resistance.
   • Potential Anticipation: While it addresses source/drain extensions, the title does not explicitly mention "raised epitaxial layers" or the specific spacer configuration of Claim 1 of US7745847. It might anticipate the "doped region" element of Claim 1 and general MOS transistor features (e.g., gate on substrate) but is less likely to anticipate the specific structural elements of the raised epitaxial layers and spacer interaction.

5. US20050156154A1

   • Full Citation: US20050156154A1, "Protecting Silicon Germanium Sidewall with Silicon for Strained Silicon/Silicon Germanium MOSFETs"
   • Publication/Filing Date: Publication: 2005-07-21; Priority: 2004-01-16
   • Brief Description: This publication describes a technique for protecting silicon germanium (SiGe) sidewalls with silicon in strained Si/SiGe MOSFETs.
   • Potential Anticipation: This reference is relevant to the use of SiGe for PMOS transistors to induce strain, which aligns with Claim 4 of US7745847. If the SiGe layers are "raised epitaxial layers" as described in Claim 1, it could anticipate Claim 1 and its dependent claims related to PMOS and SiGe (Claims 3 and 4). However, the title primarily focuses on sidewall protection rather than the raised nature of the source/drain itself or the specific spacer configuration.

6. US20060211245A1

   • Full Citation: US20060211245A1, "Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect"
   • Publication/Filing Date: Publication: 2006-09-21; Priority: 2003-12-03
   • Brief Description: This publication describes a method for forming abrupt junctions in semiconductor devices using a silicide growth dopant snowplow effect.
   • Potential Anticipation: This reference focuses on junction formation and doping profiles. While relevant to the "doped region" element of Claim 1, it does not explicitly disclose "raised epitaxial layers" or the specific spacer geometry of US7745847. Therefore, it is unlikely to anticipate Claim 1 as a whole, but might be relevant to the formation of the doped regions within the structure.

7. US7195985B2

   • Full Citation: US7195985B2, "CMOS transistor junction regions formed by a CVD etching and deposition sequence"
   • Publication/Filing Date: Publication: 2007-03-27; Priority: 2005-01-04
   • Brief Description: This patent describes the formation of CMOS transistor junction regions using a CVD etching and deposition sequence.
   • Potential Anticipation: This reference discusses CMOS transistor junction formation using CVD and etching. This is a general method. Unless the "deposition sequence" specifically involves raised epitaxial layers that interact with spacers as described in Claim 1 of US7745847, it is unlikely to anticipate Claim 1. It could be relevant to method claims of US7745847 regarding epitaxial growth or recess etching.

8. US20070298558A1

   • Full Citation: US20070298558A1, "Method of fabricating semiconductor device and semiconductor device"
   • Publication/Filing Date: Publication: 2007-12-27; Priority: 2006-06-22
   • Brief Description: This publication describes a method for fabricating a semiconductor device and the resulting device.
   • Potential Anticipation: The general title makes it difficult to assess specific anticipation without further detail. It broadly covers semiconductor device fabrication and the device itself. It might anticipate very general aspects of MOS transistors but lacks specificity regarding "raised epitaxial layers" and their interaction with spacers as defined in Claim 1 of US7745847.

9. US20080006818A1

   • Full Citation: US20080006818A1, "Structure and method to form multilayer embedded stressors"
   • Publication/Filing Date: Publication: 2008-01-10; Priority: 2006-06-09
   • Brief Description: This publication describes a structure and method for forming multilayer embedded stressors.
   • Potential Anticipation: This patent is relevant to the concept of stress engineering, which is the underlying goal of forming strained epitaxial layers in US7745847. If the "embedded stressors" are "raised epitaxial layers" in the context of US7745847 and the structure includes a gate and spacers interacting as defined in Claim 1, it could be highly relevant to Claim 1 and claims related to the epitaxial layer (Claims 3-6). The term "embedded" might suggest they are not necessarily "raised" above the substrate surface in the same way as in US7745847, requiring further investigation.

10. US20080032468A1

    • Full Citation: US20080032468A1, "Mos transistor and fabrication thereof"
    • Publication/Filing Date: Publication: 2008-02-07; Priority: 2006-08-01
    • Brief Description: This publication describes a MOS transistor and its fabrication.
    • Potential Anticipation: Similar to US20070298558A1, the general title provides insufficient detail to ascertain direct anticipation of Claim 1 of US7745847 without further review of the full patent content.

11. US20080179636A1

    • Full Citation: US20080179636A1, "N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers"
    • Publication/Filing Date: Publication: 2008-07-31; Priority: 2007-01-27
    • Brief Description: This publication describes N-type field-effect transistors (N-fets) with tensilely strained semiconductor channels, fabricated using buried pseudomorphic layers.
    • Potential Anticipation: This reference is relevant to NMOS transistors (Claim 5) and the concept of tensilely strained channels. The use of "buried pseudomorphic layers" suggests a stressor, which could be an epitaxial layer. If these layers are "raised" and the spacer interaction matches Claim 1 of US7745847, it could be highly relevant to Claim 1, and particularly Claims 5 and 6 (if SiC or another tensile strain material is used). The term "buried" might again differentiate it from "raised" as taught in US7745847.

Conclusion on Most Relevant Prior Art:

Based on the titles and their direct relevance to the key features of US7745847's independent structure claim (Claim 1), the most relevant prior art documents appear to be those that explicitly mention "raised sources and drains" or "raised source and drain structures," and those related to strain engineering using specific materials like SiGe or SiC.

• US6429084B1 ("MOS transistors with raised sources and drains")
• US6774000B2 ("Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures")

These two patents directly address the concept of "raised" source/drain regions, which are the "raised epitaxial layers" in US7745847. Their relevance would depend on whether they also teach the specific interaction of the spacer with these raised layers, where the spacer extends laterally upon a portion of the raised epitaxial layers and its bottom is above the surface of the semiconductor substrate, as claimed in US7745847.

Additionally, patents like US20050156154A1 (SiGe for strained Si/SiGe MOSFETs), US20080006818A1 (multilayer embedded stressors), and US20080179636A1 (N-fets with tensilely strained channels using buried pseudomorphic layers) are also highly relevant due to their focus on strain engineering and specific materials (SiGe/SiC), which are details provided in the dependent claims of US7745847. Their potential to anticipate Claim 1 would depend on whether their described stressor structures are "raised epitaxial layers" that interact with spacers in the manner claimed. Without the full text of these cited patents, a definitive conclusion on complete anticipation of Claim 1 cannot be made, but they represent the strongest candidates for relevance to the inventive concept of US7745847.

Obviousness Analysis of US Patent 7,745,847 Under 35 U.S.C. § 103

This analysis addresses the obviousness of US patent 7,745,847 (hereinafter '847 patent) under 35 U.S.C. § 103, based solely on the prior art references listed in the "Citations" section of the '847 patent and the description of the prior art contained within the '847 patent itself.

The '847 Patent's Independent Claim

Claim 1 of US7745847B2, the independent claim for the MOS transistor structure, recites:
"1. A MOS transistor structure, comprising:
a gate formed on a semiconductor substrate;
two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate;
a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate; and
two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate."

The '847 patent's background describes the problem it aims to solve: conventional methods for obtaining strained channels (e.g., epitaxially growing a SiGe layer adjacent to spacers after forming the spacers) have difficulty achieving the required extent of compressive or tensile stress for improved carrier mobility. The invention's solution, as highlighted in its detailed description, is to form the epitaxial layer before the spacer, leading to a specific structural arrangement where the spacer extends laterally upon a portion of the raised epitaxial layer.

Combination of Prior Art References

A person having ordinary skill in the art (PHOSITA) would have found the structure of Claim 1 of the '847 patent obvious in view of the combination of:

• US 6,429,084 B1 (IBM - '084 patent), titled "MOS transistors with raised sources and drains"
• US 6,110,787 A (Chartered Semiconductor Manufacturing Ltd. - '787 patent), titled "Method for fabricating a MOS device"
• General knowledge in the art regarding the benefits of strained epitaxial layers in MOS transistors, as acknowledged in the background of the '847 patent.

Reasoning for Obviousness

1. Gate formed on a semiconductor substrate: This fundamental element of a MOS transistor is universally known and taught by numerous prior art references, including the '787 patent, which describes a "Method for fabricating a MOS device".

2. Two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate: The '084 patent explicitly teaches "MOS transistors with raised sources and drains". A PHOSITA would readily understand that these "raised sources and drains" are positioned adjacent to the gate. Furthermore, given the problem in the art (improving carrier mobility through mechanical stress in the channel, as described in the '847 patent's background), a PHOSITA would know that such raised source/drain regions are commonly formed using epitaxial growth, particularly with materials like SiGe or SiC, to induce strain. The term "raised" inherently means the structures are "above the surface of the semiconductor substrate."

3. A spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate: The formation of spacers on the sidewalls of a gate is a standard and routine fabrication step in MOS technology, as would be understood from general knowledge in the field or taught by a generic MOS fabrication patent like the '787 patent. Given the teaching of "raised sources and drains" from the '084 patent, a PHOSITA, when integrating these raised structures with a standard gate and spacer configuration, would find it a natural and expected outcome, or a straightforward design choice, for the subsequently formed spacers to extend laterally onto a portion of these pre-existing raised regions. The specific geometric requirement that "a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate" is an inherent consequence of the epitaxial layers themselves being "raised" above the substrate surface, meaning any spacer sitting on them would also have its bottom surface above the original substrate surface.

4. Two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate: Doped source/drain regions are essential components of any MOS transistor, as taught by the '787 patent. Furthermore, US 6,774,000 B2 (IBM - '000 patent), also cited as prior art, specifically teaches a "Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures," directly disclosing doped regions within raised structures.

Motivation to Combine

A PHOSITA would have been motivated to combine the teachings of the '084 patent and the '787 patent, coupled with general knowledge in the art, to produce a high-performance MOS transistor. The '084 patent teaches the benefit of "raised sources and drains", which can reduce parasitic resistance and improve gate control. The '787 patent teaches the general fabrication of MOS devices, including gates and spacers. The background of the '847 patent itself highlights the well-known objective of enhancing carrier mobility by introducing mechanical stress, often achieved through epitaxial growth of materials like SiGe or SiC in the source/drain regions.

Therefore, a PHOSITA would recognize the desirability of combining these known features: employing raised source/drain structures (for improved device geometry and reduced resistance) that are formed epitaxially (for strain-induced mobility enhancement). In such a combined structure, the resulting physical arrangement where spacers, formed on the gate sidewalls, extend laterally over a portion of these pre-existing raised epitaxial source/drain regions would be an expected and obvious outcome of integrating these known elements in a functional MOS transistor. This integration would involve routine engineering choices to optimize device characteristics, not an inventive step. The claimed structure represents a straightforward arrangement of known components, and their spatial relationship would be an obvious design consideration for a PHOSITA seeking to integrate these features for improved performance.