US 8076194

US Patent 8076194, titled "Method of fabricating metal oxide semiconductor transistor," was issued on December 13, 2011, from an application filed on May 18, 2010. The current assignee is Marlin Semiconductor Ltd, though it was originally assigned to United Microelectronics Corp. The inventors are Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, and Hsuan-Hsu Chen.

Abstract:
A method of fabricating a MOS transistor is disclosed. The method includes providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, with the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, where the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, where a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

Plain-language overview of independent claims:

• Independent Claim 1: This claim describes a method for making a Metal Oxide Semiconductor (MOS) transistor. The key steps involve creating a gate on a semiconductor substrate, then putting a protective layer over the entire substrate, including the gate. Next, a trench (recess) is formed in the substrate next to the gate. An epitaxial layer is then grown in this trench, extending above the original surface of the semiconductor substrate. Finally, a spacer is formed on the side of the gate, which also extends over part of this raised epitaxial layer, such that the point where the epitaxial layer and the spacer meet is above the substrate's surface.

• Independent Claim 10: This claim focuses on a method for fabricating a Complementary Metal Oxide Semiconductor (CMOS) transistor, which involves both "first conductive" (e.g., PMOS) and "second conductive" (e.g., NMOS) transistor areas separated by an isolation structure. Similar to Claim 1, it involves forming a gate in each area and then a first protective layer covering the substrate and gates. A first recess is created in the first conductive transistor area next to its gate, and a first epitaxial layer is grown in this recess, extending above the substrate surface. A spacer is then formed on the sidewall of each gate and over a portion of this first epitaxial layer, with the contact surface between the epitaxial layer and spacer being above the substrate surface.

No specific litigation related to US patent 8076194 was found in the CAFC 2026 dockets. However, Google Patents notes that there is pending litigation, specifically PTAB case IPR2026-00061 filed, and mentions "Family has litigation" with a link to Darts-ip. This indicates that while no CAFC dockets were found, other legal proceedings are active.