US 11456365

Here is a concise summary of US Patent 11456365:

US Patent 11456365

• Title: Memory transistor with multiple charge storing layers and a high work function gate electrode
• Assignee: Longitude Flash Memory Solutions Ltd
• Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
• Filing Date: January 25, 2021
• Issue Date: September 27, 2022
• Abstract: The patent describes a memory device featuring a channel connecting two diffusion regions, a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer situated between a gate structure and the channel. The key innovation in the multi-layer charge trapping layer is its composition: a first oxygen-rich nitride dielectric layer and a second oxygen-lean nitride dielectric layer, separated by an oxide anti-tunneling layer.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Memory Device):
  This claim describes a memory device. It includes a conductive path (channel) between two electrically active regions (first and second diffusion regions). Above this channel, there's a stack of insulating layers:

  1. A "tunnel dielectric layer" directly above the channel.
  2. A "multi-layer charge trapping layer" above the tunnel dielectric. This trapping layer is special: it has a first dielectric layer (oxygen-rich nitride) and a second dielectric layer (oxygen-lean nitride) positioned next to each other. An "anti-tunneling layer" made of oxide is placed between these two nitride layers.
  3. A "gate structure" positioned above the entire multi-layer charge trapping stack.

• Independent Claim 13 (Memory Device):
  This claim also describes a memory device, similar to Claim 1, with a channel between two diffusion regions and a tunnel dielectric layer above the channel. The key difference lies in the description of the multi-layer charge trapping layer: it specifically includes an "oxygen-rich first nitride layer" and an "oxygen-lean second nitride layer" situated above the first nitride layer. It does not explicitly require the anti-tunneling layer in this top-level claim, although dependent claims might add it. A gate structure is disposed above this multi-layer charge trapping layer.

• Independent Claim 25 (Method of Forming a Memory Device):
  This claim outlines a method for manufacturing a memory device. The steps correspond to building the device described in Claim 13:

  1. Creating the conductive path (channel) between the first and second diffusion regions.
  2. Forming the tunnel dielectric layer above the channel.
  3. Forming the multi-layer charge trapping layer above the tunnel dielectric. This involves creating an "oxygen-rich first nitride layer" and an "oxygen-lean second nitride layer" above the first nitride layer.
  4. Forming the gate structure above the multi-layer charge trapping layer.

• Independent Claim 37 (Method of Forming a Memory Device):
  This claim describes another method for manufacturing a memory device, aligning with the device structure of Claim 1. The steps are:

  1. Creating the channel between the first and second diffusion regions.
  2. Forming the tunnel dielectric layer above the channel.
  3. Forming the multi-layer charge trapping layer above the tunnel dielectric. This involves forming a first dielectric layer (oxygen-rich nitride) abutting a second dielectric layer (oxygen-lean nitride), and crucially, forming an "oxide anti-tunneling layer" between these two dielectric layers.
  4. Forming the gate structure above the multi-layer charge trapping layer.

USPTO and CAFC Docket Search:

As of April 26, 2026:

• USPTO: The patent US11456365 is active and was granted on September 27, 2022, with an adjusted expiration date of September 7, 2028.
• CAFC 2026 Dockets: A direct search for CAFC 2026 dockets specifically for patent 11456365 did not yield immediate results in the provided search snippets. Therefore, there is no authoritative information from this search to confirm any cases currently before the Federal Circuit in 2026.
• Related Litigation (from patent metadata): The patent family is noted to have ongoing litigation. Specifically, a PTAB case IPR2025-01281 has been filed (with a status of "Settlement"), and US cases have been filed in both the California Northern District Court (5:25-cv-02389) and the California Central District Court (8:25-cv-00119). These district court and PTAB cases are at lower levels than the CAFC and may or may not lead to future appeals at the Federal Circuit.