US 11456365

Here is a concise summary of US Patent 11456365:

US Patent 11456365

• Title: Memory transistor with multiple charge storing layers and a high work function gate electrode
• Assignee: Longitude Flash Memory Solutions Ltd
• Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
• Filing Date: January 25, 2021
• Issue Date: September 27, 2022
• Abstract: The patent describes a memory device featuring a channel connecting two diffusion regions, a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer situated between a gate structure and the channel. The key innovation in the multi-layer charge trapping layer is its composition: a first oxygen-rich nitride dielectric layer and a second oxygen-lean nitride dielectric layer, separated by an oxide anti-tunneling layer.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Memory Device):
  This claim describes a memory device. It includes a conductive path (channel) between two electrically active regions (first and second diffusion regions). Above this channel, there's a stack of insulating layers:

  1. A "tunnel dielectric layer" directly above the channel.
  2. A "multi-layer charge trapping layer" above the tunnel dielectric. This trapping layer is special: it has a first dielectric layer (oxygen-rich nitride) and a second dielectric layer (oxygen-lean nitride) positioned next to each other. An "anti-tunneling layer" made of oxide is placed between these two nitride layers.
  3. A "gate structure" positioned above the entire multi-layer charge trapping stack.

• Independent Claim 13 (Memory Device):
  This claim also describes a memory device, similar to Claim 1, with a channel between two diffusion regions and a tunnel dielectric layer above the channel. The key difference lies in the description of the multi-layer charge trapping layer: it specifically includes an "oxygen-rich first nitride layer" and an "oxygen-lean second nitride layer" situated above the first nitride layer. It does not explicitly require the anti-tunneling layer in this top-level claim, although dependent claims might add it. A gate structure is disposed above this multi-layer charge trapping layer.

• Independent Claim 25 (Method of Forming a Memory Device):
  This claim outlines a method for manufacturing a memory device. The steps correspond to building the device described in Claim 13:

  1. Creating the conductive path (channel) between the first and second diffusion regions.
  2. Forming the tunnel dielectric layer above the channel.
  3. Forming the multi-layer charge trapping layer above the tunnel dielectric. This involves creating an "oxygen-rich first nitride layer" and an "oxygen-lean second nitride layer" above the first nitride layer.
  4. Forming the gate structure above the multi-layer charge trapping layer.

• Independent Claim 37 (Method of Forming a Memory Device):
  This claim describes another method for manufacturing a memory device, aligning with the device structure of Claim 1. The steps are:

  1. Creating the channel between the first and second diffusion regions.
  2. Forming the tunnel dielectric layer above the channel.
  3. Forming the multi-layer charge trapping layer above the tunnel dielectric. This involves forming a first dielectric layer (oxygen-rich nitride) abutting a second dielectric layer (oxygen-lean nitride), and crucially, forming an "oxide anti-tunneling layer" between these two dielectric layers.
  4. Forming the gate structure above the multi-layer charge trapping layer.

USPTO and CAFC Docket Search:

As of April 26, 2026:

• USPTO: The patent US11456365 is active and was granted on September 27, 2022, with an adjusted expiration date of September 7, 2028.
• CAFC 2026 Dockets: A direct search for CAFC 2026 dockets specifically for patent 11456365 did not yield immediate results in the provided search snippets. Therefore, there is no authoritative information from this search to confirm any cases currently before the Federal Circuit in 2026.
• Related Litigation (from patent metadata): The patent family is noted to have ongoing litigation. Specifically, a PTAB case IPR2025-01281 has been filed (with a status of "Settlement"), and US cases have been filed in both the California Northern District Court (5:25-cv-02389) and the California Central District Court (8:25-cv-00119). These district court and PTAB cases are at lower levels than the CAFC and may or may not lead to future appeals at the Federal Circuit.

The Google Patents page for US11456365B2 indicates that the "Family has litigation" and lists several litigation events.

Known litigation involving US patent 11456365 includes:

• PTAB case IPR2025-01281

  • Outcome/Status: Filed (Settlement)

• US case filed in California Northern District Court

  • Jurisdiction: California Northern District Court
  • Case Number: 5:25-cv-02389
  • Source: District Court

• US case filed in California Central District Court

  • Jurisdiction: California Central District Court
  • Case Number: 8:25-cv-00119
  • Source: District Court

Please note that specific details such as plaintiff(s), defendant(s), and filing dates for the district court cases are not directly provided in the Google Patents summary but generally can be found by looking up the case numbers on PACER or through services like Unified Patents or Darts-ip (which provide access to court documents and case summaries). The provided information from Google Patents only indicates the jurisdiction, case number, and source for these cases.Known litigation involving US patent 11456365 includes:

• PTAB Case:

  • Case Number: IPR2025-01281
  • Outcome/Status: Filed (Settlement)
  • Additional Details: Specific plaintiff(s) and defendant(s) are not directly provided in the available summary, but IPR cases typically involve a petitioner challenging the patent owner.

• US District Court Case (California Northern District Court):

  • Jurisdiction: California Northern District Court
  • Case Number: 5:25-cv-02389
  • Additional Details: Specific plaintiff(s), defendant(s), and filing date are not directly provided in the available summary.

• US District Court Case (California Central District Court):

  • Jurisdiction: California Central District Court
  • Case Number: 8:25-cv-00119
  • Additional Details: Specific plaintiff(s), defendant(s), and filing date are not directly provided in the available summary.

Proceedings overview

One AIA trial proceeding has been filed against US patent 11456365. This proceeding, IPR2025-01281, was terminated due to a settlement between the parties. This means the claims of the patent have not been fully adjudicated by the PTAB, and the patent's validity has not been tested through a Final Written Decision. For a defendant, this indicates the patent claims remain untested by the PTAB, and an IPR defense remains an option, though the specific claims and prior art raised in the settled IPR may face estoppel for the petitioner and its privies.

IPR2025-01281 — Sandisk Technologies, Inc. et al. v. Longitude Flash Memory Solutions Ltd.

• Type: Inter Partes Review
• Filed: 2025-09-03
• Status: Terminated-Settled. This indicates the proceeding concluded without a Final Written Decision, likely due to an agreement between the petitioner and the patent owner.
• Judge panel: Not publicly available from the provided data or general search for a settled case prior to institution or FWD.
• Petition grounds: This information is not explicitly available from the structured data. A specific search would be required to retrieve the petition document from the USPTO PTAB E2E system to determine the challenged claims, prior art, and statutory bases (§ 102 / § 103 / § 112).
• Institution decision: The proceeding status is "Terminated-Settled" as of 2026-02-20, which is prior to the typical one-year deadline for a final written decision (September 2026). It is highly probable that an institution decision was never reached or was issued shortly before settlement, as settlement often occurs at or after institution. Without specific access to the PTAB E2E docket for IPR2025-01281, the exact date and panel's reasoning for institution (or denial) are not publicly available from the provided data or general search.
• Final Written Decision (if issued): No Final Written Decision was issued as the proceeding was Terminated-Settled.
• Settlement / termination: The proceeding was terminated as settled on 2026-02-20. The specific terms of the settlement are confidential between Sandisk Technologies, Inc. et al. and Longitude Flash Memory Solutions Ltd.
• Appeal: Given the termination via settlement and absence of a Final Written Decision, no Federal Circuit appeal would have occurred.
• Defensive value: This proceeding did not result in any claims being invalidated by the PTAB. However, the fact that a large entity like Sandisk Technologies, Inc. filed an IPR could indicate potential validity concerns with the patent. The claims of US11456365 remain untested by a PTAB Final Written Decision.

Strategic summary

There is one AIA trial proceeding, IPR2025-01281, on file for US patent 11456365. This IPR was initiated by Sandisk Technologies, Inc. et al. but was ultimately terminated as settled on 2026-02-20, before a Final Written Decision could be rendered. Consequently, no claims of US11456365 have been officially canceled or sustained by the PTAB. All claims of the patent are therefore considered UNTESTED by the PTAB.

Regarding the estoppel landscape, Section 315(e)(2) estoppel, which bars petitioners and their privies from raising grounds that were raised or reasonably could have been raised, typically applies after a Final Written Decision is issued. Since IPR2025-01281 was terminated by settlement, it is unlikely that statutory estoppel under § 315(e)(2) would apply in the same manner as if a FWD had been issued. However, contractual estoppel (via the settlement agreement) could prevent Sandisk and its privies from challenging the patent again using the same or similar prior art. For a new defendant facing assertion of this patent, virtually all prior-art grounds remain available for a potential new IPR filing, assuming they are not in privity with Sandisk Technologies, Inc. et al.

The involvement of Sandisk Technologies, Inc., a significant player in the memory technology space, suggests that the patent claims may have been viewed as potentially problematic or impactful by a competitor. The settlement before a decision could indicate a mutually beneficial agreement, rather than a definitive statement on the patent's validity. There is no public pattern of aggressive PTAB appeals by the patent owner or involvement of defensive aggregators indicated by this single proceeding.

Recommended next steps

Since IPR2025-01281 was terminated by settlement and no claims were adjudicated, there is no Final Written Decision to link to for invalidated claims. The patent claims remain untested by the PTAB.

For a defendant considering challenging US11456365:

• Investigate the settlement: While the terms are confidential, understanding the context or any public statements around the settlement for IPR2025-01281 might offer insights into the patent owner's or petitioner's positions.
• Conduct a thorough prior art search: Given that the patent's claims haven't been tested by a PTAB FWD, a fresh and comprehensive prior art search is crucial to identify strong grounds for a new IPR petition, should one be necessary.
• Evaluate claims independently: Carefully analyze the claims of US11456365, particularly those cited in any assertion, against newly identified or existing prior art to determine the strength of potential invalidity arguments.
• Consider a new IPR filing: If strong prior art grounds are found, filing a new IPR remains a viable strategy as estoppel from the settled IPR is unlikely to apply to an unrelated defendant.## Proceedings overview
  One AIA trial proceeding has been filed against US patent 11456365. This proceeding, IPR2025-01281, was terminated due to a settlement between the parties. This means the claims of the patent have not been fully adjudicated by the PTAB, and the patent's validity has not been tested through a Final Written Decision. For a defendant, this indicates the patent claims remain untested by the PTAB, and an IPR defense remains an option, though the specific claims and prior art raised in the settled IPR may face estoppel for the petitioner and its privies.

IPR2025-01281 — Sandisk Technologies, Inc. et al. v. Longitude Flash Memory Solutions Ltd.

• Type: Inter Partes Review
• Filed: 2025-09-03
• Status: Terminated-Settled. This indicates the proceeding concluded without a Final Written Decision, likely due to an agreement between the petitioner and the patent owner.
• Judge panel: Not publicly available from the provided data or general search for a settled case prior to institution or FWD.
• Petition grounds: This information is not explicitly available from the structured data. A specific search would be required to retrieve the petition document from the USPTO PTAB E2E system to determine the challenged claims, prior art, and statutory bases (§ 102 / § 103 / § 112).
• Institution decision: The proceeding status is "Terminated-Settled" as of 2026-02-20, which is prior to the typical one-year deadline for a final written decision (September 2026). It is highly probable that an institution decision was never reached or was issued shortly before settlement, as settlement often occurs at or after institution. Without specific access to the PTAB E2E docket for IPR2025-01281, the exact date and panel's reasoning for institution (or denial) are not publicly available from the provided data or general search.
• Final Written Decision (if issued): No Final Written Decision was issued as the proceeding was Terminated-Settled.
• Settlement / termination: The proceeding was terminated as settled on 2026-02-20. The specific terms of the settlement are confidential between Sandisk Technologies, Inc. et al. and Longitude Flash Memory Solutions Ltd.
• Appeal: Given the termination via settlement and absence of a Final Written Decision, no Federal Circuit appeal would have occurred.
• Defensive value: This proceeding did not result in any claims being invalidated by the PTAB. However, the fact that a large entity like Sandisk Technologies, Inc. filed an IPR could indicate potential validity concerns with the patent. The claims of US11456365 remain untested by a PTAB Final Written Decision.

Strategic summary

There is one AIA trial proceeding, IPR2025-01281, on file for US patent 11456365. This IPR was initiated by Sandisk Technologies, Inc. et al. but was ultimately terminated as settled on 2026-02-20, before a Final Written Decision could be rendered. Consequently, no claims of US11456365 have been officially canceled or sustained by the PTAB. All claims of the patent are therefore considered UNTESTED by the PTAB.

Regarding the estoppel landscape, Section 315(e)(2) estoppel, which bars petitioners and their privies from raising grounds that were raised or reasonably could have been raised, typically applies after a Final Written Decision is issued. Since IPR2025-01281 was terminated by settlement, it is unlikely that statutory estoppel under § 315(e)(2) would apply in the same manner as if a FWD had been issued. However, contractual estoppel (via the settlement agreement) could prevent Sandisk and its privies from challenging the patent again using the same or similar prior art. For a new defendant facing assertion of this patent, virtually all prior-art grounds remain available for a potential new IPR filing, assuming they are not in privity with Sandisk Technologies, Inc. et al.

The involvement of Sandisk Technologies, Inc., a significant player in the memory technology space, suggests that the patent claims may have been viewed as potentially problematic or impactful by a competitor. The settlement before a decision could indicate a mutually beneficial agreement, rather than a definitive statement on the patent's validity. There is no public pattern of aggressive PTAB appeals by the patent owner or involvement of defensive aggregators indicated by this single proceeding.

Recommended next steps

Since IPR2025-01281 was terminated by settlement and no claims were adjudicated, there is no Final Written Decision to link to for invalidated claims. The patent claims remain untested by the PTAB.

For a defendant considering challenging US11456365:

• Investigate the settlement: While the terms are confidential, understanding the context or any public statements around the settlement for IPR2025-01281 might offer insights into the patent owner's or petitioner's positions.
• Conduct a thorough prior art search: Given that the patent's claims haven't been tested by a PTAB FWD, a fresh and comprehensive prior art search is crucial to identify strong grounds for a new IPR petition, should one be necessary.
• Evaluate claims independently: Carefully analyze the claims of US11456365, particularly those cited in any assertion, against newly identified or existing prior art to determine the strength of potential invalidity arguments.
• Consider a new IPR filing: If strong prior art grounds are found, filing a new IPR remains a viable strategy as estoppel from the settled IPR is unlikely to apply to an unrelated defendant.

Inventors

• Igor Polishchuk: Not explicitly stated, but likely employed by Longitude Flash Memory Solutions Ltd. at the time of filing, as they are the original assignee.
• Sagy Charel Levy: Not explicitly stated, but likely employed by Longitude Flash Memory Solutions Ltd. at the time of filing.
• Krishnaswamy Ramkumar: Not explicitly stated, but likely employed by Longitude Flash Memory Solutions Ltd. at the time of filing.

No unusual patterns (e.g., all inventors departing the original assignee within 12 months of filing) are determinable from the provided information.

Original assignee

The original assignee is Longitude Flash Memory Solutions Ltd.

It is unclear from the provided patent text whether Longitude Flash Memory Solutions Ltd. shipped a product embodying the claims. The patent generally describes semiconductor devices, specifically non-volatile memory transistors, which are components within electronic products rather than end-user products themselves.

Their primary line of business, based on the patent's technical field, is semiconductor devices and integrated circuits, particularly non-volatile semiconductor memories.

Their current status (operating, acquired, dissolved, in bankruptcy) is not determinable from the provided patent information.

Assignment timeline

The USPTO Assignment Center search for patent US11456365 shows no recorded assignments for this specific patent. This indicates that the original assignee, Longitude Flash Memory Solutions Ltd., still holds the direct assignment record for this patent, as far as the USPTO's public assignment database reflects.

However, further investigation into Longitude Flash Memory Solutions Ltd. and its affiliates provides important context regarding the ownership and licensing of this patent. Longitude Flash Memory Solutions, Ltd. (LFMS) is an affiliate of IPValue Management, Inc. (IPValue) and Longitude Licensing Ltd. (LLL). IPValue is a company that specializes in monetizing intellectual property portfolios. LFMS acquired its patent portfolio, including patents related to memory technology, from Cypress Semiconductor, which was acquired by Infineon Technologies in 2020. Longitude Licensing Ltd., as an exclusive licensee or in conjunction with IPValue Management, Inc., conducts the licensing of the LFMS portfolio.

Therefore, while the direct assignment record for US11456365 isn't publicly recorded as transferred from Longitude Flash Memory Solutions Ltd. to another entity in the USPTO Assignment Center, the patent is part of a portfolio managed and licensed by Longitude Licensing Ltd. and IPValue Management, Inc.

Timeline diagram

timeline
    title Ownership of US 11456365
    2007 : Priority date May 25
    2008 : Filed by Longitude Flash Memory Solutions Ltd
    2022 : Issued to Longitude Flash Memory Solutions Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — Present. Although there is no direct assignment recorded in the USPTO Assignment Center for US11456365, Longitude Flash Memory Solutions Ltd. (LFMS) is an affiliate of IPValue Management, Inc. (IPValue) and Longitude Licensing Ltd. (LLL). IPValue's mission is to unlock value from IP portfolios and has generated billions from patent licenses, indicating a focus on patent monetization rather than product manufacturing. Longitude Licensing Ltd. is explicitly described as a "patent licensing entity." Longitude Licensing is based in Dublin, Ireland, and privately owned by Vector Capital. These characteristics strongly suggest that LFMS and LLL operate as licensing-only entities.

2. Known asserter in the chain — Present. Longitude Licensing Ltd. and its affiliates, including Longitude Flash Memory Solutions Ltd., are explicitly associated with IPValue Management, Inc. IPValue Management is a known entity in the patent monetization space, often referred to in the context of patent assertion. IPValue Management's affiliates have been involved in various patent litigation, including against companies like SK Hynix, Samsung, Micron, and Sandisk.

3. Repeat correspondent across the chain — Unclear. Without specific reel/frame entries for assignments of US11456365 from the USPTO Assignment Center, it is not possible to determine if the same correspondent attorney has appeared multiple times in the chain for this specific patent.

4. Cascading transfers — Unclear. No recorded assignments for US11456365 are present in the USPTO Assignment Center, so cascading transfers cannot be identified for this specific patent.

5. Pre-litigation transfer — Unclear. As there are no recorded assignments for this patent in the USPTO Assignment Center, it is not possible to determine if a transfer occurred within 6 months of litigation. However, the current litigation involving Longitude Flash Memory Solutions Ltd. (e.g., IPR2025-01281 filed by Sandisk Technologies, Inc. against LFMS) suggests that the patent is part of an asserted portfolio.

6. Bankruptcy fire-sale — Not Present. There is no information in the provided patent text or search results to suggest that Longitude Flash Memory Solutions Ltd. or any prior owner underwent a bankruptcy fire-sale.

7. Privateering — Unclear. While Longitude Flash Memory Solutions Ltd. acquired its patent portfolio from Cypress Semiconductor, which was later acquired by Infineon Technologies, there's no direct evidence in the provided text to confirm that Longitude is asserting these patents on behalf of Cypress/Infineon against their competitors.

8. Defensive aggregator (anti-NPE) — Not Present. The information indicates that Longitude Flash Memory Solutions Ltd. and its affiliates are involved in licensing and assertion, which is contrary to the role of a defensive aggregator.

Verdict

NPE — high confidence

Longitude Flash Memory Solutions Ltd. (LFMS) is an affiliate of IPValue Management, Inc. (IPValue) and Longitude Licensing Ltd. (LLL), both of which are known patent monetization entities. IPValue's stated mission to "unlock value from their IP portfolios" through licensing, and LLL being a "patent licensing entity," strongly indicates an NPE model. Furthermore, LFMS has been actively involved in licensing agreements and litigation with major semiconductor companies like SK Hynix, Samsung, Micron, and Sandisk. The IPR case IPR2025-01281 filed by Sandisk Technologies, Inc. against Longitude Flash Memory Solutions Ltd. also confirms assertion activity.

(Verification: Search US11456365 at https://assignmentcenter.uspto.gov/)

To identify the most relevant prior art for US patent 11456365, I will search the USPTO database for the patent and then analyze its cited references. As an AI, I cannot directly access or "search" the USPTO database in the same way a human would use the online portal. However, I can leverage the provided patent text, which includes "Prior art keywords" and a "CROSS-REFERENCE TO RELATED APPLICATIONS" section, to identify relevant prior art documents.

The patent text itself serves as the authoritative source for its cited prior art. I will extract the direct citations mentioned within US11456365B2 to fulfill the request.

Here's the analysis of the most relevant prior art for US Patent 11456365, based on the cross-referenced applications within the patent document:

The "CROSS-REFERENCE TO RELATED APPLICATIONS" section of US11456365B2 explicitly links it to a chain of prior applications, indicating they are foundational to the current patent. These represent critical prior art as they contain the development history and preceding claims.

Most Relevant Prior Art (Directly cited in the Cross-Reference section):

1. U.S. patent application Ser. No. 16/429,464

   • Full Citation: U.S. patent application Ser. No. 16/429,464, filed Jun. 3, 2019.
   • Publication/Filing Date: June 3, 2019.
   • Brief Description: This is a direct continuation of Ser. No. 15/864,832. As a direct continuation, it is highly likely to share substantial inventive subject matter with US11456365B2.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This application likely anticipates all claims of US11456365B2 that were present in Ser. No. 16/429,464 as filed. Without the full text of Ser. No. 16/429,464, it's impossible to state specific claims, but as a continuation, it would typically cover the same or very similar inventive concepts.

2. U.S. patent application Ser. No. 15/864,832

   • Full Citation: U.S. patent application Ser. No. 15/864,832, filed Jan. 8, 2018, now U.S. Pat. No. 10,312,336, issued Jun. 4, 2019.
   • Publication/Filing Date: January 8, 2018 (filed).
   • Brief Description: This is a continuation of Ser. No. 15/335,180 and subsequently issued as U.S. Pat. No. 10,312,336. The issuance as a patent indicates it contains patentable subject matter directly related to the family of inventions.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This patent and application would likely anticipate claims in US11456365B2 that are common to the scope of U.S. Pat. No. 10,312,336.

3. U.S. patent application Ser. No. 15/335,180

   • Full Citation: U.S. patent application Ser. No. 15/335,180, filed on Oct. 26, 2016 now U.S. Pat. No. 9,929,240, issued Mar. 27, 2018.
   • Publication/Filing Date: October 26, 2016 (filed).
   • Brief Description: This is a continuation of Ser. No. 14/811,346 and issued as U.S. Pat. No. 9,929,240.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Claims in US11456365B2 that are directly found in U.S. Pat. No. 9,929,240 are potentially anticipated.

4. U.S. patent application Ser. No. 14/811,346

   • Full Citation: U.S. patent application Ser. No. 14/811,346, filed Jul. 28, 2015, now U.S. Pat. No. 9,502,543, issued on Nov. 22, 2016.
   • Publication/Filing Date: July 28, 2015 (filed).
   • Brief Description: This is a continuation of Ser. No. 14/159,315 and issued as U.S. Pat. No. 9,502,543.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Claims in US11456365B2 that are directly found in U.S. Pat. No. 9,502,543 are potentially anticipated.

5. U.S. patent application Ser. No. 14/159,315

   • Full Citation: U.S. patent application Ser. No. 14/159,315, filed on Jan. 20, 2014, now U.S. Pat. No. 9,093,318, issued on Jul. 28, 2015.
   • Publication/Filing Date: January 20, 2014 (filed).
   • Brief Description: This is a continuation of Ser. No. 13/539,466 and issued as U.S. Pat. No. 9,093,318.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Claims in US11456365B2 that are directly found in U.S. Pat. No. 9,093,318 are potentially anticipated.

6. U.S. patent application Ser. No. 13/539,466

   • Full Citation: U.S. patent application Ser. No. 13/539,466, filed on Jul. 1, 2012, now U.S. Pat. No. 8,633,537, issued on Jan. 21, 2014.
   • Publication/Filing Date: July 1, 2012 (filed).
   • Brief Description: This is a continuation-in-part of Ser. No. 13/288,919 and issued as U.S. Pat. No. 8,633,537. A continuation-in-part means it includes subject matter from the earlier application but also new subject matter. The shared subject matter is prior art.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Claims in US11456365B2 that are common to the subject matter disclosed in U.S. Pat. No. 8,633,537 are potentially anticipated.

7. U.S. patent application Ser. No. 13/288,919

   • Full Citation: U.S. patent application Ser. No. 13/288,919, filed Nov. 3, 2011, now U.S. Pat. No. 8,859,374, issued on Oct. 14, 2014.
   • Publication/Filing Date: November 3, 2011 (filed).
   • Brief Description: This is a divisional of U.S. patent Ser. No. 12/152,518 and issued as U.S. Pat. No. 8,859,374. A divisional application typically covers different claims to the same inventive subject matter as the parent application.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Claims in US11456365B2 that claim the same invention as disclosed and claimed in U.S. Pat. No. 8,859,374 are potentially anticipated.

8. U.S. patent Ser. No. 12/152,518

   • Full Citation: U.S. patent Ser. No. 12/152,518, filed May 13, 2008, now U.S. Pat. No. 8,063,434, issued Nov. 22, 2011.
   • Publication/Filing Date: May 13, 2008 (filed).
   • Brief Description: This application is the direct parent of the divisional application Ser. No. 13/288,919 and claims the benefit of priority to U.S. Provisional Patent Application No. 60/940,160. Issued as U.S. Pat. No. 8,063,434.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This patent is a core piece of prior art for US11456365B2, and any claims in US11456365B2 that are disclosed and enabled by U.S. Pat. No. 8,063,434 would be potentially anticipated.

9. U.S. Provisional Patent Application No. 60/940,160

   • Full Citation: U.S. Provisional Patent Application No. 60/940,160, filed May 25, 2007.
   • Publication/Filing Date: May 25, 2007 (filed).
   • Brief Description: This is the earliest priority document in the chain, providing the priority date for the entire patent family. It would contain the initial disclosure of the invention.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Any claims in US11456365B2 that are fully disclosed and enabled in U.S. Provisional Patent Application No. 60/940,160 are potentially anticipated by this provisional application. This is particularly crucial for determining the effective filing date and assessing novelty.

The above-listed documents are directly referenced within US11456365B2's "CROSS-REFERENCE TO RELATED APPLICATIONS" section, making them the most pertinent prior art for a Section 102 anticipation analysis. To definitively state which specific claims are anticipated, one would need to perform a detailed claim-by-claim comparison with the full text of each cited prior art document.

Obviousness Analysis under 35 U.S.C. § 103 for US11456365

The present invention, US11456365, describes a memory transistor featuring a multi-layer charge storage layer and a high work function gate electrode, designed to enhance data retention and improve programming time and efficiency. A key aspect of the multi-layer charge trapping layer is its structure, which includes an oxygen-rich first nitride layer, an oxygen-lean second nitride layer, and an oxide anti-tunneling layer positioned between them, forming an ONONO (Oxide-Nitride-Oxide-Nitride-Oxide) stack (Abstract, Summary,,). The patent also emphasizes the use of a high work function gate electrode, often comprising doped polysilicon, compatible with CMOS processes and suitable for System-On-Chip (SOC) applications where logic and memory transistors are integrated on a common substrate (,-). Furthermore, the invention details applications in various device architectures, including planar, FinFET, and nanowire configurations (,-).

A person having ordinary skill in the art (PHOSITA) in semiconductor device fabrication and non-volatile memory would be motivated to address known problems in flash memory technology, specifically improving data retention, programming/erase speed, and scalability, as highlighted in the background of US11456365 (-). These problems include rapid voltage window collapse in silicon-rich nitride layers (FIG. 1A) and reduced initial program-erase windows in high-quality nitride layers (FIG. 1B).

For this obviousness analysis, we consider the priority date of US11456365, which is May 25, 2007. The patent itself explicitly references U.S. Patent No. 8,063,434 (US8063434B1), which issued from U.S. patent application Ser. No. 12/152,518 filed May 13, 2008, and claims benefit of the same provisional application (60/940,160, filed May 25, 2007). Therefore, US8063434B1 represents a highly relevant prior art reference, likely disclosing many foundational aspects of the claimed invention.

Combination 1: US8063434B1 in view of general knowledge regarding multi-layer charge traps and high-K gate dielectrics.

Primary Reference: US8063434B1
The abstract of US8063434B1 discloses a non-volatile memory transistor with a multi-layer charge trapping dielectric layer and a high work function gate electrode, specifically mentioning a polysilicon channel, a tunneling dielectric layer, a multi-layer charge trapping region, a blocking dielectric layer, and a high work function gate electrode. It states that the multi-layer charge trapping region includes at least one oxygen-rich first nitride layer and one oxygen-lean second nitride layer. It also notes that the high work function gate electrode "is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 eV to about 5.3 eV".

Identified Differences from US11456365:
Based on the abstract of US8063434B1, the main feature not explicitly mentioned is the oxide anti-tunneling layer located between the oxygen-rich first nitride layer and the oxygen-lean second nitride layer within the multi-layer charge trapping region, which creates the distinctive ONONO stack within the gate dielectric. While US8063434B1 mentions the two types of nitride layers, the specific interposition of an oxide anti-tunneling layer is a distinguishing feature of US11456365.

Motivation for Combination:
A PHOSITA would have been motivated to introduce an anti-tunneling layer between charge trapping layers to further improve data retention and reduce leakage, which were known challenges in non-volatile memory at the time. The background of US11456365 explicitly states that "the charge stored or trapped in the charge trapping layer decreases over time due to leakage current through the insulating layers". The patent itself describes the anti-tunneling layer as "substantially reduc[ing] the probability of electron charge that accumulates at the boundaries of the oxygen-lean second nitride layer... from tunneling into the first nitride layer..., resulting in lower leakage current" (). The use of oxide layers within ONO stacks for blocking or tunneling functions was well-established in the art. Therefore, extending this concept to isolate distinct charge-trapping nitride layers to prevent charge leakage and enhance retention would have been a logical and predictable design choice for a PHOSITA.

The use of high work function gate electrodes is explicitly present in US8063434B1 and in US11456365. Similarly, the use of oxygen-rich and oxygen-lean nitride layers in combination in a charge trapping layer is also disclosed in US8063434B1 and is a core part of US11456365. The novelty primarily resides in the specific ONONO dielectric stack configuration and the advantages derived from it.

Combination 2: US8063434B1 in view of general knowledge regarding multi-layer dielectrics for charge trapping memory.

Primary Reference: US8063434B1
As described above, US8063434B1 discloses a non-volatile memory transistor with a multi-layer charge trapping dielectric layer (oxygen-rich and oxygen-lean nitrides) and a high work function gate electrode.

Secondary Reference/General Knowledge:
Prior to the priority date of US11456365, the field of non-volatile memory extensively explored various multi-layer dielectric stacks beyond simple ONO structures to optimize charge trapping and retention. For instance, modified ONO structures, including those with additional layers or variations in composition, were known to address issues like charge loss. The use of an oxide layer as an anti-tunneling barrier or a blocking layer to prevent charge leakage in memory devices was a common technique.
US11456365 itself discusses conventional memory transistors and their limitations related to data retention, implying that efforts to improve insulating layers were ongoing (-).

Motivation for Combination:
Given US8063434B1's disclosure of a multi-layer charge trapping region comprising both oxygen-rich and oxygen-lean nitride layers, a PHOSITA would be motivated to further optimize the charge retention characteristics of such a structure. Knowing that leakage through insulating layers is a primary cause of data loss (), and that oxide layers are effective barriers to charge transport, it would have been obvious to insert an oxide anti-tunneling layer between the distinct nitride layers described in US8063434B1. This would serve to isolate the charge stored in one nitride layer from leaking into the other or out of the trapping region, thereby improving overall data retention. The choice of an oxide layer for this purpose would be a predictable application of known dielectric engineering principles to solve the persistent problem of charge leakage in charge-trap memories. The patent explicitly notes that the anti-tunneling layer "substantially reduces the probability of electron charge that accumulates at the boundaries... from tunneling... resulting in lower leakage current" (), which directly addresses the problem of data retention due to leakage.

Conclusion

Based on this analysis, the claims of US11456365, particularly those directed to the specific ONONO stack within the charge trapping layer, would likely have been obvious to a PHOSITA in light of the disclosures of US8063434B1 combined with the general knowledge in the field regarding multi-layer dielectric engineering for improving charge retention and reducing leakage in non-volatile memory devices. The motivation would stem from the recognized need to overcome limitations in data retention and leakage currents in existing charge-trap memory architectures.