US 8063434

I'll search for authoritative information on this patent, including any 2026 litigation activity.

Let me check specifically for 2026 appellate or litigation activity on this patent.

Let me check whether this patent has been asserted in the 2025–2026 IpValue/Longitude campaigns.

US 8,063,434 B1 — Analyst Summary

Bottom line up front: I could retrieve and verify the patent's bibliographic and claim data from the authoritative full text (Google Patents mirror of the USPTO record). I found no CAFC 2026 docket entry, and no 2026 appellate activity of any kind, naming U.S. Patent No. 8,063,434. My searches for 2026 Federal Circuit coverage returned unrelated patents. I cannot rule out a very recent or sealed proceeding, but as of this search there is no public 2026 CAFC docket for this patent number.

1. Bibliographic data (verified)

Note on the title/claim mismatch: the title and the specification emphasize a high work function gate electrode on the memory transistor, but granted independent claim 1 does not itself recite a high work function gate electrode for the memory transistor — that limitation appears only in dependent claim 2. The title is therefore broader than the independent claim.

2. Abstract (verbatim)

An embodiment of a semiconductor device includes a non-volatile memory transistor including an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate, the ONO dielectric stack comprising a multilayer charge storage layer including a silicon-rich, oxygen-lean top silicon oxynitride layer and a silicon-rich, oxygen-rich bottom silicon oxynitride layer, and a metal oxide semiconductor (MOS) logic transistor including a gate oxide and a high work function gate electrode.

3. Plain-language overview of the independent claim

Claim 1 (the only independent claim) is a device claim covering an integrated device containing two transistors on a common substrate:

1. A non-volatile memory transistor having an oxide-nitride-oxide (ONO) dielectric stack on a semiconductor substrate surface. The key structural point is that the stack's charge-storage layer is a two-layer (multi-layer) silicon oxynitride region:
   • a top silicon oxynitride layer that is silicon-rich and oxygen-lean (the charge-trapping layer), and
   • a bottom silicon oxynitride layer that is silicon-rich and oxygen-rich (described in the specification as substantially trap-free).
2. A MOS logic transistor on the same device, having a gate oxide and a high work function gate electrode.

In plain terms: one chip, two transistor types — a SONOS-style charge-trap memory cell with a graded, two-layer oxynitride storage region, plus ordinary logic — where the logic gate electrode is made of a high work function material. The specification's stated purposes are (a) improved data retention/programming efficiency in the memory cell, and (b) CMOS-process compatibility so memory and logic can be built together for embedded memory / System-On-Chip. "High work function" is defined in the specification as increasing the minimum energy needed to remove an electron from the gate electrode, and is realized in the disclosed embodiment as P+ (boron or BF₂) doped polysilicon doped to about 4.8–5.3 eV.

The dependent claims add, in substance:

• Claim 2: the memory transistor also has a high work function gate electrode over the ONO stack.
• Claims 3 and 9: the top oxynitride is trap-rich and the bottom oxynitride is substantially trap-free.
• Claims 4–7: dopant-type options for the logic and/or memory gate electrodes.
• Claim 8: both the memory and logic gate electrodes are formed from a single patterned doped polysilicon layer (this is the manufacturing-efficiency point of the invention).

Note on literal claim wording (not auto-corrected): the granted claims contain apparent typographical inconsistencies that I am reporting as written, not as I would expect them to read. For example, claim 5 recites a "P+ doped polysilicon layer to form a P-type (NMOS) logic transistor," while claim 6 recites an "N+ doped polysilicon layer to form an P-type (PMOS) SONOS memory transistor and a N-type (NMOS) logic transistor." The specification's disclosure is that a P+ doped polysilicon layer forms an NMOS SONOS memory transistor and a PMOS logic transistor. Anyone relying on claims 4–7 should read the actual granted claim text rather than the specification's summary.

4. Litigation / CAFC search results

• CAFC 2026 dockets: No results. My searches targeted at Federal Circuit 2026 activity turned up no docket, opinion, or summary referencing 8,063,434. The patent is a 2011-issued semiconductor/ONO-stack patent, not an § 101 "abstract idea" case, so it would be unlikely to surface in the 2026 eligibility-driven CAFC reporting wave — consistent with finding nothing.
• Asserted in the 2025 campaign: Longitude Flash Memory Solutions Ltd. (with IPValue Management, Inc.) sued Western Digital Corp. / SanDisk in C.D. Cal., Case No. 8:25-cv-00119, filed January 22, 2025, asserting five patents "apparently received from Cypress Semiconductor." I could not confirm from the sources retrieved whether 8,063,434 is one of the five asserted patents — the public reporting does not identify them. Treat that as an open question. (Sources: RPX litigation news https://litigation.rpxcorp.com/news/84773-ipvalue-sues-western-digital-over-former-cypress-semiconductor-patents ; docket https://dockets.justia.com/docket/california/cacdce/8:2025cv00119/[954920](/patent/954920) )
• Related-but-different prior IPRs: The 2015 Apple/Longitude IPR cluster (IPR2015-01910, -01925, -01934) targeted 6,510,488, 7,224,607, and 8,316,177, not 8,063,434. Do not conflate these.
• Forward citations: 8,063,434 is cited as prior art in EP 2 725 607 A3 (Nov. 2011 reference, cited for the poly-gate/ONO structure at col. 5–9, Figs. 2A–2D, 3), among other references.

5. Explicit uncertainty statements

• I do not have direct USPTO PatentCenter/PAIR access in this session; bibliographic data above is drawn from the authoritative full-text record fetched from Google Patents (which mirrors USPTO data) plus web search. The adjusted expiration of 2029-09-16 and "Active" status are as listed and are not a legal conclusion.
• I found no authoritative 2026 CAFC docket for this patent. Absence of a search hit is not affirmative proof that no such proceeding exists.
• The "Related Child Applications" table on the Google Patents page contains an obvious data artifact — it lists "US13/593,466 … System and method for providing an alumni engagement platform and game" as a continuation. That appears to be a database error unrelated to this patent; I have not treated it as real.
• I could not verify whether 8,063,434 is among the five patents asserted in IPValue/Longitude v. Western Digital (8:25-cv-00119).

Family context (for completeness): this patent sits in a large Cypress/Longitude continuation family sharing the 2007-05-25 priority date, including US 8,859,374; 9,093,318; 9,306,025; 9,502,543; 9,929,240; 10,446,656; 10,312,336; 10,903,325; 11,056,565; 11,456,365; 11,721,733; 12,009,401; and pending publication US 2024/0332385 A1. The related US 8,093,128 ("Integration of non-volatile charge trap memory devices and logic CMOS devices") is the closest sibling on the memory-plus-logic integration theme.