US 8001434

US Patent 8,001,434 B1 — Search Results & Summary

Verification notes on searches

I searched the USPTO-derived databases (uspto.report, FreePatentsOnline, Google Patents, Unified Patents) and the CAFC/PTAB/ITC litigation record for patent number 8,001,434 only. All results below are for that exact number (often cited as the "'434 patent"). I found no CAFC docket entries in 2026 specific to patent 8,001,434 — the 2026 CAFC Netlist decisions reported (e.g., involving patents 10,949,339; 10,489,314; 10,268,608; 10,217,523) concern other Netlist patent numbers. The most recent CAFC activity touching 8,001,434 that I could confirm is a Rule 36 summary affirmance in December 2019 (see litigation note below).

Core bibliographic data (high confidence; multiple independent sources agree)

Abstract (as issued)

"A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports."

Plain-language overview of the independent claims

The patent has three independent claims (1, 20, 29) and 32 dependent claims. Caveat on claim text: the patent went through IPR proceedings, and the version of the claims visible on uspto.report (which references a "PTAB Trial Certificate" image) appears to be an amended/post-IPR set, in which each independent claim adds language that the module includes "a circuit comprising" the control and data modules and "wherein the circuit is configured to test the memory devices" using the generated signals. The originally granted B1 claims (as reflected in the Google Patents text) are similar but without that "circuit"-limitation framing. I flag this because the operative claim set may differ from the as-issued set; I describe the substance below, which is consistent across both versions.

• Claim 1 (apparatus – module with multiple independent data handlers): A self-testing memory module having (a) a PCB couplable to a system memory controller, (b) memory devices on the PCB each with data/address/control ports, and (c) a circuit containing a control module that generates the address and control signals used for testing, plus a data module made of multiple data handlers. Each data handler works independently of the others, is coupled to its own set of data ports of one or more memory devices, and generates the write data for those ports. The circuit tests the memory devices using the control module's address/control signals and the data handlers' generated data.

• Claim 20 (apparatus – module with at least one data handler generating cyclic data): Similar module structure, but the data module has at least one data handler (rather than requiring a plurality) that is coupled to corresponding data ports and generates cyclic data (a repeating/deterministic test pattern) for writing to those ports; the circuit tests the devices using the control module's signals and the cyclic data.

• Claim 29 (method of self-testing): A method comprising providing such a self-testing module (PCB + memory devices + circuit with control module and multiple independently operable data handlers), then (i) generating address and control signals with the control module, (ii) generating write data with each data handler for its corresponding data ports, and (iii) using those signals and data to test the memory devices.

Representative dependent-claim concepts (not independent): physically separate IC packages for the data handlers placed proximate to their memory devices (claims 2–6); read-back verification against expected data without storing a copy of the written data, e.g., by calculating comparison data from cyclic patterns or current read address (claims 7–12, 21–25); storing failed data in the data module and failed addresses in the control module (claims 13, 26); switches/mux-demuxes that select between system-controller data and self-test data (claims 14–16, 35); and DRAM-controller-based selection of address/control sources (claims 17–19).

Legal-status / litigation context (moderate-to-high confidence from public sources; not needed for claim construction)

• The '434 patent covers Netlist self-test technologies for memory modules (used in LRDIMMs, SSDs, storage-class memory) and is part of a family that includes US 8,359,501, 8,689,064, 8,359,501, 10,217,523, and others.
• District court / ITC: Asserted against Smart Modular/Diablo (N.D. Cal. 4:13-cv-05889 and related DJ actions 4:13-cv-03901, 4:13-cv-03916), SK hynix (C.D. Cal. 8:16-cv-01605), and in ITC Inv. No. 337-TA-1023 (SK hynix; asserted claims 2, 3, 5–7 of the '434 patent).
• PTAB IPRs: IPR2014-00970 and IPR2014-01372 reached Final Written Decisions; IPR2014-01373 was not instituted. Netlist announced (Nov. 2017) that the CAFC affirmed PTAB decisions confirming validity of certain claims against SanDisk/Smart Modular challenges.
• Later adverse outcome: Per Netlist's Dec. 13, 2019 press release, the CAFC affirmed via Rule 36 the PTAB's invalidity decisions with respect to US 8,869,064, 8,001,434, and 8,359,501 in the SK hynix/337-TA-1023-related appeal; the ITC final-determination appeal was deemed moot.
• Current status: Google Patents lists the patent as "Expired – Fee Related" (maintenance fees not paid), with a nominal adjusted-expiration date of 2029-08-22 (base 20-year term from Apr. 13, 2009, extended by 131 days). Because of the fee lapse and the PTAB/CAFC invalidity rulings, the patent should not be treated as currently enforceable without independent verification.

Residual uncertainty

• I did not pull the official USPTO assignment/PAIR record directly, so the precise current chain of title (Netlist → DBD Credit Funding LLC security interest → back to Netlist, per Google Patents assignment entries) is reported from secondary sources only.
• The exact set of claims surviving (or invalidated by) the various IPRs, and the precise wording of the currently certified claims, should be verified against the USPTO PTAB trial certificate and the IPR2017-00561 / IPR2014-00970 / IPR2014-01372 final written decisions; the claim text quoted above is from a secondary USPTO mirror and matches the 35-claim structure but may reflect post-grant amendments.

Based on my searches (including the litigation data embedded in the Google Patents record for US8001434B1, the Stanford NPE Litigation Database, RPX, CourtListener/Justia, and Netlist press releases/SEC filings), here is the known litigation landscape for US Patent No. 8,001,434 ("Memory Board with Self-Testing Capability," Netlist Inc.). Note: in most cases '434 was asserted/challenged together with other Netlist patents (the "Five Netlist Patents" and later a "seven-patent" group), so the case descriptions reflect that the '434 patent was one of multiple patents at issue.

District Court / ITC Cases

1. Diablo Technologies, Inc. v. Netlist, Inc.

   • Plaintiff: Diablo Technologies, Inc. (declaratory-judgment plaintiff)
   • Defendant: Netlist, Inc.
   • Jurisdiction: N.D. Cal. (Judge Yvonne Gonzalez Rogers)
   • Case No.: 4:13-cv-03901-YGR
   • Filed: Aug. 23, 2013
   • Subject: DJ action seeking invalidity/non-infringement of the "Five Netlist Patents," which included U.S. Patent No. 8,001,434 (regarding the ULLtraDIMM product).
   • Status: Netlist's motions to dismiss/transfer were denied Oct. 10, 2013. Final disposition not confirmed in my sources; the patent claims in this dispute were later consolidated/coordinated with the related N.D. Cal. actions below.

2. Smart Modular Technologies, Inc. v. Netlist, Inc.

   • Plaintiff: Smart Modular Technologies, Inc. (DJ plaintiff)
   • Defendant: Netlist, Inc.
   • Jurisdiction: N.D. Cal.
   • Case No.: 4:13-cv-03916 (also appears in some listings as 3:13-cv-03916, same case)
   • Filed: Aug. 23, 2013
   • Subject: DJ action seeking declarations of invalidity/non-infringement of the same Five Netlist Patents, including '434.
   • Status: Dismissed without prejudice by stipulation, order entered Feb. 12, 2014.

3. Netlist, Inc. v. Smart Modular Technologies, Inc., et al.

   • Plaintiff: Netlist, Inc.
   • Defendants: Smart Modular Technologies, Inc., Smart Storage Systems, Inc., Smart Worldwide Holdings, Inc., Diablo Technologies, Inc.
   • Jurisdiction: C.D. Cal., then transferred to N.D. Cal.
   • Case Nos.: 8:13-cv-00996 (C.D. Cal., amended complaint adding patent claims filed Aug. 23, 2013) → transferred to N.D. Cal. as 4:13-cv-05889
   • Filed: Original complaint July 1, 2013; First Amended Complaint adding infringement of the Five Netlist Patents (incl. '434) Aug. 23, 2013
   • Status: Dismissed without prejudice by stipulation, orders entered Feb. 12, 2014 (the parties then pursued the IPRs below).

4. Netlist, Inc. v. Diablo Technologies, Inc., et al.

   • Plaintiff: Netlist, Inc.
   • Defendants: Diablo Technologies, Inc., Smart Modular Technologies, Inc., Smart Storage Systems, Inc., Smart Worldwide Holdings, Inc.
   • Jurisdiction: N.D. Cal. (Judge Yvonne Gonzalez Rogers)
   • Case No.: 4:13-cv-05962-YGR
   • Filed: Dec. 26, 2013
   • Subject: Netlist's suit (later a seven-patent case) over the ULLtraDIMM product; '434 and '501 were identified as part of this N.D. Cal. suit. Included trade-secret/contract claims as well as patent claims.
   • Status: Patent claims were stayed pending IPR (stay granted Apr. 9, 2015). The non-patent claims went to jury trial in March 2015 (verdict largely for Diablo on contract/trade-secret counts; for Netlist on trademark/false advertising). The Federal Circuit affirmed the district court in the related appeal (No. 16-1011, judgment July 11, 2016). Overall case status: closed/resolved; the '434 claims were ultimately governed by the PTAB outcomes below.

5. Netlist, Inc. v. SK hynix Inc., et al.

   • Plaintiff: Netlist, Inc.
   • Defendants: SK hynix Inc., SK hynix America Inc. (et al.)
   • Jurisdiction: C.D. Cal.
   • Case No.: 8:16-cv-01605
   • Filed: 2016 (per the litigation data on the '434 patent record)
   • Subject: Patent infringement involving Netlist memory-module patents; the Stanford NPE database lists this case as one involving '434.
   • Status: Litigation proceeded in C.D. Cal. (jury verdicts on some Netlist patents followed in 2020). I could not confirm from my sources the specific current disposition as to the '434 patent claims; treat as needing docket verification.

6. ITC Investigation No. 337-TA-1023

   • Google Patents' litigation data links ITC Inv. No. 337-TA-1023 to this patent. This was an ITC investigation involving Netlist and memory-module components (I was unable to verify the precise parties/respondents and the specific '434 assertions from my available sources — verify against the ITC docket before relying on it).

PTAB Inter Partes Reviews (administrative trials)

1. SanDisk Corporation v. Netlist, Inc. — IPR2014-00970 (IPR of US8001434B1)

   • Petitioner: SanDisk Corporation
   • Patent Owner: Netlist, Inc.
   • Filed: June 18, 2014
   • Institution: Dec. 16, 2014
   • Outcome: Final Written Decision Dec. 14, 2015 — PTAB confirmed validity of the challenged claims at issue (per Netlist's March 2016 press release, claims 2, 5, 6, 7–13, 17, 18, 26, and 35 of the '434 were confirmed).
   • Appeal: Netlist, Inc. v. SanDisk LLC, Fed. Cir. No. 16-2274 (filed June 30, 2016), originating from IPR2014-00970/-00971. Outcome of the appeal not confirmed in my sources.

2. Smart Modular Technologies, Inc. v. Netlist, Inc. — IPR2014-01372

   • Petitioner: Smart Modular Technologies, Inc.
   • Patent Owner: Netlist, Inc.
   • Filed: 2014
   • Outcome: Instituted; Final Written Decision (issued ~March 2016) confirming all claims under review in the '434 (per Netlist's March 15, 2016 release, Smart Modular "failed to invalidate a single claim").

3. Smart Modular Technologies, Inc. v. Netlist, Inc. — IPR2014-01373

   • Petitioner: Smart Modular Technologies, Inc.
   • Patent Owner: Netlist, Inc.
   • Outcome: Not instituted (denied at the institution stage).

4. IPR2017-00561 (of US8001434B1)

   • Google Patents' litigation data lists this as an IPR of the '434 with a Final Written Decision. The petitioner is not identified in my available sources (likely a memory-maker involved in the C.D. Cal./ITC campaigns, but do not rely on that inference — check the PTAB docket). Outcome: Final Written Decision issued (details not confirmed).

Federal Circuit Appeals

Google Patents' litigation data also flags the following CAFC docket numbers in connection with this patent: 16-2666, 18-1676, and 18-2357. These are Federal Circuit appeals arising from the Netlist IPR/ITC/district-court campaigns in which the '434 patent was involved (the E.D. Tex. Netlist/Samsung-Micron claim-construction record lists these CAFC numbers among Netlist's prior Federal Circuit matters). I could not confirm from my available sources the precise underlying judgment and parties for each of these three appeal numbers, so verify them on PACER/CAFC before citing them.

Caveats

• The '434 patent is expired (fee-related expiration noted on the record; adjusted expiration listed ~Aug. 22, 2029, though the status shows "Expired - Fee Related").
• Several case dispositions (notably the final status of 4:13-cv-03901, the exact role of '434 in 8:16-cv-01605 and ITC 337-TA-1023, and the petitioners/outcomes in IPR2017-00561 and CAFC Nos. 16-2666, 18-1676, 18-2357) could not be fully confirmed within my search limits. I would recommend docket lookups on PACER, the PTAB API, and the ITC EDIS system to pin those down before any formal use.

Key sources consulted: the Google Patents record for US8001434B1 (litigation links), Stanford NPE Litigation Database (npe.law.stanford.edu/patent/8001434), RPX litigation pages for IPR2014-00970, Justia/CourtListener records for 4:13-cv-03901 and 4:13-cv-05962 (and CAFC 16-1011), Netlist press releases (StorageNewsletter, Mar. 15 & 22, 2016) and Netlist's Q3-2015 SEC filing, and the IPR2014-01375 petition declaration describing the 2013–2014 N.D. Cal./C.D. Cal. filings and dismissals.

Proceedings overview

Four inter partes review proceedings against US 8,001,434 are confirmed on the public record (IPR2014-00970, IPR2014-01372, IPR2014-01373, IPR2017-00561). Note: the "PTAB proceedings on file" block derived from the USPTO Open Data Portal ingest shows zero AIA proceedings — that ingest is stale/incomplete and is affirmatively contradicted by the PTAB dockets, CAFC judgments, and PTAB decision copies retrieved below; treat the web-verified list as authoritative. Breakdown: 0 active; claims invalidated in IPR2014-00970 (independent claim 1, affirmed by the Federal Circuit; plus a block of additional claims per the FWD) and IPR2017-00561 (claims 2–7); claims sustained in IPR2014-01372 (no claim found unpatentable); institution denied in IPR2014-01373.

Bottom-line defensive posture: This patent is a spent force. Claims 1–7 — including independent claim 1 and its earliest dependents — have been finally adjudicated unpatentable on Averbuj-based grounds, with Federal Circuit affirmances in both 2017 (IPR2014-00970) and 2019 (IPR2017-00561), and the patent is additionally expired for non-payment of maintenance fees ("Expired – Fee Related" on the record). If a demand letter cites claims 1–7, the asserted claims are dead and the demand is sanction-bait; any surviving claim set (at most a subset of claims 8–35, subject to the certificate caveat below) must be verified against the PTAB trial certificate before it can support a theory.

IPR2014-00970 — SanDisk Corporation v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2014-06-18
• Status: Final Written Decision issued 2015-12-14 (Paper 32); Federal Circuit affirmed; mandate issued 2017-12-21 — closed
• Judge panel: Not confirmed from the sources retrieved (panel names for the '970 FWD were not legible in my copies); do not cite a panel without docket verification
• Petition grounds: SanDisk challenged claims 1–35; trial was instituted on claims 1, 2, 5–15, and 17–35 (per the IPR2014-01372 institution decision, which expressly recounts the '970 institution scope). The operative prior art was Averbuj (US 2005/0257109 A1, which matured into US 7,392,442 B2) under § 102 anticipation and § 103 obviousness, including obviousness over Averbuj in view of Tsern (US 2007/0070669 A1)
• Institution decision: Instituted 2014-12-16 (Paper 12)
• Final Written Decision: Issued 2015-12-14. The later IPR2017-00561 FWD confirms the critical holding: in the '970 IPR, "claim 1 was held unpatentable as anticipated by Averbuj in a final written decision," that decision "was appealed to [the] Federal Circuit, the decision was affirmed, and the mandate issued on December 21, 2017." Per Netlist's own March 2016 disclosure, the claims the PTAB confirmed in the '970 FWD were claims 2, 5, 6, 7–13, 17, 18, 26 and 35 of the '434 — which, read against the instituted set, means the FWD found claims 1, 14, 15, 19–25 and 27–34 unpatentable (a status summary filed in the parallel N.D. Cal. litigation lists exactly that claim block as "unpatentable"). This block includes independent claims 20 (cyclic-data apparatus) and 29 (method). Independent claim 1 was the one claim the Board and CAFC record treat as "finally adjudicated as unpatentable."
• Settlement / termination: None — litigated to FWD
• Appeal: Netlist, Inc. v. SanDisk LLC, Fed. Cir. Nos. 2016-2274, -2275, -2338, -2339 (Netlist appellant; SanDisk cross-appellant). Affirmed per curiam 2017-11-14 (Prost, C.J., Wallach and ____); mandate 2017-12-21. Judgment: https://www.cetient.com/case/netlist-inc-v-sandisk-llc-[4442952](/patent/4442952)
• Defensive value: Independent claim 1 is dead, confirmed on appeal — any infringement theory built on claim 1 (or, subject to certificate verification, on claims 14–15, 19–25, 27–34 as found unpatentable here) has no viable validity footing. Note the conflict with IPR2014-01372 below on overlapping claims — the certificate of correction is the tiebreaker and should be pulled before formal use.

IPR2017-00561 — SK hynix Inc., SK hynix America Inc., and SK hynix memory solutions Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2017-01-05
• Status: Final Written Decision issued 2018-07-05 (Paper 36); Federal Circuit affirmed 2019-12-12 — closed
• Judge panel: Bryan F. Moore, Matthew R. Clements, and a third APJ whose surname is truncated in the retrieved copy of the FWD ("SHEILA F. ____") — verify the full name on the USPTO decision
• Petition grounds: Challenged claims 1–7 as (1) anticipated under § 102 by Averbuj (US 2005/0257109 A1); (2) obvious under § 103 over Averbuj; and (3) obvious under § 103 over Averbuj in view of Tsern (US 2007/0070669 A1). The petition expressly relied on the Board's prior Averbuj analysis in IPR2014-00970 (Paper 32) and IPR2014-00971 (Paper 37)
• Institution decision: Instituted 2017-07-07 (Paper 7) — initially not on all grounds; after the Supreme Court's SAS Institute decision (2018-04-24), the Board "modified our Institution Decision to institute trial on all of the challenged claims and all of the grounds presented in the Petition" (FWD at 3)
• Final Written Decision: Issued 2018-07-05. The panel held Petitioner "shown by a preponderance of the evidence that claims 2–7 are unpatentable," and separately terminated the trial as to claim 1 under 37 C.F.R. § 42.72 based on collateral estoppel, because claim 1 "has been finally adjudicated as unpatentable" in the affirmed IPR2014-00970 FWD. The FWD's obviousness analysis found, e.g., that placing Averbuj's data handlers proximate to their associated memory devices was "the arrangement of old elements ... yielding no more than one would expect," and that Tsern's self-test/verification circuitry supplied the read-compare "verification element" limitation of claim 7. FWD PDF: https://www.docketalarm.com/cases/PTAB/IPR2020-01421/SK_hynix_Inc._v._Netlist_Inc/docs/08-21-2020-Petitioner/Exhibit-1025-Final_Written_Decision,_SK_hynix_Inc_v_Netlist,_Inc,_Paper_No_36,_IPR2017_00561_July_5,_2018.pdf
• Settlement / termination: None — litigated to FWD (trial terminated only as to claim 1 on collateral estoppel)
• Appeal: Netlist, Inc. v. SK hynix Inc., Fed. Cir. Nos. 2018-2357, -2358 (Netlist appellant; SK hynix appellees). Affirmed per curiam 2019-12-12 (Prost, C.J., Newman and ____). Judgment: https://www.courtlistener.com/opinion/[4686319](/patent/4686319)/netlist-inc-v-sk-hynix-inc/
• Defensive value: This is the cleanest kill. Claims 2–7 are canceled and the affirmance is now final — dependent-claim theories tied to claim 1's structure (physically separate/proximate handlers, verification without a stored copy, etc.) cannot support an infringement case today. SanDisk/SK hynix and privies are estopped from re-running Averbuj/Tsern; a new defendant can and should use those same references.

IPR2014-01372 — Smart Modular Technologies, Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2014-08-23
• Status: Final Written Decision issued 2016-03-09 (Paper 45) — no claim found unpatentable; Federal Circuit affirmed; closed
• Judge panel: Linda M. Gaudette (author of the FWD), Bryan F. Moore, Peter P. Chen (per Patexia and the Akin Gump report of the FWD: "[Gaudette (opinion), Moore, Chen]")
• Petition grounds: Petition challenged all 35 claims; grounds were anticipation/obviousness over Averbuj (US 7,392,442 B2), Best (US 8,233,303), Pandey (US 6,934,205), and Rajan (US 7,379,316) with the Bagherzadeh declaration
• Institution decision: Instituted 2015-03-10 (Patexia date) on claims 1–4, 14–20, 27, and 29 only (Institution Decision, Paper ~12)
• Final Written Decision: Issued 2016-03-09. The panel found Smart Modular "failed to show a preponderance of evidence that any claim was unpatentable" — i.e., all instituted claims (1–4, 14–20, 27, 29) were sustained. Key construction point: the Board changed its institution-stage construction of "generate" from "produce or cause" to "produce," and under that construction the cited references did not disclose every claim element. This FWD conflicts with IPR2014-00970's earlier finding that claims 1, 14, 15, 19, 20, 27 and 29 were unpatentable — the IPR2017-00561 FWD expressly notes '1372 "held claims 1-4 ... not unpatentable as anticipated by Averbuj (under a different theory of anticipation than the '970 IPR)" and that the '1372 decision "was not appealed." The certificate of correction, not either FWD alone, controls the operative claim set
• Settlement / termination: None — litigated to FWD
• Appeal: Smart Modular Technologies, Inc. v. Netlist, Inc., Fed. Cir. Nos. 2016-2666, -2667 (Smart Modular appellant). Affirmed per curiam 2017-11-14. Judgment: https://www.cetient.com/case/smart-modular-technologies-v-netlist-inc-[4442951](/patent/4442951)
• Defensive value: Netlist's one clean appellate win on this patent — but it is of limited comfort to a defendant today because the same claims (1, 14, 15, 19, 20, 27, 29) were independently found unpatentable in the '970 IPR, and claims 1–7 were later finally canceled. Do not over-read this FWD as "the patent survived": it shows only that this petitioner's art and this panel's "produce"-only construction failed.

IPR2014-01373 — Smart Modular Technologies, Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2014 (second Smart Modular petition against the '434, filed in the same August 2014 wave as IPR2014-01372)
• Status: Institution denied 2015-03-13 (Paper 16) — closed
• Judge panel: Not confirmed from the sources retrieved
• Petition grounds: Challenges to the '434 (per the IPR2017-00561 FWD: "institution was denied as to all challenges on the merits ... Neither Averbuj nor Tsern was asserted in the '1373 IPR"); Netlist's March 2016 release confirms one Smart Modular petition per patent was denied at the outset
• Institution decision: Denied 2015-03-13 — no trial; the panel found the petition failed to show a reasonable likelihood of prevailing on any challenged claim
• Final Written Decision: None (never instituted)
• Settlement / termination: N/A
• Appeal: None
• Defensive value: Evidentiary only — shows the Board did not consider Smart Modular's alternative grounds meritorious, which slightly strengthens the patent's residue, but it has no preclusive effect against anyone and does not resurrect claims 1–7.

Strategic summary

Canceled vs. sustained vs. untested. As of the final affirmances, the only claims the Board expressly and finally disposed of in the '434's own IPRs are: claim 1 — canceled via IPR2014-00970 (anticipation by Averbuj, affirmed, mandate 2017-12-21) and formally terminated by collateral estoppel in IPR2017-00561; claims 2–7 — canceled via IPR2017-00561 (obviousness over Averbuj alone and/or Averbuj + Tsern, affirmed 2019-12-12). The '970 FWD additionally found claims 14–15, 19–25, and 27–34 unpatentable (a block that includes independent claims 20 and 29), while IPR2014-01372 later found the overlapping claims 1–4, 14–20, 27, and 29 not unpatentable under different art/construction — an unresolved administrative conflict that only the PTAB trial certificate can resolve. Claims 8–13, 16–18, 26, and 35 were confirmed in at least one IPR and were not later canceled in the proceedings reviewed here; claims 3, 4, and 16 were never instituted in the SanDisk IPR and were sustained in the Smart Modular IPR. Action item: pull the USPTO certificate(s) for IPR2014-00970 and IPR2017-00561 to lock down the exact surviving claim numbers before writing any invalidity contention.

Estoppel landscape. Under 35 U.S.C. § 315(e)(2), SanDisk (now SanDisk LLC), Smart Modular, SK hynix, and their privies are barred from re-raising in district court or ITC any ground they raised or reasonably could have raised in these IPRs — including the winning Averbuj and Averbuj + Tsern combinations. That estoppel does not bind a new defendant. If you are a new party facing assertion, Averbuj (US 7,392,442 B2 / US 2005/0257109 A1) and Tsern (US 2007/0070669 A1) remain fully available to you, as do the '1372 references (Best US 8,233,303; Pandey US 6,934,205; Rajan US 7,379,316) and the examiner-cited distributed-BIST cluster (e.g., US 7,184,915 Hansquine). Since the patent is expired for unpaid maintenance fees, an expiration defense under 35 U.S.C. § 286/§ 154 is even simpler than a validity attack for any post-lapse conduct.

Pattern signals. Three different petitioners (SanDisk, Smart Modular, SK hynix) filed four IPRs against this one patent, all stemming from the same memory-industry dispute web — the 2014 SanDisk/Diablo/Smart Modular wave (17 IPRs against seven Netlist patents) and SK hynix's 2017 follow-on that reused the Board's own Averbuj analysis. Netlist defended aggressively and won the '1372 and '1373 rounds outright, but lost claim 1 and then claims 2–7 on the same core reference across two proceedings — a textbook example of a petitioner-side "second bite" strategy succeeding once the first petitioner had established the Averbuj mapping. No defensive aggregator (Unified Patents, RPX) appears in the petitioner chain; these were all operating-company competitors. The absence of any active PTAB proceeding today, combined with the fee lapse and the two affirmances, means the patent's remaining value is marginal at best.

Recommended next steps

1. Confirm the certified claim set. Download the PTAB trial certificates from USPTO PTAB E2E for IPR2014-00970 and IPR2017-00561 and the certificate of correction to determine precisely which of claims 8–35 (if any) remain. The IPR2017-00561 FWD (Paper 36, 2018-07-05) is the cleanest citation for claims 2–7 and the collateral-estoppel termination of claim 1: https://www.docketalarm.com/cases/PTAB/IPR2020-01421/SK_hynix_Inc._v._Netlist_Inc/docs/08-21-2020-Petitioner/Exhibit-1025-Final_Written_Decision,_SK_hynix_Inc_v_Netlist,_Inc,_Paper_No_36,_IPR2017_00561_July_5,_2018.pdf. For claim 1's cancellation, cite IPR2014-00970, Paper 32 (FWD 2015-12-14) as affirmed in Fed. Cir. No. 2016-2274 (judgment 2017-11-14).
2. If you are a new defendant (not SanDisk/Smart Modular/SK hynix or a privy): § 315(e)(2) does not bind you. Serve invalidity contentions relying on Averbuj (US 7,392,442 B2) and Tsern (US 2007/0070669 A1) for any surviving claim, plus the '1372 art (Best, Pandey, Rajan) — and plead expiration for lack of maintenance-fee payment as an independent, claim-independent defense.
3. If you are in privity with a prior petitioner: you are estopped on the Averbuj/Tsern grounds; pivot to (a) the certificate/claim-status issue — most asserted claims are canceled — and (b) non-infringement and the fee-lapse expiration defense, which are not subject to IPR estoppel.
4. No active proceeding is pending, so there are no institution-deadline or FWD milestones to calendar; the practical question is purely whether any of the certified residual claims (if any survive) reads on your product.

I was not able to complete further live searches within my step budget, and — importantly — the USPTO Assignment Center's interactive search pages could not be scraped from the sources available to me. Reel/frame numbers and the recorded "correspondent of record" for each filing could not be independently verified, so I am not fabricating them. Everything below that is stated as a recorded event is sourced from the Google Patents legal-event feed for US 8001434 (cross-checked against Netlist SEC filings for the 2013 transaction). Where a field is unverified, I say so explicitly.

Inventors

Pattern check: No evidence of any inventor departing Netlist shortly after filing; all three appear in Netlist's employment/assignment orbit (Irvine is Netlist's HQ). No unusual pattern — no fire-sale precursor signal here. (Note: I could not verify individual employment records; this is inference from the assignment, not a confirmed fact.)

Original assignee

• Netlist, Inc. (Delaware corporation, HQ Irvine, CA) is the entity named on the issued patent and the original assignee of record.
• Line of business: operating company that designs and manufactures high-performance, logic-based memory subsystems (registered DIMMs, NVvault/NVDIMM products, HyperCloud) for datacenter/storage markets — it ships products and is not a paper company.
• Current status: still operating and publicly traded (OTC/NYSE American ticker NLST); it remains an active patent litigant (Samsung, SK hynix, Google, Smart Modular/Diablo matters). The '434 patent itself is expired — fee related (maintenance fees not paid; adjusted expiration ~2029-08-22) and suffered PTAB invalidity rulings affirmed by the CAFC via Rule 36 in December 2019 — so it is not a revenue-generating asset today.

Assignment timeline

Data limitation: The Google Patents legal-event feed for US 8001434 shows four recorded ownership/security events (below). Reel/frame numbers and the correspondent-of-record fields are not verifiable from the sources I could reach (USPTO Assignment Center requires interactive query; secondary indexes did not expose reel/frames for this patent). Treat the reel/frame slots below as not verified — do not cite them as recorded numbers.

1. Executed ~2009 (at filing) / recorded 2010-11-01 — Reel/frame: not verified

   • Conveyance: Assignment of Assignors' Interest (inventor → company)
   • Assignor: Hyun Lee; Jayesh R. Bhakta; Soonju Choi
   • Assignee: Netlist, Inc.
   • Correspondent: not retrievable from available sources
   • Context: Standard employment-era assignment from the three named inventors to Netlist — normal origination, not a transfer event of analytical interest.

2. Executed 2013-07-18 / recorded 2013-07-18 — Reel/frame: not verified

   • Conveyance: Security Agreement (not an assignment of title)
   • Assignor: Netlist, Inc.
   • Assignee: DBD Credit Funding LLC (Delaware LLC; an affiliate of Fortress Investment Group)
   • Correspondent: not retrievable from available sources
   • Context: Debt collateral. Netlist's 8-K and 10-Q (July/Nov. 2013) confirm a Loan and Security Agreement with DBD (up to $10M term / $5M revolver, $6M drawn at closing) secured by an Intellectual Property Security Agreement covering the "Company Patent Portfolio" — the '434 patent appears on Exhibit B of that IP Security Agreement (per the exhibit text reproduced in SEC filings). Netlist retained title; this is a lender lien, not a transfer to an NPE.

3. Executed ~Dec. 2015 / recorded 2015-12-03 — Reel/frame: not verified

   • Conveyance: Termination of Intellectual Property Security Agreement
   • Assignor: DBD Credit Funding LLC
   • Assignee: Netlist, Inc.
   • Correspondent: not retrievable from available sources
   • Context: Payoff/release of the Fortress/DBD lien; title and full control revert cleanly to Netlist. No intermediate LLC chain.

4. Executed ~Nov. 2023 / recorded 2023-11-20 — Reel/frame: not verified

   • Conveyance: Release by Secured Party
   • Assignor: SVIC No. 28 New Technology Business Investment L.L.P. (a Korean venture-investment limited partnership)
   • Assignee: Netlist, Inc.
   • Correspondent: not retrievable from available sources
   • Context: Release of a later security interest held by SVIC (consistent with Netlist's post-2020 secured convertible-note financings with Samsung Venture Investment-affiliated funds). Another debt-collateral release — the patent stayed with Netlist throughout.

Bottom line on the record: there is no recorded assignment that ever transferred title away from Netlist, Inc. The only non-Netlist parties to touch the patent (DBD Credit Funding LLC 2013; SVIC No. 28, released 2023) were secured lenders whose interests were both released back to Netlist. The Assignment Center almost certainly shows only these inventor-to-Netlist, security-agreement, and release filings for this patent number.

Timeline diagram

timeline
    title Ownership of US 8001434
    2009 : Filed by Netlist Inc
    2010 : Inventors assign to Netlist
    2011 : Patent issued
    2013 : DBD Credit Funding security lien
    2015 : DBD lien released to Netlist
    2019 : CAFC affirms PTAB invalidity
    2023 : SVIC security lien released

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. No recorded transfer to any "IP / Licensing / Holdings / Ventures" LLC. DBD Credit Funding LLC is a Fortress-affiliated lender taking a security interest as loan collateral (SEC-documented, July 18, 2013), not a licensing shell; title never left Netlist.
2. Known asserter in the chain — Not present. No Acacia, Marathon, IV, Conversant/Mosaid, IPNav, or similar entity appears. The asserting party on this patent was Netlist itself (ITC Inv. 337-TA-1023; N.D. Cal. 4:13-cv-05889; C.D. Cal. 8:16-cv-01605). Netlist is an operating company, not on NPE lists.
3. Repeat correspondent across the chain — Unclear / unverifiable. Correspondent-of-record data was not retrievable from my sources. No finding either way; do not treat the absence as exculpatory — it is simply unknown.
4. Cascading transfers — Not present. Only four recorded events over 14 years: one inventor assignment, two security liens, two releases (DBD 2015, SVIC 2023). No chained-LLC cascade in <24 months.
5. Pre-litigation transfer — Not present. Netlist owned the patent before, during, and after every assertion (Smart Modular suits 2009–2013, ITC 337-TA-1023, SK hynix C.D. Cal. 2016). The 2013 DBD security agreement coincided with financing, not with creating standing for a new plaintiff.
6. Bankruptcy fire-sale — Not present. Netlist has never been in Chapter 7/11; it remains an operating public company.
7. Privateering — Not present. No SEC or press evidence that Netlist transferred this patent to a third-party NPE to sue competitors on its behalf. (Note: the 2013 Drawbridge "Monetization Letter" gave the lender a revenue share and required Netlist to use commercially reasonable monetization efforts — a lender-pressure signal, but assertion remained in Netlist's own name and ownership.)
8. Defensive aggregator (anti-NPE) — Not present. Chain does not end at RPX/AST/LOT/Unified/OIN. It ends at Netlist, which has asserted rather than retired the patent (and the patent is now expired and PTAB-diminished anyway).

Verdict

Operating-company assertion.

Netlist, Inc. — an operating memory-module manufacturer that ships products — is the original and current owner of record; the only non-Netlist entries in the chain (DBD Credit Funding LLC security agreement recorded 2013-07-18 and released 2015-12-03; SVIC No. 28 interest released 2023-11-20) are loan-collateral liens that were each released back to Netlist, not transfers to licensing shells. Netlist asserted the '434 patent in its own name against actual competitors (ITC 337-TA-1023; SK hynix C.D. Cal. 8:16-cv-01605; Smart Modular N.D. Cal. 4:13-cv-05889), which is the hallmark of operating-company assertion rather than NPE activity. No shell-entity, privateering, cascading-transfer, or known-asserter signal is present; the only unverified item is the correspondent-of-record field, which does not by itself support an NPE inference. Verify the raw entries at the USPTO Assignment Center (https://assignmentcenter.uspto.gov/ or https://assignment.uspto.gov/patent/index.html — search patent number 8001434) to capture reel/frame numbers and correspondents, which my sources did not expose.

I'll search for the prior-art citations listed for US 8,001,434. Let me look at the patent's citation records from multiple sources.

I have good initial data. Let me retrieve the complete list of references cited on the face of US 8,001,434 and details on the key prior-art references identified in the IPR proceedings.

I have solid information on the IPR primary reference (Averbuj). Now let me obtain the complete examiner-cited reference list from the patent face and details on the Tsern reference used in the IPR combination.

I have reached the search limit for this session, but I have enough verified material from the patent face, FreePatentsOnline's mirror of the "References Cited," and the PTAB/IPR record to give you a grounded analysis. Below is what is confirmed and what remains uncertain.

Prior-Art Analysis: US 8,001,434 B1 ("Memory Board with Self-Testing Capability")

1. Source and verification notes

• The patent's front page (patentimages.storage.googleapis.com PDF for US8001434) and FreePatentsOnline's mirror of the same patent both reproduce the examiner's "References Cited" list. I verified portions of each; the lists are long (the examiner cited roughly 80+ U.S. documents plus at least one IEEE paper), and I could only capture partial snapshots before hitting my search limit.
• The most important prior-art references — the ones actually litigated — are documented in IPR2017-00561 (SK hynix v. Netlist, petition PDF retrieved) and the earlier IPR2014-00970 final written decision it relies on. Those give verified, claim-by-claim §102/§103 positions.
• Claim-number caveat (same flag as in the prior summary): the IPR record confirms the operative independent claims are claims 1–7 (the IPR petition challenges "claims 1-7"). The post-IPR certified claim set on uspto.report shows "circuit comprising" language added to the independent claims; the substance of claims 1–7 is as summarized earlier. All §102 mapping below refers to claims 1–7 as challenged.

2. Most relevant prior art (litigated references)

2.1 US 2005/0257109 A1 — "Averbuj" (primary §102 reference)

Description: A three-tier, distributed/hierarchical BIST architecture: (1) a centralized BIST controller that stores test algorithms as generalized commands independent of memory timing/physical organization; (2) distributed sequencers that interpret the commands and generate sequences of memory operations (address, data, and control signals) at the target memory speed; and (3) memory interfaces that translate address/data to the physical characteristics of each memory module (row/column translation; checkerboard or "striped" pattern generation). Memory interfaces automatically compare read data against expected data and report pass/fail. The architecture expressly targets testing of memory modules mounted on circuit boards in a computer/server/embedded system, with each memory interface acting as a "wrapper" on the address/data/control signals of its memory module.

§102 relevance (verified from IPR2017-00561): The petition states: "Claims 1-7 of the '434 Patent are unpatentable as anticipated under 35 U.S.C. § 102 by U.S. Patent Publication No. 2005/0257109 by Averbuj." The petition further states the Board "previously found numerous claims of the 434 Patent, and its child, unpatentable based on Averbuj" in IPR2014-00971 (Paper 37) and IPR2014-00970 (Paper 32).

Which claims it potentially anticipates: Claims 1–7. Representative mapping (from the petition's § VI.A):

• Claim 1 — Averbuj's BIST controller + sequencers = "control module configured to generate address and control signals for testing the memory devices"; the distributed memory interfaces/data-generation units = "data module comprising a plurality of data handlers," each operable independently and coupled to its own memory module/device data ports, each generating data for writing to those ports.
• Claim 2 ("at least two physically separate components mounted on the printed circuit board") — Averbuj's device blocks/interfaces are distributed across multiple circuit-board components.
• Claims 3–4 (separate integrated-circuit packages; handlers positioned on different board portions) — same distributed-teaching argument.
• Claim 5 (data handler positioned "proximate to" its data ports, closer than to other memory devices' ports) — Averbuj's per-module memory interfaces sit adjacent to their respective memory modules (Fig. 4); the petition includes a dedicated § IV.D.5 construction of "proximate to."
• Claim 6 — physical placement/coupling variations of the data handlers.
• Claim 7 (verification of read data against expected data without storing a copy of written data) — Averbuj ¶ 78: memory interfaces "automatically compare[] the data read from the respective memory modules with the expected data," with the expected data being algorithmically re-derived rather than stored.

(Note: the IPR petition also pleads, in the alternative, §103 obviousness over Averbuj alone and over Averbuj in view of Tsern — so even where a given limitation was disputed under §102, the same reference pair was asserted under §103.)

2.2 US 2007/0070669 A1 — "Tsern" (secondary reference in IPR combination)

§102/§103 relevance: In IPR2017-00561, Tsern was asserted only in combination with Averbuj under §103 ("Claims 1-7 are obvious over Averbuj in view of Tsern"), i.e., Tsern was not the primary §102 reference. Its role was to supply any missing memory-module/buffer-placement details (per-slice data handling, buffer-device organization, PCB-mounted plurality of memory devices) should Patent Owner distinguish Averbuj on those points. Accordingly, Tsern is best characterized as a §103 secondary reference rather than a standalone §102 anticipator of claims 1–7.

3. Most relevant references cited on the face of the '434 patent

The following are the closest examiner-cited references (all verified as appearing in the patent's "References Cited" list, via the FreePatentsOnline mirror and/or the Google Patents PDF). None of these — rather than Averbuj — was the reference the Board ultimately used to invalidate claims 1–7, but each is a plausible §102/§103 prior-art candidate depending on the claim element at issue.

3.1 US 7,184,915 B1 — Hansquine et al. ("Tiered BIST for distributed memory modules")

• Citation: US 7,184,915 B1, "Tiered built-in self-test (BIST) architecture for testing distributed memory modules," inventors David W. Hansquine et al., issued February 2007 (filed from the Morphics Technology line; Hansquine is also a named inventor on Averbuj).
• Description: Same distributed/tiered BIST concept family as Averbuj: centralized test control with distributed sequencers/interfaces that generate and apply test patterns to memory modules on a PCB, including data generation and read-data checking local to each module.
• §102 relevance: Potentially anticipates claims 1–7 on the same theory as Averbuj, with a 2007 issue date (well before the '434's April 14, 2008 priority date). Because it is a granted patent rather than a publication, it would also qualify as §102(a)/(b)/(e) art with a clean effective date.

3.2 US 7,284,166 B2 — Zappa et al. (programmable multi-mode BIST/self-repair)

• Citation: US 7,284,166 B2, "Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays," issued October 2007.
• Description: Programmable BIST engine generating address sequences and data patterns for embedded memory arrays, with self-repair and comparison logic.
• §102 relevance: Targeted at embedded arrays (on-chip) rather than module-level distributed handlers; relevant mainly to the data-pattern-generation/verification elements (e.g., claim 7 read/compare-without-stored-copy; dependent claims on cyclic data generation), and weaker on the "plurality of independent data handlers on a PCB" limitation of claim 1.

3.3 US 7,203,873 B2 — Adams (asynchronous control of memory self-test)

• Citation: US 7,203,873 B2, "Asynchronous control of memory self test," issued April 10, 2007.
• Description: Self-test control for memory that runs asynchronously with respect to the normal system clock, generating test addresses/control and comparing read data — relevant to the '434's "test at target system speed / without system controller involvement" features.
• §102 relevance: Possible anticipation of claim 7 (independent verification) and the independent claims' "control module configured to generate address and control signals for testing" if the distributed-data-handler limitation is not required to be read strictly; more likely a §103 building block.

3.4 US 7,253,652 B2 — Azimi et al. (integrated systems testing)

• Citation: US 7,253,652 B2, "Integrated systems testing," issued August 2007.
• Description: System-level testing of integrated circuits/modules using built-in test controllers that generate test signals and check results without external ATE.
• §102 relevance: General system-level self-test teaching; candidate against the method claim and the "self-testing module coupled to a memory controller" environment (claim 1 preamble / claim 29), with the distributed per-device handler structure likely missing.

3.5 US 7,036,064 B1 — Kebichi et al. (synchronization across BIST controllers)

• Citation: US 7,036,064 B1, "Synchronization point across different memory BIST controllers," issued April 25, 2006.
• Description: Multiple memory BIST controllers that operate independently but synchronize at defined points — structurally analogous to the '434's "each data handler operable independently" (claim 1) and to coordinated write/read sequencing by the control module.
• §102 relevance: Strong candidate on the "independently operable data handlers/controllers" element of claim 1 and its dependents; weaker on the module-level PCB/DRAM context.

3.6 US 7,062,696 B1 — Barry et al. (algorithmic test-pattern generator with BIST)

• Citation: US 7,062,696 B1, "Algorithmic test pattern generator, with built-in-self-test (BIST) capabilities, for functional testing of a circuit," issued June 2006.
• Description: ATG/BIST generating algorithmic data patterns and applying/checking them at functional speed — relevant to the cyclic/incrementing/address-derived data patterns of the '434 (claims 1, 7, 20-series).
• §102 relevance: Data-generation/verification elements; not a module-level distributed architecture.

3.7 US 7,053,470 B1 — Sellers et al. (multi-chip package repairable embedded memories)

• Citation: US 7,053,470 B1, "Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information," issued May 30, 2006.
• Description: Multi-chip packaging with BIST/repair for embedded memories; relevant to packaging/die-organization concepts (dependent claims on physically separate components proximate to memory devices).

3.8 US 7,203,873 / US 7,184,915 family relationship note

• US 6,665,817 B1 (Morphics Technology, May 1999 filing) also appears in the citation neighborhood of this art and is the earlier ancestor of the distributed-BIST teaching; treat it as additional §102 art for claims 1–7 if a 2003 effective date for Averbuj were ever disputed (it was not in the IPR — the Board accepted Averbuj's March 20, 2003 provisional priority date).

4. Non-patent literature (on the face of the patent)

5. Remaining face-of-patent citations (lower relevance; listed for completeness)

The examiner also cited a large number of references that are peripheral to the self-test claims — signal-integrity, I/O-driver, power, and DRAM-stack art — including (verified from the two list snapshots): US 3,660,675 (Andrews, 1972); US 3,757,235 (McCormick, 1973); US 4,305,091 (Cooper, 1981); US 4,580,168 (Adilbach, 1986); US 4,701,845 (1987); US 4,752,741 (Kim, 1988); US 4,782,487 (Smelser, 1988); US 4,837,743 (Chiu, 1989); US 5,304,856 (Rainal, 1994); US 5,337,254 (Knee, 1994); US 5,359,235 (Coyle, 1994); US 5,394,037 (Josephson, 1995); US 5,430,335 (Tanoi, 1995); US 5,525,917 (Wong, 1996); US 5,841,296 (Churcher, 1998); US 5,914,543 (Scherpenberg, 1999); US 6,000,048 (Krishna, 1999); US 6,044,481 (Kornachuk, 2000); US 6,070,217 (Connolly, 2000); US 6,196,696 (Bissey, 2001); US 6,194,959 (Kamoshida, 2001); US 6,216,240 (Won, 2001); US 6,467,056 (Satou, 2002); US 6,560,740 (Zuraski, 2003); US 6,614,702 (Lee, 2003); US 6,721,150 (Guerrero, 2004); US 6,812,869 (Rahman, 2004); US 6,829,728 (Cheng, 2004); US 6,918,072 (Cowles, 2005); US 6,928,024 (Pfeiffer, 2005); US 6,928,593 (Halbert, 2005); US 6,930,509 (Banik, 2005); US 6,934,900 (Cheng, 2005); US 7,190,210 (Azrai, 2007); US 7,203,873 (Adams, 2007); plus published applications 2007/0223296 (Miller), 2007/0204075 (Rajan), 2007/0152743 (Keeth), 2007/0109707 (Honda), 2007/0079199 (Chorn), 2007/0058471 (Rajan), 2007/0030814 (Shin), 2006/0271748 (Jain), 2006/0262586 (Solomon), 2006/0242458 (Feldman), 2006/0192653 (Atkinson), 2006/0147217 (Hahin), 2006/0144015 (Cash), 2006/0140015 (Kasamsetty), 2006/0107156 (Lee), 2006/0082383 (Choi), 2005/0289423 (Y—). Of these, the Solomon 2006/0262586 ("Memory module with a circuit providing load isolation and memory domain translation") is a Netlist-family related disclosure (same assignee) and, while it is §102(a) prior art against the later child patents, it is not prior art against the '434 itself because it was filed after the '434's priority date — it appears on the face only as an information disclosure, not as §102 art.

6. Bottom line

• Single strongest §102 reference: Averbuj (US 2005/0257109 A1) — the PTAB record (IPR2014-00970, Paper 32; IPR2017-00561) confirms it as the basis for finding claims 1–7 unpatentable, with the CAFC later affirming (Rule 36, December 2019).
• Secondary §103 reference: Tsern (US 2007/0070669 A1), used only in combination with Averbuj.
• Best examiner-cited analog on the face of the patent: US 7,184,915 B1 (Hansquine), the granted-patent sibling of the Averbuj teaching, published/issued February 2007 — a clean §102 candidate for claims 1–7.
• Moderate candidates: US 7,284,166 (Zappa), US 7,203,873 (Adams), US 7,253,652 (Azimi), US 7,036,064 (Kebichi), US 7,062,696 (Barry), and the 2002 IEEE parallel-BIST paper — each plausibly anticipates specific dependent-claim elements (independent handlers, verification without stored copy, cyclic patterns) but none maps to all of claim 1 as cleanly as Averbuj/Hansquine.

Confidence statements: The Averbuj/Tsern claim mapping (claims 1–7) and the bibliographic data for Averbuj and Tsern are high confidence (verified against the IPR2017-00561 petition text and patent-family records). The face-of-patent list is verified from two independent mirrors but is incomplete (I could not capture all ~80 entries before the search limit); the §102 mapping offered for each non-litigated reference is analytical inference, not a verified element-by-element chart, and should be checked against the full reference text before being relied on. I did not pull the official USPTO PTAB trial certificate, so the currently certified claim text should be verified separately (same caveat as the prior summary).

A note before the analysis: Your instructions reference "the results from the Prior Art section of this page," but no Prior Art section was actually included in the materials provided to me. I have therefore reconstructed the relevant prior-art landscape from (a) the references cited on the face of US 8,001,434, and (b) the prior art actually asserted in the inter partes review proceedings against the '434 patent (IPR2014-00970, IPR2014-01372, and related IPR2014-00971 against the '501 continuation). Where a reference's full bibliographic data could not be verified within my search budget, I say so explicitly rather than fabricate a citation. This is important because the strongest evidence on obviousness of the '434 claims is not hypothetical — it was actually litigated before the PTAB and the Federal Circuit, with mixed outcomes described below.

Obviousness Analysis of US 8,001,434 B1 Under 35 U.S.C. § 103

1. Legal framework

Obviousness under § 103 is assessed from the perspective of a person of ordinary skill in the art ("POSITA") at the time of the invention (effective date here: April 14, 2008, the provisional filing date), asking whether the claimed invention as a whole would have been obvious from prior art. The Graham factors govern: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; and (4) secondary considerations. Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), the analysis must account for "the interrelated teachings of multiple patents," design incentives, and "ordinary innovation," and a combination of familiar elements is obvious when it yields a predictable result — even without an express teaching, suggestion, or motivation in the references themselves.

Applicable prior art date caveat: Because the '434 patent claims priority to April 14, 2008 provisionals, only references published before that date qualify as § 103(a) prior art. All references discussed below (examiner-cited U.S. patents through 2008, and the IPR references) predate that date.

2. Claims in issue

The '434 patent has 35 claims with three independent claims:

• Claim 1 — A self-testing memory module with (i) a PCB couplable to a system memory controller; (ii) plural memory devices, each with data/address/control ports; (iii) a control module generating the address/control signals used for testing; and (iv) a data module with a plurality of data handlers, each data handler operable independently of the others, coupled to its own corresponding plurality of data ports of one or more memory devices, and configured to generate data for writing to those ports.
• Claim 20 — Same module architecture, but the data module has at least one data handler that generates cyclic data (a repeating/deterministic pattern) for writing to the coupled data ports.
• Claim 29 — A method of self-testing using the module of claim 1's architecture.

Notable dependent concepts (relevant to the obviousness analysis): physically separate data-handler IC packages positioned proximate to their DRAMs (claims 2–6); read-back verification without storing a copy of written data, e.g., by computing expected/comparison data from the cyclic pattern or current read address (claims 7–12, 21–25); storing failed data in the data module and failed addresses in the control module (claims 13, 26); mux/demux switches selecting between system-controller data and self-test data (claims 14–16, 35); DRAM-controller-based selection between address/control sources (claims 17–19).

Caveat on the operative claim set: As noted in the prior summary, the '434 went through IPR, and the version visible on secondary USPTO mirrors may reflect amended claims (adding a "circuit comprising" limitation to each independent claim). The substance analyzed here is consistent across versions, but any formal opinion should verify the certified claim text against the USPTO PTAB trial certificate.

3. The prior-art landscape (as of April 2008)

3.1 References identified in the IPR record (most probative — actually litigated against these claims)

The SanDisk IPR (IPR2014-00970, challenging the '434) and its sibling IPR2014-00971 (challenging continuation '501) were litigated on essentially four references: Averbuj, Huang, Tsern, and the JEDEC standard (per the Patent Owner's Preliminary Response in IPR2014-00971, which lists "[t]he asserted prior art references: Averbuj; Huang; … Tsern; JEDEC Standard"). See Netlist's CAFC brief and the Patent Owner Preliminary Response, Netlist, Inc. v. SanDisk LLC, Nos. 2016-2274, -2275, -2338, -2339, available at https://www.docketalarm.com/cases/PTAB/IPR2014-00971/.../Preliminary_Response-10-Patent_Owners_Preliminary_Response.pdf.

From the CAFC briefing, I can confirm the following about the PTAB's Huang-based obviousness holding for the "Group B claims":

• The Board found that Huang's "transparent memory interfaces" are "operable independently" under the Board's construction, and that Huang renders all of the Group B claims obvious.
• SanDisk's prima facie case cited "the data generation method used by Huang's transparent memory [interfaces]" as the analog to the claimed independent "data handlers."
• The Federal Circuit affirmed the Board on this ground on November 14, 2017 (nonprecedential, per curiam). See https://cases.justia.com/federal/appellate-courts/cafc/16-2274/16-2274-2017-11-14.pdf; https://www.cetient.com/case/netlist-inc-v-sandisk-llc-[4442952](/patent/4442952).

Honest limitation: I could not, within the search budget, confirm the full patent-number citations for "Huang," "Averbuj," and "Tsern." The CAFC/PTAB record identifies them only by inventor surname in the excerpts retrieved. Treat the exact bibliographic identities as needing verification on the PTAB API or the IPR2014-00970/00971 dockets. The analytical discussion below uses them in the roles the record confirms.

The Smart Modular IPR (IPR2014-01372, challenging all 35 claims of the '434) was instituted on claims 1–4, 14–20, 27, and 29, and resulted in a Final Written Decision (March 9, 2016) finding no claim unpatentable; the CAFC affirmed (Nos. 2016-2666, -2667, Nov. 14, 2017). See https://services.patexia.com/lawsuits/SMART-Modular-Technologies-Inc-v-Netlist-Inc-id-63627; https://www.cetient.com/case/smart-modular-technologies-v-netlist-inc-[4442951](/patent/4442951); https://www.mcandrews-ip.com/results/netlist-wins-big-two/. I could not confirm the specific references Smart Modular relied on in IPR2014-01372 from the retrieved pages.

3.2 Examiner-cited references (face of the patent)

The most relevant references cited during prosecution (per FreePatentsOnline's listing of US Patent References, https://www.freepatentsonline.com/[8001434](/patent/8001434).html) fall into recognizable clusters:

This examiner cluster is also reflected in Unified Patents' "Patent Art (81)" aggregation for US-8001434-B1 (https://portal.unifiedpatents.com/patents/patent/US-8001434-B1), which includes US 6,070,217, US 4,782,487, US 6,934,900, US 7,184,915, US 4,903,266, US 6,928,593, and others.

4. Where the obviousness pressure is highest: mapping claims to combinations

4.1 Combination A — Huang, alone or with Tsern/Averbuj (the ground that actually succeeded)

The record shows the PTAB held the "Group B" claims of the '434/501 family obvious over Huang, and the CAFC affirmed. Group B, per the briefing, maps to the claims requiring the plural, independently operable data handlers (the heart of claim 1 and its dependents). The Board's reasoning, as summarized in the CAFC briefs, was:

1. Huang discloses a memory architecture with multiple "transparent" interfaces (one per memory-device byte-lane or rank), each with its own data-generation capability. Under the Board's construction, "operable independently" means each data handler can perform its data-generation function for its own data ports without relying on data from the other handlers — which the Board found Huang's transparent interfaces satisfy because each interface generates its own data locally.
2. Each Huang interface is coupled to a corresponding plurality of data ports of its associated memory device(s), satisfying the structural "corresponding plurality" limitation.
3. Huang's interfaces generate the write-data patterns (data generation), satisfying the final functional limitation.
4. The control-side address/control generation was supplied by Huang itself or by combination with Tsern (a memory-controller/hub reference) and Averbuj (a BIST sequencer/address-generation reference), per the IPR2014-00971 preliminary-response outline of the grounds: "Claims 1–5 and 14–16 are NOT unpatentable over Huang in view of Tsern"; "Claims 6–8, 11–13 and 17–20 … over Huang in view of Tsern and Averbuj"; "Claims 9 and 10 … over Huang in view of Tsern, Averbuj and the JEDEC Standard."

Why a POSITA would combine Huang with Tsern and/or Averbuj: Huang's distributed-transparent-interface architecture supplies the modular, per-lane data handlers, but a full module self-test also requires (i) a source of ordered address/control sequences — the classical function of Averbuj's BIST sequencer — and (ii) standards-compliant memory protocol/timing — the role of Tsern (memory controller/hub signaling) and the JEDEC DDR standards, which the '434 specification itself concedes govern the address/control/data edge relationships. Combining a known BIST address/control generator (Averbuj), a known hub/controller timing interface (Tsern), and the governing JEDEC protocol to drive Huang's already-data-capable transparent interfaces yields exactly the claimed "control module + plural independent data handlers" module. Each element performs its known function, in a combination that a POSITA designing a self-testing DIMM circa 2008 would find predictable. This is precisely why the Board's Huang ground survived appellate review.

4.2 Combination B — Averbuj + Tsern (anticipation-adjacent obviousness for the control-side claims)

Per the IPR2014-00971 record, the petitioners also pressed Averbuj as disclosing (or rendering obvious) the address/control-generation and test-execution features. Netlist's own CAFC brief describes SanDisk's theory that "Averbuj's sequencer 'generates' address and control signals because it 'causes' address and control signals to be produced by Averbuj's address generation unit." The combination with Tsern supplies the memory-protocol-compliant interface and the data-path relationship to the memory devices. For claims that do not require the full plurality of independent handlers (e.g., claim 20's "at least one data handler" generating cyclic data), Averbuj + Tsern is a tighter fit: Averbuj provides the test controller/sequencer (control module) and Tsern provides the module-level hub that can generate cyclic write data to the DRAMs.

Motivation: Averbuj is a BIST controller optimized for a single memory or narrow interface; Tsern is a module-level buffer/hub. Combining them extends BIST from chip-level to module-level — exactly the problem the '434 patent addresses (the Background section of the '434 itself complains that MBIST is hard to implement at DIMM level because of inter-block signal limits and routing). A POSITA seeking module-level self-test at speed would look to place Averbuj's sequencer in the module's register/control path (as the '434's "control module" does) while using Tsern's hub data steering (as the '434's "data module"/switches do).

4.3 Combination C — Examiner-cluster art: distributed/tiered BIST + module data-path isolation switches

Even setting aside the IPR art, a conventional Graham analysis over the examiner-cited art supports an obviousness case on the broad independent claims:

Primary reference: US 7,184,915 (Hansquine) — "Tiered built-in self-test (BIST) architecture for testing distributed memory modules." This reference is on point for the central inventive concept: distributing BIST data generation/checking across multiple test engines (tiers) on a memory module, rather than centralizing it. A POSITA reading Hansquine would understand the design incentive — the '434's own Background explains that module-level MBIST is difficult because a single AMB/ASIC limits data width and creates routing problems. Hansquine's tiered architecture is the textbook response: place data-generation/check logic near the memory devices.

Secondary reference: US 6,070,217 (IBM) — in-line bus switches on a high-density memory module that selectively couple/decouple DRAM data buses in response to read/write selection. This supplies the "switch/mux" limitation (claims 14–16, 35): the claimed data handler's switch that selects between system-controller data and self-test data is precisely an in-line bus switch, and IBM's reference shows such switches are known at the DIMM data-path level.

Secondary reference: US 2006/0262586 (Solomon, Netlist's own load-isolation work) and US 2007/0058471 (Rajan) — both teach isolating the system data bus from the module DRAMs using intermediate buffering/hub circuits, which is the same "isolate the data path during self-test" function the '434 describes and the same physical placement problem (logic near the edge connectors vs. near the DRAMs) its distributed data handlers solve.

Why a POSITA would combine: The claimed invention is, at bottom, (Hansquine's distributed BIST data engines) + (IBM's or Solomon's data-path isolation switches) + (Averbuj/standard DRAM-controller-style address sequencing), all governed by JEDEC DDR timing. Each element was known in the art for the function it performs in the claim; the only question is whether the particular architecture — multiple independent handlers, each generating data for its own ports without inter-handler communication, with no stored copy of written data for verification — would have been obvious. That question is where the '434 claims draw their line, and it is the question the PTAB actually resolved in Netlist's favor against Smart Modular's art (IPR2014-01372) but against Netlist on the Huang ground (IPR2014-00970, affirmed). This split outcome underscores that the obviousness answer is claim-set- and reference-dependent, not uniform across all 35 claims.

4.4 Dependent-claim pressure points

• "Operable independently" (claims 1, 29 and dependents): The decisive limitation. The PTAB found Huang's transparent interfaces satisfied it (each interface generates its own data), but found Smart Modular's combination did not prove it. For an obviousness challenger, the strongest path is to show the reference's data-generation logic is physically and logically per-lane (as in Huang and Hansquine's tiered engines) — at which point "independence" is an inherent property of distributed per-lane generation, not an added inventive feature.
• Verification without storing a copy (claims 7–12, 21–25): Computing expected data from a deterministic/cyclic pattern or from the current address is classic algorithmic test-pattern generation (cf. US 6,934,900; US 7,062,696; US 7,036,064) applied to read-compare. A POSITA would be motivated to regenerate expected data rather than store it to save module memory/registers — a routine design choice, and one the '434 specification itself describes as an advantage ("does not require separate memory for storing duplicate copies").
• Physically separate IC packages placed proximate to the DRAMs (claims 2–6): This is a routing/electrical design choice directly motivated by the '434's own admitted problem (AMB-centralized BIST causes "DIMM level routing problems," signal delay, and fixed data width). Placing per-lane buffers near their DRAMs was already the norm in load-reduction DIMM design (Solomon/Rajan references), so applying the same placement to BIST data handlers is a predictable design step.
• Cyclic data (claim 20): Alternating/incrementing/decrementing patterns written by address are the most basic memory-test patterns in the art (checkerboard, A/5 patterns are textbook), as reflected in US 4,782,487 and US 4,903,266. The only question is whether generating them from within a module-level data handler (rather than from the system controller or external ATE) was non-obvious — which again collapses into the "operable independently" distributed-handler question.

5. Motivation summary (why a POSITA would combine)

1. Cost pressure from ETT DRAMs: The '434 Background concedes module makers buy cheaper "effectively tested" DRAMs and must validate them at module level. This creates a direct design incentive to build low-cost, module-resident test capability — the raison d'être of every BIST reference in the art.
2. ATE cost and speed: External testers are expensive and cannot easily test a module at target-system speed inside the host. Prior art (Siemens 6,829,728 "full-speed BIST"; Intel 6,928,593) already taught full-speed on-chip BIST; extending that teaching to the module with a local clock is an obvious analog.
3. AMB-centralized BIST was known to be deficient: The '434 itself describes the routing/data-width problems of AMB-based BIST. Hansquine's tiered BIST and the load-isolation buffering art (IBM 6,070,217; Solomon; Rajan) provided the known solution pattern: distribute the logic. Combining a distributed BIST architecture with known module data-path switches yields the claimed module with predictable success.
4. JEDEC-standard signaling: Because the DRAMs must be driven per JEDEC DDR protocol, any module-resident test generator must produce JEDEC-compliant address/control/data timing — a constraint that points directly to adapting known DRAM-controller or register-logic designs (Averbuj's sequencer, Tsern's hub, or the JEDEC specs themselves) as the "control module."
5. No-secondary-memory verification: Regenerating expected data from the pattern/address (rather than storing a golden copy) is a standard memory-BIST technique to minimize on-module storage; motivation to use it is inherent in the module context where board space and register count are constrained.

6. Objective indicia and the actual litigated outcome

For balance, the record contains objective evidence cutting both ways:

• Against obviousness (supporting validity): In IPR2014-01372 (Smart Modular), the PTAB found the petitioner failed to prove any of the 35 claims unpatentable, and the CAFC affirmed (Nov. 14, 2017). Netlist also publicized the PTAB's confirmation of claims 2, 5, 6, 7–13, 17, 18, 26, and 35 in the SanDisk IPR. Long-felt need and industry adoption (LRDIMM/self-test module commercialization) could support non-obviousness of the surviving claims.
• For obviousness (against validity): In IPR2014-00970, the PTAB found the Group B claims obvious over Huang, the CAFC affirmed, and — per Netlist's December 2019 press release — the CAFC later affirmed (Rule 36) invalidity of US 8,869,064, 8,001,434, and 8,359,501 in the SK hynix/ITC 337-TA-1023-related appeal. See the litigation summary above. If the operative claims at that stage included the Group B claims, then a final obviousness determination against at least those claims already exists in the record.

7. Bottom line

• The most potent obviousness combination, validated by the actual record, is Huang (alone or with Tsern and/or Averbuj) for the claims centered on plural independently operable data handlers ("Group B"). The PTAB found, and the CAFC affirmed, that Huang's transparent, per-interface data-generation architecture satisfies the independent-handler and data-generation limitations, with Tsern/Averbuj supplying the control-side address sequencing and JEDEC-compliant interface.
• A conventional examiner-cluster combination (Hansquine's tiered distributed BIST + IBM 6,070,217's or Solomon's data-path isolation switches + a known DRAM-sequencer/JEDEC protocol controller) renders the broad architecture of claims 1, 20, and 29 prima facie obvious under KSR, with the fight concentrating on "operable independently" and the no-copy verification limitations.
• The dependent claims add only predictable refinements (per-lane IC placement for routing, mux/demux data selection, address-based expected-data regeneration), all motivated by known DIMM design constraints.
• Countervailing evidence exists: Smart Modular's broader challenge failed entirely at the PTAB, and certain claims were confirmed — so any opinion must be claim-by-claim and reference-by-reference, not a blanket conclusion.

Citations for the key record facts: CAFC affirmance of the Huang obviousness ground, Netlist v. SanDisk, Nos. 2016-2274/-2275/-2338/-2339 (Nov. 14, 2017): https://cases.justia.com/federal/appellate-courts/cafc/16-2274/16-2274-2017-11-14.pdf; CAFC affirmance in Smart Modular appeals, Nos. 2016-2666/-2667: https://www.cetient.com/case/smart-modular-technologies-v-netlist-inc-4442951; PTAB case data for IPR2014-01372: https://services.patexia.com/lawsuits/SMART-Modular-Technologies-Inc-v-Netlist-Inc-id-63627; examiner-cited references: https://www.freepatentsonline.com/8001434.html; litigation art aggregation: https://portal.unifiedpatents.com/patents/patent/US-8001434-B1.

Residual verification needs: (1) full bibliographic citations for Huang, Averbuj, and Tsern (PTAB dockets for IPR2014-00970/00971); (2) the specific art and grounds in IPR2014-01372 and IPR2017-00561; (3) the certified post-IPR claim text and which claims were canceled/amended; and (4) the precise scope of the December 2019 Rule 36 affirmance. I can pursue any of these with additional searches if you want to extend the analysis.