US 6467056

Patent Overview — US6467056B1

Title: Semiconductor integrated circuit and method of checking memory
Patent number: US6467056B1
Application number: US09/461,401 (filed 1999-12-15)
Publication/grant date: 2002-10-15
Priority date (as listed): 1997-04-16
Inventor(s): Masayuki Satou; Isao Shimizu; Hiroshi Fukiage
Original assignee: Hitachi Ltd; current assignee listed as Renesas Electronics Corp (per the source listing, which notes assignee data may be inaccurate)
Legal status (per source): Expired – Fee Related; anticipated expiration 2018-04-16
Source: https://patents.google.com/patent/[US6467056](/patent/US6467056)/en

Purpose. The text describes a technique for diagnosing a semiconductor integrated circuit, particularly for detecting defective bits in a semiconductor memory. It addresses shortcomings of conventional memory testing, where development relies on a memory tester and repeated sample testing, redesign, and retesting (FIG. 11), and of logic-verification approaches such as the "VisualTest" tool and Verilog-based simulators (FIG. 12), which require massive test-pattern files (ranging from a few giga steps to a few mega steps) and therefore permit only partial, not comprehensive, verification.

Plain-language scope. The inventors discuss a "virtual tester" technique comprising a pattern generator (a computer-executable program generating test patterns per a predetermined algorithm) and a simulator that checks a semiconductor memory on a computer from logic design data. The text also notes hardware emulators using FPGAs, which make a logic configuration from HDL and verify operation electrically, avoiding the need to store a test pattern as a file and thus avoiding a high-capacity memory requirement. The source excerpt also mentions a memory-testing/diagnostic method, without detailing claim language.

What the excerpt does not establish. The supplied text is an excerpt; it does not include the full claims, detailed description, drawing descriptions, or the complete background. It does not establish the specific claimed subject matter, the exact inventions covered, prosecution history, or validity. Prior-art documents are not identified beyond the tools and techniques named. Assignee and legal-status entries are source listings, not legal conclusions.