Invalidity dossier
US 6000048
Combined logic and memory circuit with built-in memory test
Current assignee: Cirrus Logic Inc
Added 9/21/2026, 9:36:05 AM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 6000048 A
Title: Combined logic and memory circuit with built-in memory test
Assignee/Original Assignee: Cirrus Logic Inc. (per the source listing). Inventors: Srinivas Krishna and Bernard Sardinha.
Key dates (from source): Priority/filing date 1996-08-14; publication/grant date 1999-12-07; anticipated expiration 2016-08-14; legal status listed as "Expired – Fee Related." A Taiwanese priority filing (TW086111705A, TW330294B) is also listed.
Purpose: As stated in the supplied definitions, the invention "generally relates to the built-in self testing of memory portions of integrated circuits," enabling "the use of a single testing device for testing of electronic integrated circuits incorporating both logic and memory portions." Particularly, it concerns built-in testing of memory embedded in a larger integrated circuit. The stated motivation is that IC fabrication is defect-prone, that defecting elements may surface in only one of many test patterns, and that memory testers and logic/VLSI testers have developed along separate paths, so using one type of tester for the other's circuitry "introduces severe inefficiencies."
Plain-language scope (only what the excerpt shows): The subject matter is an integrated circuit combining logic and memory that includes built-in memory test circuitry, aimed at testing embedded memory. Classifications include G01R31/3187 ("Built-in tests") and G01R31/3181 ("Functional testing"), with further classes covering graphics controllers and bit-mapped memory control (G09G5/363, G09G5/39). The excerpt describes a video-controller context (e.g., a PCI bus linking a host to a VGA board, a video accelerator chip with a logic section, video FIFO, cursor register, and a palette table implemented as SRAM, e.g., a 256×18 lookup table), while stating the invention is not limited to VGA boards, PCI buses, video boards, or video controllers.
What the excerpt does not establish: It contains no claims text, no abstract, no detailed description of the built-in test circuitry's operation, no drawings/figures (image content is not reproduced), and no prior-art references. It therefore does not establish the specific claimed structure, test algorithms, or scope of protection.
Generated 10/1/2026, 10:02:03 PM
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
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Extensions
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Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.