Invalidity dossier

US 6560740

Added 9/21/2026, 1:01:45 PM

At a glanceNo PTAB challengesNo litigation on file

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview: US6560740

Title: Apparatus and method for programmable built-in self-test and self-repair of embedded memory

Patent number: US6560740 (US6560740B1)

Assignee: Advanced Micro Devices, Inc. (original assignee, per the supplied record)

Key dates:

  • Priority/filing date: 1999-08-03 (application US09/366,444)
  • Granted/published: 2003-05-06
  • Anticipated expiration: 2019-08-03
  • Status shown: Expired – Lifetime

Purpose and plain-language scope:
The patent describes testing and repairing memory arrays that are embedded within an integrated circuit chip. Testing circuitry—built-in self-test (BIST), and specifically array BIST (ABIST)—is placed on the chip itself, so the chip can test its own embedded memory rather than relying solely on external equipment.

In broad terms, a semiconductor device may include a memory unit plus a BIST system made up of a BIST logic unit coupled to the memory unit and a master test unit coupled to the BIST logic unit. The master test unit provides a stored memory test pattern to the BIST logic unit and generates address and control signals. The BIST logic unit produces data input signals based on the test pattern, sends them to the memory unit, receives the resulting data output signals, and compares the two to form BIST results. The BIST results may provide fault location information as well as fault detection, and that location information may be used to guide repair of the embedded memory—which typically has redundant rows and/or columns that can replace faulty ones (built-in self-repair, BISR).

The patent is characterized as addressing limitations of hardwired ABIST circuits that cannot be altered after fabrication; the text notes that programmable BIST may avoid needing external circuitry to generate/provide test patterns.

Source: https://patents.google.com/patent/US6560740/en

What the excerpt does not establish: It does not provide the full claims, detailed embodiments, drawing descriptions, examiner citations, or prior-art analysis. It states no litigation, ownership-transfer, or validity conclusions—and none is asserted here.

Generated 10/1/2026, 10:00:59 PM

Cases on file (0)

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Litigation summary

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Proceedings on file (0)

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AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.

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Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

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Prior art

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Obviousness

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Extensions

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Derivative works

Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.

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