US 7634666

I'll run targeted searches for this patent number, including current litigation status.

US Patent 7,634,666 — Analyst Summary

Search scope note: I searched for the literal identifier 7634666 / US7634666B2. All results below relate to that patent. Searches for a 2026 CAFC docket tied to this patent returned no results (see "Litigation / Docket Status"). One search result concerned IPR2025‑01089, but that proceeding's exhibits (Japanese fuel‑injection publications, Heywood's Internal Combustion Engine Fundamentals) relate to a different Longhorn patent — not the '666 — so I have excluded it from the '666 analysis.

1. Bibliographic Data (from the authoritative full text at https://patents.google.com/patent/[US7634666](/patent/US7634666)/en)

Date caveat: the metadata provided to me states today's date as 2026‑09‑11, while your instruction states 2026‑04‑26. Either way, the listed adjusted expiration (2026‑04‑24) means the patent is at/near the end of its enforceable term. I flag the discrepancy rather than resolve it.

2. Abstract (as granted)

"A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller."

3. Plain-Language Overview of the Independent Claims

Claim 1 — the crypto-engine as a co-processor architecture

A cryptographic engine made of two blocks: (a) an arithmetic unit that works as a co-processor to a host CPU, and (b) an interface controller that handles communications between the two. The arithmetic unit contains:

• a memory unit for storing/loading data — itself defined as an input switch (selecting incoming or interim data), several SRAM elements receiving data from that switch, output switches connected to those SRAMs, and an address controller steering data flow through the switches and SRAMs;
• three dedicated arithmetic blocks: a multiplication unit, an addition unit, and a sign inversion unit; and
• an arithmetic controller that governs storing/loading by the memory unit and enables the three arithmetic blocks.

Key structural limitation: the outputs of all three arithmetic units are fed back to the arithmetic controller.

Claim 4 — the crypto-engine including the interface-controller details and RSA/ECC mode selection

Same two-block architecture (arithmetic unit as co-processor + interface controller) and the same arithmetic-unit contents as claim 1 (memory unit; multiplication, addition and sign-inversion units; arithmetic controller with outputs fed back to it). Claim 4 adds specificity to the interface controller, which must include:

• a bus interface for connecting the high-frequency data manipulated inside the arithmetic unit with the lower-frequency data in the host processor (i.e., bridging the heterogeneous clock domains);
• a concatenater/splitter for merging or splitting data width; and
• a cryptographic controller that generates status and interrupt signals for the host processor and generates an op‑code signal for the arithmetic unit, with the arithmetic unit selecting RSA or "EGO" modes of operation based on the op‑code signal.

Literal-reading caveat (per your instruction not to auto-correct): the claim text as published on Google Patents recites "RSA or EGO modes of operation." The specification's corresponding passage reads "RSA or ECC operations." I cannot verify from the sources available whether "EGO" is a typographical error in the granted claim (i.e., a certificate-of-correction artifact), an OCR artifact on Google Patents, or the literal granted text; I flag it rather than assume.

Dependent claims (quick map)

• Claims 2 & 5 (multiplication-unit internals): a register pre-storing the multiplier data; a pair of multiplication elements; a shift register loading the multiplier data bitwise into those elements; and a FIFO register to synchronize data movement between the two multiplication elements.
• Claims 3 & 6 (multiplication-element internals): a bitwise segmented multiplier, bitwise segmented multiplicand, and a modulo, performing modular multiplication of multiplier and multiplicand according to the modulo value.
• Claims 7 & 9 (numerical limits): memory unit size "substantially equal to 384 bytes" and sign-inversion unit k‑size "substantially equal to 64 bits." (Consistent with the spec: k=64; "3×10 24‑bit SRAM blocks" = 3,072 bits = 384 bytes.)
• Claim 8 (dep. on 1): the three arithmetic-unit outputs are fed back to the arithmetic controller and the memory unit.
• Claim 10 (dep. on 4): restates that each of the multiplication, addition and sign-inversion units has an output fed back to the arithmetic controller.
• Claim 11 (dep. on 10): feedback to both the arithmetic controller and the memory unit.

4. Technical Substance (for context)

The engine's stated purpose is a shared hardware platform executing both RSA and ECC (per the spec, "RCA or ECC" and "EEC" appear as apparent typographical variants): both rely on modular multiplication, so the units are shared. The preferred embodiment has a Modular Arithmetic Unit (MAU 11) — SRAM Block 13, Controller 14, Modular Multiplication Unit (MMU) 15, Modular Addition Unit (MADU) 16, Sign Inversion Unit (SIU) 17 — and an Interface Control Unit (ICU 12) with a Bus Interface Unit, Concatenation/Split Unit, and Modular‑opcode Generator inside a Cryptographic Controller. The PEs implement Montgomery's multiplication, using a modified, k‑bit segmented algorithm with two process elements (PE1, PE2) plus a FIFO delay line, and store interim U_out/u_carry_out as (k+1) bits rather than 2k bits to reduce gate count. Reported implementation: 0.35 µm technology, ~15K gates for RSA / ~20K gates for RSA+ECC at k=64; 1024‑bit RSA in ~7 ms (e=2¹⁶+1) and ~607 ms (average 1024‑bit exponent) at 22 MHz.

5. Litigation / Docket Status (most recent first)

• E.D. Tex. 2:24‑cv‑00397, Longhorn Automotive Group LLC v. Nissan Motor Co., Ltd. — filed 2024‑05‑31, assigned to Judge Rodney Gilstrap; consolidated 2024‑10‑22 into lead case 2:24‑cv‑00554 (Hyundai). The '666 is one of five patents‑in‑suit, asserted against Renesas R‑Car SoCs used in Nissan vehicles. Docket: https://dockets.justia.com/docket/texas/txedce/2:2024cv00397/[230526](/patent/230526)
• On 2025‑09‑26, Judge Gilstrap granted Nissan's Rule 12(b)(6) motion to dismiss Longhorn's direct‑infringement claims (finding the "regularly travel[s]… to test and/or troubleshoot" pleading insufficient under Twombly), with leave to amend. Reporting: https://www.fr.com/insights/thought-leadership/blogs/texas-round-up-september-2025/ — Uncertainty: the report describes a method claim; I could not confirm from these sources whether the dismissed direct-infringement count specifically covered the '666 or only other patents‑in‑suit.
• Unified Patents "Patroll" prior-art contest on US‑7,634,666‑B2 (2024‑06‑07 to 2024‑08‑30), targeting at least claim 1; owner identified as Longhorn Automotive Group, "asserted against Nissan"; a winner was announced and winning prior art published 2025‑01‑14. https://patroll.unifiedpatents.com/contests/v4BnWmDzYWwnHPnbG
• PTAB: IPR2014‑00180, petitioner International Business Machines Corporation, filed 2013‑11‑20; an IPR certificate (K1) issued 2018‑02‑07. https://portal.unifiedpatents.com/ptab/case/IPR2014-00180 — Uncertainty: I do not have authoritative confirmation from these searches of the substantive outcome (which claims, if any, were cancelled or confirmed by the final written decision/certificate). Do not treat any claim-survival conclusion as established.
• S.D.N.Y. 1:13‑cv‑03777 (Intellectual Ventures v. JPMorgan Chase) — asserted claim 4 against the IBM 4765 PCIe Cryptographic Coprocessor; the court (Markman) construed "op‑code signal" as a "signal capable of indicating an RSA operation when it has one characteristic and an ECC operation when it has a different characteristic," and addressed capability-versus-actual-performance infringement. Source: http://business.cch.com/ipld/intellectualVjp.pdf
• Earlier IV-era suits and appeals (from the patent's litigation record): D. Neb. 8:13‑cv‑00167; S.D.N.Y. 1:14‑cv‑04638; W.D. Pa. 2:13‑cv‑00740 and 2:14‑cv‑00832; S.D. Ohio 2:13‑cv‑00785; N.D. Ala. 2:13‑cv‑01106; W.D. Mo. 2:13‑cv‑04160; D. Minn. 0:13‑cv‑02071; N.D. Ga. 1:13‑cv‑02454; CAFC 14‑1724, 17‑2429, 18‑1024.

CAFC 2026 docket — explicit finding

I found no 2026 Court of Appeals for the Federal Circuit docket activity for US 7,634,666. My searches for that combination returned zero results. The only Federal Circuit dockets surfaced are the older ones listed in the patent's litigation record (14‑1724, 17‑2429, 18‑1024). I have no authoritative information that any 2026 appeal involving this patent exists; absence of results here is not proof of absence of a filing.

6. Confidence and Gaps

High confidence (grounded in the authoritative patent text): title, application/filing/priority/issue dates, inventors, original assignee and recorded reassignment chain, abstract, all 11 claims and their dependency structure, classifications, and the technical description.

Lower confidence / open items to verify against primary sources (USPTO PatentCenter, PACER, PTAB API):

1. Whether the granted claim 4 text literally says "EGO" or "ECC" (see the literal-reading caveat above).
2. The substantive outcome of IPR2014‑00180 and what the 2018 IPR certificate did to the claims.
3. Whether the '666 remains asserted in the consolidated E.D. Tex. action after the 2025‑09‑26 dismissal-with-leave-to-amend, and whether any appeal to the Federal Circuit has since been docketed.
4. The precise post‑PTA expiration date/term adjustment (Google Patents lists 2026‑04‑24 as "adjusted expiration").

I'll research litigation involving US patent 7634666. Let me start with searches on the key litigation databases and the patent itself.

I found several litigation references. Let me dig deeper into the specific cases, the IPR, and the more recent Longhorn Automotive assertions.

Let me research the remaining case numbers, the IPR outcome, and the Federal Circuit appeals.

I hit my research tool limit before I could confirm every docket detail, so I'll give you what is well-documented and clearly flag what remains unverified. All case numbers, party names, and patent numbers below are reproduced literally as found; I have not normalized or "corrected" any of them.

Litigation involving U.S. Patent No. 7,634,666 ("Crypto-engine for cryptographic processing of data")

Important context first: The '666 patent is titled "Crypto-engine for cryptographic processing of data," issued Dec. 15, 2009, from App. No. 10/641,869 (filed Aug. 15, 2003), priority Aug. 15, 2003. Original assignee CityU Research Ltd / City University of Hong Kong. It passed through Intellectual Ventures entities and is currently held by Longhorn Automotive Group LLC (assignment recorded 2024-03-26, per the Google Patents family/assignment record). The recorded legal status shows "Expired – Lifetime," with an adjusted expiration of 2026-04-24 — i.e., the patent's term has just run out (as of your April 26, 2026 date, roughly two days ago).

The litigation comes from two distinct waves: (1) the 2013–2014 Intellectual Ventures II LLC bank/financial-services campaign, and (2) the 2024 Longhorn Automotive automotive campaign.

Wave 1 — Intellectual Ventures II / Intellectual Ventures I (2013–2014)

Note: IV's 2013 bank campaign asserted the same five patents together — U.S. Pat. Nos. 6,715,084; 6,314,409; 5,745,574; 6,826,694; and 7,634,666 (collectively "the patents-in-suit"). The '666 patent appears in these suits as part of that common package. The Stanford NPE Litigation Database lists only two cases naming the '666 patent (the Citigroup and BBVA cases below); the others are documented in the SunTrust/Google Patents record but are not all individually confirmed as naming the '666 patent in my results.

Additional district-court filings in the same IV family-litigation record that I could not individually confirm as naming the '666 patent (they appear under the patent family's litigation data on Google Patents):

• D. Neb. 8:13-cv-00167 — Nebraska District Court
• W.D. Pa. 2:13-cv-00740 and W.D. Pa. 2:14-cv-00832 — Western District of Pennsylvania
• S.D. Ohio 2:13-cv-00785 — Southern District of Ohio
• W.D. Mo. 2:13-cv-04160 — Western District of Missouri
• D. Minn. 0:13-cv-02071 — District of Minnesota

(I was cut off before I could resolve the parties for these. They likely fit the IV bank-campaign pattern — e.g., other regional banks — but I will not guess at names.)

PTAB — Inter Partes Review

• IPR2014-00180 — petitioner: International Business Machines Corporation (IBM); patent owner: Intellectual Ventures II LLC. The Google Patents record notes "PTAB case IPR2014-00180 filed (Final Written Decision)." Per the SunTrust order, the PTAB instituted IPR on all claims of the '666 patent (claims 1–11) on April 16, 2014, finding IBM had established a reasonable likelihood that claims 1–11 were invalid over the prior art. A Final Written Decision issued, and an Inter Partes Review Certificate (K1) was issued Feb. 7, 2018 (per the patent's legal-events record). (I was unable to confirm in my truncated search whether any claims were cancelled or upheld — the certificate exists, so check the FWD for claim-level outcome.)

Federal Circuit appeals

• No. 14-1724 — Intellectual Ventures II LLC v. JPMorgan Chase & Co. The Federal Circuit dismissed the interlocutory appeal on April 1, 2015 for lack of jurisdiction, holding the court has no jurisdiction over a denied motion to stay pending CBM review until the Board institutes a proceeding. (The '666 patent was one of the patents-in-suit.)
• No. 17-2429 and No. 18-1024 — listed in the Google Patents family-litigation record as Federal Circuit cases involving the family. I could not confirm the parties or subject matter for these two appeals before running out of search steps. They are likely appeals arising from the IV bank litigation and/or the IPR outcomes, but I will not speculate further.

Wave 2 — Longhorn Automotive (2024–present)

Related: Unified Patents ran a prior-art bounty contest on claim 1 of US-7,634,666 (Longhorn Automotive), open June 7 – Aug. 30, 2024, noting the patent "has been asserted against Nissan" and that prior art was found (announced Jan. 14, 2025).

Bottom line

The '666 patent has a substantial litigation history:

• Wave 1 (IV, 2013–2014): at least four confirmed bank/financial-services suits (SunTrust 1:13-cv-02454, JPMorgan Chase 1:13-cv-03777, BBVA Compass 2:13-cv-01106, Citigroup 1:14-cv-04638), plus ~five additional IV filings in the family record I couldn't tie to the '666 patent specifically.
• PTAB: IPR2014-00180 (IBM), instituted on all claims April 16, 2014; FWD issued; IPR certificate issued Feb. 7, 2018.
• CAFC: 14-1724 (dismissed 2015); 17-2429 and 18-1024 (unconfirmed).
• Wave 2 (Longhorn, 2024): Longhorn Automotive Group LLC v. Nissan (E.D. Tex. 2:24-cv-00397, consolidated into 2:24-cv-00554) — claims 1–11 asserted against Nissan.

Caveats / honesty flags:

1. I was cut off by tool limits and could not confirm (a) the parties for case nos. 8:13-cv-00167, 2:13-cv-00740, 2:13-cv-00832, 2:13-cv-00785, 2:13-cv-04160, 0:13-cv-02071; (b) the claim-level outcome of IPR2014-00180's Final Written Decision/IPR certificate; and (c) the identity/subject matter of Fed. Cir. Nos. 17-2429 and 18-1024.
2. The Google Patents "family litigation" list is keyed to family ID 34136462 (which includes both US-7,634,666 and its continuation US-8,458,492), so some listed cases may involve the sibling patent rather than the '666 patent specifically. I flagged those separately rather than presenting them as confirmed.
3. Primary sources to verify the open items: the Unified Patents litigation portal case pages (e.g., portal.unifiedpatents.com/litigation/... for the exact case IDs), the PTAB portal page for IPR2014-00180, and PACER dockets for the E.D. Tex. Longhorn case.

I'll research the AIA trial proceedings. The structured block says the USPTO ODP ingest shows none, but the prior sections flag IPR2014-00180 — an older proceeding that predates ODP's AIA-trial ingest. Let me verify the claim-level outcome, panel, grounds, and any appeals.

The FWD surfaced. Let me confirm the claim-level disposition, whether any claims were canceled, the § 315(e) estoppel posture, and any appeal.

The FWD text shows the Board crediting patent owner on the key "feedback" limitation. Let me confirm the final disposition (claims upheld vs. canceled) and check for any appeal and a parallel CBM.

Proceedings overview

The USPTO Open Data Portal structured block returns no AIA trial proceedings for US 7,634,666 — but that block is wrong for this patent, and I flag the discrepancy explicitly rather than adopt it. Web search surfaced one AIA trial: IPR2014-00180, a pre-2015 legacy IPR that appears to fall outside ODP's AIA-trial ingest window. The consolidated picture is 1 total proceeding — 0 invalidated, 1 fully sustained (all challenged claims), 0 settled, 0 institution-denied.

The bottom line for a defendant today: the '666 has been tested once at the PTAB and came out completely intact — every one of claims 1–11 survived. IBM's obviousness case failed on the single structural limitation (the "feedback" recitation) and on a deficient reason-to-combine. That is a hardening signal, not a "claims canceled" signal — but it is highly ground-specific (Matsuzaki + Dworkin + the IBM § 103 theory), and it does nothing to insulate the patent from different art, such as the prior art surfaced in Unified Patents' 2024–2025 Patroll contest.

IPR2014-00180 — International Business Machines Corporation v. Intellectual Ventures II LLC

• Type: Inter Partes Review (35 U.S.C. §§ 311–318)

• Filed: 2013-11-20

• Status: Final Written Decision issued — all challenged claims held not shown unpatentable (patent survived intact). An Inter Partes Review Certificate (kind code K1) issued 2018-02-07 confirming the outcome. (Google Patents legal-events record lists the K1 certificate dated 2018-02-07.)

• Judge panel: David C. McKone (writing the Final Written Decision), James A. Tartal, and Miriam L. Quinn, Administrative Patent Judges. (Panel confirmed in the 2014-07-03 Conduct Order, Paper 22, and the 2014-08-07 Order, Paper 26.)

• Petition grounds: Obviousness (pre-AIA § 103) of claims 1–11 over Matsuzaki (Ex. 1008, an arithmetic device / co-processor) in view of Dworkin (Ex. 1012, a finite-field and integer-arithmetic processor for ECC/RSA), supported by the declaration of Dr. Çetin Koç (Ex. 1001). Institution decision dated 2014-04-16 — I could not pull the institution paper itself, but the FWD proceeds to the merits on claims 1–11, and prior reporting indicates trial was instituted on all claims 1–11.

• Institution decision: Instituted (2014-04-16). (Flag: the exact institution text — instituted on all claims vs. a subset — is inferred from the FWD reaching all claims and from prior reporting; I did not retrieve the institution paper.)

• Final Written Decision (dated 2015-04-03, Paper 35): No claim canceled. The panel found that Matsuzaki does not disclose the feedback limitation of claims 1 and 4 — "the outputs of the multiplication unit, the addition unit and the sign inversion unit are feedback to the arithmetic controller." Concretely: "As can be seen in Figure 17 . . . the outputs of multiplier 21 and sign inverting unit 51 are inputs to adder 22, rather than feedback to control unit 10," and "the adder operates on (and, thus, changes) those values and outputs a single . . . feedback to the controller. Thus, we find that Matsuzaki does not disclose the feedback limitation of claims 1 and 4." The panel further rejected IBM's attempt to supply the limitation from Dworkin, because IBM never articulated a sufficient reason to combine: "merely pointing out similarities between Matsuzaki and Dworkin and invoking the words 'common sense' . . . is not a sufficient articulation of a reason to combine," and "the lack of expert testimony supporting a sufficient reason to combine Matsuzaki and Dworkin weighs heavily against Petitioner." The dependent claims rise and fall with independent claims 1 and 4, so the sustained result covers claims 1–11.

  • Source (FWD PDF): https://www.finnegan.com/a/web/[115342](/patent/115342)/2G4qSr/ipr2014-00180-final-written-decision-35-usc-c2a7-318a-and-3.pdf

• Settlement / termination: None. This went to a merits FWD; no adverse judgment, no settlement termination.

• Appeal: I found no Federal Circuit appeal of this FWD for the '666 in the searches available. I flag this as an open item rather than asserting none exists — the FWD-issuing petitioner (IBM) had its institution denial upheld in the separate § 315 stay appeal context, but that is a different posture. (The older CAFC dockets 14-1724, 17-2429, and 18-1024 in the family record are unrelated stay/other issues; I could not confirm any of them is this FWD's appeal.)

• Defensive value: The single most-litigated structural hook in this patent — the "outputs . . . feedback to the arithmetic controller" limitation of independent claims 1 and 4 — has already defeated one fully developed obviousness challenge on the merits. Any new IPR must (a) find art that actually feeds the multiplier, adder, and sign-inversion outputs back to the arithmetic controller, and (b) articulate a factually supported reason to combine. Hand-waving "common sense" is exactly what failed IBM.

Procedural color worth knowing (all from the public record):

• Paper 22 (Order, 2014-07-03, by Judge Quinn): the panel denied IBM's request to file inventor deposition testimony (Dr. Chang) as § 42.123(b) supplemental information, and authorized Patent Owner to file a contingent motion to amend. (I could not confirm the disposition of that motion to amend, or whether it was ultimately filed; the K1 certificate covering the original claims suggests no substitute claims were needed.)
• One aggregator (National Law Review / PTAB Trial Blog) captions this case as "CBM2014-00180" while reproducing the caption "Case IPR2014-00180." I treat the "CBM" label as a transcription typo — the caption, patent, and panel are all the IPR. Flagging rather than auto-correcting.

Strategic summary

Claim status. Every claim of US 7,634,666 (claims 1–11) is SUSTAINED — none canceled, none disclaimed, no adverse judgment. Independent claims 1 and 4 are the load-bearing ones, and both survived on the feedback limitation. That means there is currently no canceled claim a defendant can point to in order to neutralize a demand letter. If defending, you cannot say "the troll's claims are dead."

Estoppel landscape (§ 315(e)(2)). The estoppel from IPR2014-00180 runs only against IBM as petitioner and its privies/real parties in interest — it does not bind Longhorn (patent owner) or an unrelated defendant like Nissan. So a fresh challenger is not foreclosed by IBM's loss from raising the same Matsuzaki+Dworkin combination — but using that exact losing theory would be strategically poor, since the PTAB already found it insufficient. The practical effect is the inverse of classic estoppel: the FWD educates your defense. It tells you the artifact that beats this patent is a reference showing all three arithmetic outputs fed back to the arithmetic controller, plus a well-supported motivation to combine.

Available grounds for a current defendant. Because this is a § 103 patent whose prior PTAB trial turned on a single structural limitation, the strongest fresh avenues are non-overlapping art: a single reference (or compliant combination) explicitly disclosing the three-way output feedback to the controller; or art attacking the dependent-claim specifics — the k=64 / 384-byte limits (claims 7, 9) and the Montgomery two-PE + FIFO architecture (claims 2, 3, 5, 6). Note the Unified Patents "Patroll" prior-art contest on US-7,634,666-B2 (open 2024-06-07 to 2024-08-30; winner/art published 2025-01-14) targeting at least claim 1 — the winning art from that bounty is a ready-made lead for a new petition (or a district-court § 282 defense), though it is not itself an AIA trial. https://patroll.unifiedpatents.com/contests/v4BnWmDzYWwnHPnbG

Pattern signals. A defensive aggregator (Unified Patents) entered the chain only in the 2024 Longhorn wave, and there is no new IPR on the '666 from that wave — Nissan's IPR2025-01089 targeted a different Longhorn patent (US 7,513,238) and was denied institution. The patent owner (through its IV predecessors) defended the '666 successfully at the PTAB once and did not need to appeal. There is no serial-petitioner pattern against this patent: IBM filed once and lost.

Critical timing caveat. The patent's adjusted expiration is listed as 2026-04-24, with legal status "Expired – Lifetime." If that holds, the '666 is at or past the end of its enforceable term as of today (2026-09-11) — an IPR against it now would be a fight over a patent that can no longer support forward-looking injunctive relief, and post-expiration en banc Phillips-standard review plus the 1-year statutory trial clock make a new petition of limited practical value. Verify the expiration date against USPTO PatentCenter before spending on a petition.

Recommended next steps

1. Confirm the operative date first. Pull the USPTO PatentCenter "Application Data" / term-adjustment record for 10/641,869 to fix the exact expiration (Google lists 2026-04-24 as adjusted). If the patent has expired, redirect effort from IPR to a § 282 invalidity defense for any pre-expiration damages window (6-year lookback) and to the live E.D. Tex. consolidated case (Longhorn Automotive Group LLC v. Nissan, lead 2:24-cv-00554).
2. Quote the FWD disposition, not a summary of it, when pressuring the case. The operative finding is: Matsuzaki and Dworkin do not disclose or render obvious the feedback limitation of claims 1 and 4, and Petitioner's reason to combine was insufficient. Link the FWD (above) and the IPR Certificate K1 (issued 2018-02-07) so opposing counsel sees the record.
3. Mine the Unified Patents Patroll winning art (published 2025-01-14) as the seed for any new challenge; it was crowd-sourced specifically against claim 1 of this patent and post-dates the IBM IPR, so it is not subject to IBM's § 315(e)(2) estoppel.
4. If a new IPR is contemplated, calendar the statutory milestones: institution decision ~6 months from filing, FWD within 1 year of institution (35 U.S.C. § 316(a)(11)), with the hearing typically ~2–3 months before the FWD deadline. But weigh that against the expiration reality above.
5. Verify the open items I could not fully confirm against primary sources: (a) the institution paper (Paper 7) for the exact scope of institution; (b) whether Patent Owner's contingent motion to amend (authorized 2014-07-03, Paper 22) was ever filed and, if so, its disposition; and (c) whether the 2015-04-03 FWD was appealed to the Federal Circuit. Source: PTAB E2E / USPTO PTAB Decisions (https://www.uspto.gov/patents/ptab/decisions) and the Unified Patents case page (https://portal.unifiedpatents.com/ptab/case/IPR2014-00180).

Honesty flags. The structured "PTAB proceedings on file" block is empty, but that is a false negative for this legacy pre-ODP-ingest IPR — I am overriding the default based on the surfaced FWD and certificate, per instruction to flag contradictions. I have not verified the claim-level text of the K1 certificate myself (I infer "all claims sustained" from the FWD's merits disposition and the absence of any canceled-claim record); treat "no claims canceled" as high-but-not-absolute confidence pending direct inspection of the certificate and FWD conclusion page. I found no AIA trials on this patent after 2015 and no PTAB appeal of the FWD; absence of results is not proof of absence.

I'll research the assignment record and correspondent attorneys for this patent.

Assignment & Ownership Reconstruction — US 7,634,666

Sources actually consulted in this session: the authoritative Google Patents full text/legal‑events record (which exposes reel/frame numbers) at https://patents.google.com/patent/US7634666/en; an RPX Insight litigation report (June 1, 2024); and the prior generated sections of this analysis. I was cut off by tool limits before I could open the USPTO Assignment Center record itself, so the correspondent‑of‑record field (the key tell you asked me to capture) is a verified gap in this report, not a finding. I state that plainly rather than guess at an attorney name.

Cross‑reference note — one date discrepancy to flag: the RPX report states AI‑CORE "received [the patents] from Intellectual Ventures … this past February" (i.e., ~Feb 2024), whereas the USPTO/Google Patents assignment record shows the IV‑Assets‑190 → AI‑CORE transfer executed 2023‑10‑05 and recorded 2023‑10‑13. Per your operating rules I record both and do not reconcile them.

Inventors

Pattern note (comparable to your "all inventors departing within 12 months" screen, but of a different kind): this is a university‑research pattern, not an inventor‑departure pattern. Application 10/641,869 was filed 2003‑08‑15; the inventors' assignment to City University of Hong Kong was executed 2003‑09‑01 — i.e., within about two weeks of filing — which is the standard prompt‑assignment practice for university‑employed inventors under an institutional IP policy. I found no evidence that any inventor left CityU, sold personal rights, or re‑appears anywhere else in the chain. Inventor departures are therefore not a signal here. (I did not verify current employment status of the inventors; that remains open.)

Original assignee

• Entity named on the issued patent: CityU Research Limited (Google Patents lists it as the original assignee of the granted patent; the patent issued 2009‑12‑15, after the 2009 CityU → CityU Research transfer).
• Prosecution‑era assignee: City University of Hong Kong, which received the inventors' rights by the 2003‑09‑01 assignment (Reel 014720/0072).
• Primary line of business: CityU Research Limited is the technology‑transfer / IP‑licensing arm of City University of Hong Kong — i.e., an institutional licensing vehicle, not a product company. City University of Hong Kong is an operating public university (teaching and research).
• Did it ship a product embodying the claims? No evidence of any commercial product. The specification describes an ASIC implementation benchmarked in 0.35 µm technology; the "product" is the licensed IP itself.
• Current status: CityU Research Limited's current corporate status was not verified in this session (no search result confirmed operating/dissolved/acquired). What is verified is that CityU Research divested this patent in 2009, so it has held no rights here for ~17 years.
• Sold off: The university transferred the patent out of the academic sphere entirely in 2009, seven years before the first IV enforcement wave.

Assignment timeline

Seven recorded post‑filing links. Reel/frame values are as exposed in the Google Patents legal‑events record; the underlying reels are the USPTO reels. Correspondent fields could not be retrieved in this session — see signal 3 below.

1. 2003‑09‑01 (executed) / recorded 2003‑11‑24 — Reel 014720/0072

• Conveyance: Assignment
• Assignor: Cheng, Lee Ming; Ngan, Ting On; Hau, Ka Wai
• Assignee: City University of Hong Kong
• Correspondent: not retrieved in this session (gap)
• Context: initial inventor‑to‑university employment assignment (institutional tech‑transfer intake).

2. 2009‑09‑01 (executed) / recorded 2009‑09‑03 — Reel 023180/0671

• Conveyance: Assignment
• Assignor: City University of Hong Kong
• Assignee: CityU Research Limited
• Correspondent: not retrieved in this session (gap)
• Context: internal reorganization — transfer into the university's dedicated IP‑holding/licensing subsidiary.

3. 2009‑09‑25 (executed) / recorded 2010‑02‑09 — Reel 023915/0101

• Conveyance: Assignment
• Assignor: CityU Research Limited
• Assignee: Intellectual Ventures Holding 57 LLC
• Correspondent: not retrieved in this session (gap)
• Context: outright sale of the university's patent to a monetization entity — the pivot point of the entire chain.

4. 2013‑05‑23 (executed) / recorded 2013‑05‑28 — Reel 030494/0239

• Conveyance: Merger
• Assignor: Intellectual Ventures Holding 57 LLC
• Assignee: Intellectual Ventures II LLC
• Correspondent: not retrieved in this session (gap)
• Context: internal IV corporate reorganization via merger (Delaware entity).

5. 2023‑09‑25 (executed) / recorded 2023‑09‑25 — Reel 065015/0675

• Conveyance: Assignment
• Assignor: Intellectual Ventures II LLC
• Assignee: Intellectual Ventures Assets 190 LLC
• Correspondent: not retrieved in this session (gap)
• Context: IV portfolio carve‑out into a numbered disposal vehicle ("Assets 190") — same‑day execution and recording.

6. 2023‑10‑05 (executed) / recorded 2023‑10‑13 — Reel 065227/0107

• Conveyance: Assignment
• Assignor: Intellectual Ventures Assets 190 LLC
• Assignee: AI‑Core Technologies, LLC
• Correspondent: not retrieved in this session (gap)
• Context: transfer to a licensing‑only LLC (Texas), ten days after the carve‑out; AI‑Core is a monetization conduit, not a product company.

7. 2023‑10‑06 (executed) / recorded 2024‑03‑26 — Reel 066911/0261

• Conveyance: Assignment
• Assignor: AI‑Core Technologies, LLC
• Assignee: Longhorn Automotive Group LLC
• Correspondent: not retrieved in this session (gap)
• Context: transfer‑to‑asserter. Note the striking sequencing: executory date 2023‑10‑06 is one day after the AI‑CORE acquisition executed (2023‑10‑05) — the asset passed through AI‑Core essentially in transit — while recording lagged to 2024‑03‑26, roughly two months before Longhorn's first suit (2024‑05‑31).

Not assignments (for completeness, so they aren't misread as chain links): two Certificates of Correction recorded 2010‑03‑30 and 2010‑11‑09; fee payments 2013‑03‑18, 2017‑05‑25, 2021‑05‑13; IPR2014‑00180 filing/IPR certificate events 2014‑01‑07 and 2018‑02‑13. None convey title.

Timeline diagram

timeline
    title Ownership of US 7634666
    2003 : Inventors assign to City University of Hong Kong
    2009 : CityU transfers to CityU Research Limited
         : CityU Research sells to IV Holding 57
    2013 : Merger into Intellectual Ventures II
    2023 : IV II carves out to IV Assets 190
         : Reel 065227 0107 to AI-Core Technologies
         : Reel 066911 0261 to Longhorn Automotive
    2024 : Longhorn sues Nissan in East Texas

(Event text above omits the reel slash separators and commas deliberately, per the parseability constraint; the full reel/frame values appear in the timeline section above.)

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Concrete evidence, not naming inference: Reel 023915/0101 (executed 2009‑09‑25) moved the patent from CityU Research Limited — a university tech‑transfer arm — to Intellectual Ventures Holding 57 LLC, a holding vehicle. The chain then runs through Reel 030494/0239 (merger into IV II LLC), Reel 065015/0675 (carve‑out to IV Assets 190 LLC), Reel 065227/0107 (AI‑Core Technologies, LLC), Reel 066911/0261 (Longhorn Automotive Group LLC). The terminal assignees are licensing‑only LLCs with no products in commerce; the naming suffix pattern (Assets / Holdings / Technologies) alone is not the finding — the finding is the sequence of single‑purpose conveyance links plus a same‑week pass‑through (2023‑10‑05 out of IV Assets 190, 2023‑10‑06 to Longhorn).

2. Known asserter in the chain — PRESENT.
Intellectual Ventures is expressly on your enumerated public‑NPE list, and it appears on Reel 023915/0101 and Reel 030494/0239. Longhorn Automotive Group LLC is the current assignee and is an active plaintiff (E.D. Tex. 2:24‑cv‑00397, filed 2024‑05‑31, asserting the '666 against Nissan over Renesas R‑Car SoCs). RPX described Longhorn as a "funded Texas plaintiff" launching an "automotive campaign over former IV patents," with "apparent backing from a prominent litigation funder," and referenced Alpha Alpha Intellectual Partners LLC. (Attribution caveat: the RPX phrasing is reproduced as published; I have not independently verified the funding or the Alpha Alpha relationship.)

3. Repeat correspondent across the chain — UNCLEAR / NOT VERIFIED.
This is the signal I was specifically asked to nail and could not: I did not retrieve the correspondent‑of‑record for any of the seven links. Google Patents' legal‑events record exposes assignor/assignee/reel‑frame/dates but not the recording correspondent, and my searches for the reel numbers and for the assignee LLCs returned no correspondent data before the tool limit was hit. I therefore cannot say whether one attorney or firm filed all seven recordals. On the evidence available this signal is not established. To close it, pull the individual reel/frame entries at the USPTO Assignment Center (search by patent number) and read the "correspondent" field on each — that is the single highest‑value follow‑up here.

4. Cascading transfers — PRESENT.
At least three consecutive transfers in roughly a nine‑month window in 2023–2024: Reel 065015/0675 (2023‑09‑25) → Reel 065227/0107 (2023‑10‑05/13) → Reel 066911/0261 (executed 2023‑10‑06, recorded 2024‑03‑26). The near‑simultaneous execution dates on links 6 and 7 indicate the patent was routed through AI‑Core in transit to Longhorn. (Separately, the 2013 IV Holding 57 → IV II merger is an internal reorg, not an NPE cascade.)

5. Pre-litigation transfer — PRESENT.
Longhorn's assignment was executed 2023‑10‑06 and recorded 2024‑03‑26; Longhorn's first suit naming the patent was filed 2024‑05‑31 — i.e., roughly two months after the recorded assignment and under eight months after execution. This is consistent with a chain arranged to vest clean title and set venue before assertion (E.D. Tex., Judge Gilstrap).

6. Bankruptcy fire‑sale — NOT PRESENT.
No assignor or assignee in the chain is shown entering Chapter 7/11, and no sale in bankruptcy proceedings appears in the record. The 2009 CityU → IV transfer was a negotiated university divestiture, not a bankruptcy sale.

7. Privateering — NOT PRESENT on this record (and not clearly applicable).
Classic privateering requires an operating company transferring to an NPE to attack its competitors and benefiting from the assertions. Here the pre‑NPE owner was a university (a non‑commercial research institution) that simply sold the asset. I found no evidence of retained economic interest, no SEC disclosure (CityU is not a US public company), and no competitor‑directed arrangement. Not established.

8. Defensive aggregator — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at Longhorn Automotive Group LLC, an active plaintiff, and the patent was in fact the target of a Unified Patents "Patroll" prior‑art bounty (2024) — the opposite of acquisition by a defensive aggregator.

Verdict

NPE — high confidence.

Justification: at least three strong signals are documented on the face of the reel/frame record — (a) a known asserter chain running through Intellectual Ventures (Reels 023915/0101 and 030494/0239) ending at active plaintiff Longhorn Automotive Group LLC (Reel 066911/0261); (b) cascading transfers through three single‑purpose vehicles in ~9 months (Reels 065015/0675 → 065227/0107 → 066911/0261, executed 2023‑09‑25 / 2023‑10‑05 / 2023‑10‑06); and (c) a pre‑litigation transfer, with Longhorn recording title 2024‑03‑26 and suing Nissan on 2024‑05‑31. The only material gap is the correspondent‑of‑record field (signal 3), which I could not retrieve and which, if it shows a single repeat filer across the IV‑Assets‑to‑Longhorn links, would strengthen an already strong call.

Verification link (search by patent number): https://assignment.uspto.gov/patent/index.html — search 7634666; the direct equivalently indexed entry point is https://assignmentcenter.uspto.gov/

Honesty flags

1. Correspondent data = not retrieved. All seven "Correspondent" bullets above are open, not negative findings.
2. Reel/frame values are reproduced from the Google Patents legal‑events record, which mirrors USPTO reels; I did not open the USPTO images to confirm each frame in this session.
3. RPX's "February" date for the IV → AI‑Core transfer conflicts with the recorded 2023‑10‑05/13 date; both are reported, neither reconciled.
4. IPR2014‑00180 claim‑level outcome (what, if anything, was cancelled) remains unverified here and is relevant to what Longhorn actually owns to assert.
5. Term status: the recorded adjusted expiration is 2026‑04‑24, so on today's date the enforceable term has closed; the assignment chain remains the relevant record for ownership and standing history, but live assertion capacity is likely at an end. This does not change the NPE characterization, which rests on the historical transfer pattern.

I'll verify the prior-art citations against live sources, then map each to the claims it could anticipate.

I hit the tool step-limit before I could query USPTO PatentCenter directly, so the analysis below is grounded in (a) the authoritative citation lists in the granted patent text you supplied (Google Patents, https://patents.google.com/patent/[US7634666](/patent/US7634666)/en), and (b) live corroboration for each cited reference from FreePatentsOnline, Justia, uspto.report, Unified Patents, and Google Patents. I flag any conflict rather than normalizing it.

Prior-Art Analysis — US 7,634,666 ("Crypto-engine for cryptographic processing of data")

§102 legal frame used here: a reference can anticipate a claim only if it discloses every limitation of that claim, arranged as claimed, in a single reference. Where a reference teaches only some limitations, I label it a §103 (obviousness) candidate rather than an anticipatory reference — I have not silently promoted §103 art to §102.

Relevant date: the '666 was filed / accorded priority 2003-08-15. All nine examiner-cited references pre-date that date and are therefore available as prior art. (One cited reference, US 7,027,597, issued after the '666 filing but has a 2001 filing date, so it is available as of its earlier effective date.)

Source of the list: the "Patent Citations (9)" and "Non-Patent Citations (1)" fields of the granted patent. Note the patent's own front page also shows a separate "Citations (8)" table that omits US 6,671,709 (a family member of US 6,397,241). Both tables are reproduced faithfully below, with the duplicate flagged.

1. US 4,891,781 A — Modulo arithmetic processor chip

• Full citation: US 4,891,781 A (Omura, Jimmy K.); appl. 07/289,124; priority 1987-03-03 / 1987-03-04; granted 1990-01-02; original assignee Cylink Corporation.
• Date variants: the '666 front page lists priority 1987-03-04 and grant 1990-01-02; Unified Patents shows priority 1987-03-03, application date 1988-12-21, grant date 1990-01-01. Retaining both.
• Description: a processor chip for computing addition, multiplication and exponentiation in GF(p). It has twelve n-bit registers, a full adder that shifts-and-adds data in two registers, a feedback register holding a feedback number derived from the prime modulus p, and modulo means that reduce register contents mod p. Claim 4 covers exponentiation performed as a series of modular multiplications.
• Potential §102 relevance:
  • Claims 3 / 6 (bitwise multiplier + multiplicand + "modulo … for performing modular multiplication … according to the modulo value"): closest of the cited art; the feedback register + modulo-means combination is structurally on point. Still, the reference is bit-serial/register-shift oriented, not a "bitwise segmented multiplier/multiplicand" pair, so I would treat it as a §103 reference rather than a clean anticipation.
  • Claim 1: discloses a modular arithmetic unit, but not the claimed SRAM memory unit (input switch + plurality of SRAM elements + output switches + address controller), not a discrete "sign inversion unit," and not the limitation that the multiplication/addition/sign-inversion outputs are fed back to the arithmetic controller. → §103, not §102.
• Caveat: the '666 specification expressly distinguishes prior modular-multiplication hardware generally; the examiner listed Omura as background, consistent with a §103 role.

2. US 6,230,179 B1 — Finite field multiplier with intrinsic modular reduction

• Full citation: US 6,230,179 B1; appl. 08/997,960; priority 1997-04-18; granted 2001-05-08; assignee of record on the '666 front page = Motorola, Inc. (Unified Patents/other sources list Certicom Corp as original assignee, later Motorola Solutions/BlackBerry). Inventors incl. Vanstone, Vadekar, Lambert, Glaser, Dworkin, Torla.
• Description: a finite-field multiplier with intrinsic modular reduction, comprising an interface unit (1208) that translates an n-bit-wide data path to an m-bit-wide data path, a finite-field data unit with m-bit registers, and a finite-field control unit containing a microsequencer and a finite-state-machine multiplier. A mode-selection signal (Z/F2M) selectively enables finite-field or integer arithmetic on shared hardware.
• Potential §102 relevance:
  • Claim 4 (interface controller with a bus interface for connecting high-frequency internal data with lower-frequency host data; a concatenater/splitter for merging or splitting data width): the n-bit→m-bit interface unit is the closest thing in the cited art to a width-matching/concat-split function; the Z/F2M mode selection is close in spirit to the claim's op-code-driven mode selection. But the reference's interface unit is an internal data-path width translator, not a host/high-frequency domain bridge generating status/interrupt signals, and it does not recite op-code selection of RSA vs. ECC. → §103 candidate for claim 4; not a §102 anticipation.
  • Claims 3 / 6: relevant to modular multiplication by a stored "modulo factor M" with a multiplier register B and multiplicand register A — again §103.
• Cross-check: the '666 specification's own paragraph about an "overflow control unit" mirrors the reference's carry-extension trick (register Cext), i.e., the examiner clearly viewed this as analogous-art background.

3. US 6,397,241 B1 — Multiplier cell and method of computing and US 6,671,709 B2 (same title)

• Full citations:
  • US 6,397,241 B1; appl. 09/215,935; priority 1998-12-17/18; granted 2002-05-27/28; original assignee Motorola, Inc. (current: NXP). Inventors Glaser, Torla.
  • US 6,671,709 B2; same priority 1998-12-18; granted 2003-12-30; assignee Motorola, Inc. — listed in the "Patent Citations (9)" table but omitted from the front-page "Citations (8)" table (a family/duplicate of the '241).
• Description: an integrated cryptographic system with a host interface block and a temporary-storage memory, and an arithmetic processor that computes both RSA and ECC. Multiplication cells have an INT/POLY terminal that selects a C-register for RSA modular exponentiation or ECC elliptic-curve point multiplication. The spec notes memory can support a 4:1 RSA:ECC key-size ratio (e.g., 1024-bit RSA alongside 256-bit ECC).
• Potential §102 relevance — this is the single most structurally on-point pair of references for the '666's independent claims:
  • Claim 1: discloses a crypto circuit with a host interface, a memory, and an arithmetic processor performing modular multiplication of two operands with reduction by a modulus — i.e., a co-processor architecture with a memory unit and multiplication/addition functionality. It does not recite the claim's specific memory-unit internals (input switch + plurality of SRAM elements + output switches + address controller), a distinct sign inversion unit, or feedback of all three arithmetic-unit outputs to the arithmetic controller. → §103 for claim 1; not clean §102.
  • Claim 4: the INT/POLY mode selection between RSA and ECC on shared hardware is materially the same concept as claim 4's "arithmetic unit selecting RSA or [ECC] modes based on the op-code signal," and the host-interface block maps to claim 4's bus interface. The remaining limitations (concat/split unit; cryptographic controller generating status and interrupt signals; outputs fed back to the controller) are not shown. → §103 for claim 4; this reference would be a strong primary reference in an obviousness combination.
• Note: the memory-size ratio discussion (1024-bit RSA / 256-bit ECC in shared memory) is conceptually adjacent to dependent claims 7/9 (memory ≈ 384 bytes; SIU k-size ≈ 64 bits), though it does not state those numbers. §103 only.

4. US 7,277,540 B1 — Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography

• Full citation: US 7,277,540 B1 (Shiba, Kawamura); appl. 09/487,483; filed 2000-01-19; priority 1999-01-20; granted 2007-10-02; assignee Kabushiki Kaisha Toshiba.
• Description: an arithmetic apparatus (disclosed as a coprocessor 1) for long product-sum operations that realizes both an RSA cryptosystem and an elliptic curve cryptosystem using shared hardware. It contains buffers 17X/17Y/17Z/17R, an integer-based multiplier circuit 11, a finite-field GF(2^m) multiplier circuit 12, a selector 13, adder circuits 14/15, a carry holder 16, and a controller unit 5, all communicating over a 32-bit data bus 3 with a memory 2. A second embodiment uses a single switchable multiplier (multiplier circuit 41) controlled by a signal S1 from the controller.
• Potential §102 relevance:
  • Claim 1: discloses, in substance, a co-processor with a memory, a controllable multiplier, an adder, and a controller supporting two asymmetric algorithms — but it does not disclose the claim's SRAM-block memory unit with input/output switches and address controller, a discrete sign inversion unit, or feedback of the three arithmetic-unit outputs to the arithmetic controller. → §103, likely as a primary reference.
  • Claim 4: the controller-selected switching between integer (RSA) and finite-field (ECC) multiply modes (signal S1 / selector 13) is the functional counterpart of the claim's op-code-driven RSA/ECC selection, and the bus/buffer structure is adjacent to the interface controller. Still missing the concat/split unit and status and interrupt generation and the feedback limitation. → §103 for claim 4.
  • Claims 3 / 6: shares a "carry/propagation" and modulo/generic-arithmetic approach to modular multiplication; §103.
• Why it matters: this is the closest prior art on the dual-algorithm shared-hardware concept — the '666's stated core object ("a hardware based crypto-engine … using RCA or ECC algorithms," "resources … shared by the algorithms and reused") reads directly onto Toshiba's stated object ("a crypto processing apparatus capable of realizing both an RSA cryptosystem and elliptic curve cryptosystem").

5. US 7,027,597 B1 — Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits

• Full citation: US 7,027,597 B1 (Stojancic, Tomei, Maddury); appl. 09/955,902; filed 2001-09-18; granted 2006-04-11; assignee Cisco Technologies, Inc. (a related sibling, US 7,027,598 B1, appl. 09/956,732, filed 2001-09-19, same date/assignee.)
• Description: a method and apparatus using two passes of Montgomery's method with a pre-computed constant to implement RSA / Diffie-Hellman / DSA efficiently in an IC. Structural disclosure includes a modular ALU attached to a processor's execution unit, minimal register files, and arrays of multiplier circuits and modular-reduction circuits, optionally using a residue number system (RNS).
• Potential §102 relevance:
  • Claims 2 / 3 (and 5 / 6) — the "register to pre-store the multiplier data," "pair of multiplication elements," and "modulo … for performing modular multiplication … according to the modulo value" limitations: the reference's array multiplier + modular-reduction pair and pre-computed-constant register are conceptually related, and it explicitly invokes Montgomery's method (the same algorithm the '666's PEs implement, per FIG. 6). → best characterized as a §103 reference for the multiplication-unit internals.
  • Claim 1 / Claim 4: no co-processor + interface-controller split with SRAM-block memory unit, no sign-inversion unit, no output-feedback limitation. → §103 at most; background.
  • Because it issued 2006-04-11 (after the '666's 2003-08-15 filing), its effective prior-art date rests on the 2001-09-18 filing; I flag that a §102 analysis must rely on the earlier filing/publication, not the 2006 grant.

6. US 4,316,055 A — Stream/block cipher cryptographic system

• Full citation: US 4,316,055 A; priority 1976-12-30; granted 1982-02-16; assignee International Business Machines Corporation.
• Description: the front page gives only "Stream/block cipher cryptographic system" — a symmetric stream/block cipher cryptographic system. (I was unable to open the full text before the step-limit.)
• Potential §102 relevance: general background only. It is a symmetric cipher system and does not teach modular multiplication, a co-processor arithmetic unit, an SRAM-based memory unit, or RSA/ECC mode selection. It cannot anticipate any of claims 1–11; at most it is cited for the general proposition that cryptographic processing was performed in dedicated hardware. → No §102 anticipation; §103 relevance negligible.

7. US 4,484,301 A — Array multiplier operating in one's complement format

• Full citation: US 4,484,301 A; priority 1981-03-10; granted 1984-11-20; assignee Sperry Corporation.
• Description: an array multiplier that operates in one's-complement format.
• Potential §102 relevance: arms-length background art for multiplication hardware. It is a general-purpose array multiplier and does not disclose bitwise-segmented multiplier/multiplicand pair with a stored modulo, Montgomery modular multiplication, or any crypto-engine architecture. → No §102 anticipation of claims 1–11; marginal §103 support for the "multiplication unit / multiplication element" concept in claims 2/3/5/6.

8. WO 2000/046954 A1 — Method and apparatus for generating encryption stream ciphers

• Full citation: WO 2000/046954 A1; priority 1999-02-08; published 2000-08-10; applicant Qualcomm Incorporated.
• Description: a method and apparatus for generating encryption stream ciphers — again a symmetric stream-cipher context.
• Potential §102 relevance: does not teach public-key modular arithmetic, an SRAM-block modular-arithmetic memory unit, a sign-inversion unit, or op-code-based RSA/ECC selection. → No §102 anticipation of claims 1–11; background only.

9. Non-Patent Citation — Cheng et al., Pseudorandom Generator Based on Clipped Hopfield Neural Network

• Full citation: "Pseudorandom Generator Based on Clipped Hopfield Neural Network," IEEE 1998; Cheng et al. (as listed in the patent's Non-Patent Citations field).
• Description: an IEEE 1998 paper by the same inventor family (Cheng), on a clipped-Hopfield-neural-network pseudorandom generator.
• Potential §102 relevance: concerns a PRNG, not a modular-arithmetic crypto-engine. It is listed as an examiner citation reflecting the inventors' own prior work; it does not disclose any limitation of claims 1–11 and is not an anticipation reference. Interestingly, a Cheng/Neural-Network family patent, US 9,948,460 B2 ("Multivariate cryptography based on clipped Hopfield neural network," City University of Hong Kong, 2018), later cites the '666 — i.e., the art flows the other direction.

Ranked assessment: most relevant prior art for the '666

Bottom line on §102 vs. §103

• No single cited reference appears to anticipate independent claim 1 or claim 4. Each of the four most relevant references (Toshiba, Motorola ×2, Certicom/Motorola, Cylink) discloses parts of the claimed crypto-engine — a co-processor arithmetic unit, a memory, a multiplier, an adder, and (in the Motorola and Toshiba references) RSA/ECC selection — but none appears to disclose all of: (i) the claim‑1 SRAM-block memory unit (input switch + plurality of SRAM elements + output switches + address controller), (ii) a discrete sign-inversion unit, and (iii) the requirement that the outputs of the multiplication, addition and sign-inversion units are fed back to the arithmetic controller — plus, for claim 4, the (iv) concat/split unit and (v) cryptographic controller generating both status and interrupt signals.
• The cited art is therefore best characterized as an obviousness (§103) set, not an anticipation (§102) set — which is consistent with the examiner having assembled it from the modular-multiplication-hardware and dual-RSA/ECC-processor art.
• Narrow dependent claims 3 and 6 (bitwise segmented multiplier + multiplicand + stored modulo) come closest to a §102 read on the Cylink (Omura) and Certicom/Motorola references; I would still expect a §103 finding there rather than a clean §102 hit.

Explicit uncertainty flags

1. I could not run live USPTO PatentCenter full-text searches (tool step-limit reached). Full-text corroboration above comes from FreePatentsOnline, Justia, uspto.report, Unified Patents and Google Patents — all consistent with the patent's own citation lists, but not a PatentCenter primary-source check.
2. IPR2014-00180 (IBM petitioner). Per your earlier section, that IPR was instituted on claims 1–11 and produced a Final Written Decision and a 2018 certificate. The ground references in that IPR may differ from the examiner-cited art listed here; I have not been able to confirm the IPR's specific prior art or the claim-level outcome, so I do not attribute any of the references above to that proceeding.
3. Duplicated family member: US 6,397,241 and US 6,671,709 are the same Motorola disclosure; the patent's front page lists both in "Patent Citations (9)" but only US 6,397,241 in "Citations (8)." Treat them as one reference for anticipation purposes.
4. Date variants (US 4,891,781 priority 1987-03-03 vs -04; US 6,397,241 priority 1998-12-17 vs -18) are reproduced as found; the one-day discrepancies do not affect prior-art status relative to the '666's 2003-08-15 filing.
5. The '666's independent claim 4 recites the literal text "RSA or EGO modes of operation" (per the granted-claim text in the authoritative source). I have not auto-corrected it; where the analysis above refers to RSA/ECC mode selection, that reflects the specification's "RSA or ECC" language, and the literal claim term remains as flagged in the prior section.

I'll research the specific prior art references to build a grounded § 103 analysis. Let me start with the key references.

Let me dig deeper into the specific references — the Matsuzaki patent, the Dworkin reference, the winning Patroll art, and the Toshiba reference.

I hit the research tool limit before I could pin down every reference's exact patent number. Below is the § 103 analysis built on (a) the references listed in the Prior Art section of the US 7,634,666 Google Patents page (the backward "Patent Citations" and the "Non-Patent Citations"), and (b) the two references already litigated in IPR2014‑00180 (Matsuzaki, Dworkin), which the prior sections of this analysis surfaced. I reproduce every identifier literally and flag what I could not confirm.

Obviousness Analysis — US 7,634,666 B2 under 35 U.S.C. § 103

0. Threshold facts that frame the analysis

Analytical consequence: any § 103 theory must do two things IBM failed to do — (1) actually supply the three‑way output‑feedback limitation from a reference whose controller genuinely receives all three arithmetic outputs, and (2) articulate a factually supported reason to combine (KSR/Wyers), not "common sense."

1. The prior‑art inventory (grounded in the page's Prior Art section)

1(a) Backward "Patent Citations" — these ARE candidate prior art

1(b) Non‑Patent Citation

• Cheng et al., "Pseudorandom Generator Based on Clipped Hopfield Neural Network," IEEE 1998 — the inventors' own prior work; not material to the structural claims.

1(c) REFERENCE‑QUALITY WARNING (important, and honest)

The page's "Cited By (4)" (WO2016091166A1, CN106921638A, US9948460B2, CN110113147A) and "Families Citing this family (4)" (US20070101401A1 (2005), US7870399B2 (2006), US9860055B2 (Synopsys, 2006), EP2978158A1 (NXP, 2014)) are forward citations. Their dates (2005–2019) post‑date the '666 priority (2003‑08‑15), so they are NOT prior art to the '666 and cannot be used in a § 103 combination. US9860055 and EP2978158 are relevant only as evidence of the field's trajectory, not as invalidating art. (I flag this because a careless chart would wrongly list them as references.)

1(d) The IPR art (from the litigation record)

• Matsuzaki (Ex. 1008): arithmetic device/co‑processor; memory input/output unit with a bus switch; an address generating unit; control unit 10; Fig. 17 embodiment with multiplier 21, adder 22, sign inverting unit 51. Its adder output feeds back to control unit 10, but "the outputs of multiplier 21 and sign inverting unit 51 are inputs to adder 22, rather than feedback to control unit 10."
• Dworkin (Ex. 1012): a finite‑field/integer arithmetic processor whose Fig. 2 shows "sub‑ALU 18" blocks, with controller 20; per IBM's mapping, the multiplication, addition, and sign‑inversion sub‑ALUs each directly send back their outputs to controller 20. (I could not confirm the exact patent number of this Dworkin reference from the results available; it is a Motorola processor in the same family as US6009450 — "Arithmetic processor for finite field and module integer arithmetic operations," Motorola, Dworkin‑family — but I will not assert a number I did not verify.)

2. PHOSITA

A person having ordinary skill in the art at the 2003 priority date would hold a bachelor's degree in electrical engineering, computer engineering, or computer science, and have roughly 3–5 years of experience designing cryptographic hardware / modular‑arithmetic datapaths (Montgomery multipliers, RSA/ECC co‑processors), or equivalent. This is consistent with the level of skill the IPR2014‑00180 panel credited in taking expert testimony (Dr. Koç) on hardware‑implementation issues. The subject matter — a shared RSA/ECC modular‑arithmetic co‑processor — is, per the Board, "sufficiently complex such that expert testimony is particularly helpful."

3. Element‑by‑element mapping of independent claims 1 and 4

Claim 1

Claim 4 — the added interface‑controller elements

Literal‑text caveat carried forward from the prior section: the granted claim reads "RSA or EGO modes"; the specification says "RSA or ECC." I do not auto‑correct. If "EGO" is read as its ordinary meaning, the limitation is ambiguous and a petitioner may have to construe it; if it is ECC (or a typo), Toshiba's S1‑driven selection reads on it directly. Either way the mode‑selection concept is disclosed.

4. Combinations that render the claims obvious

Combination 1 (PRIMARY): Toshiba US 7,277,540 + Dworkin (Ex. 1012)

Why this is the strongest theory. Toshiba supplies nearly the entire claimed architecture in a single reference: a co‑processor that performs both RSA and ECC, with a memory unit, a controller unit, integer and finite‑field multipliers, adders, an inverse calculator, a host bus interface, and op‑code‑driven RSA/ECC selection. The only element Toshiba does not plainly show in the form claimed is the three‑way direct feedback of multiplier, adder, and sign‑inversion outputs to the arithmetic controller — and Dworkin supplies exactly that.

Motivation to combine (KSR‑supported, and not IBM's bare "common sense"):

1. Explicit design incentive in the primary reference. Toshiba states the object is to avoid needing "two coprocessors" because that "undesirably reduce[s]" IC‑card chip area. A PHOSITA seeking one compact RSA+ECC engine is thus directed to consolidate arithmetic units and their control — precisely what adding Dworkin's centralized controller‑feedback path accomplishes.
2. Common problem, common field, shared operation. Both references address hardware acceleration of public‑key crypto over a shared modular/finite‑field datapath. The '666 specification itself concedes the premise — "the two algorithms share a common operation" (the main basic operation in both RSA and ECC‑over‑GF(p) is modular multiplication). That admission is evidence the consolidation was a recognized design objective, not an invention.
3. Predictable result / known technique. Feeding multiple arithmetic‑unit outputs back to a central control unit (Dworkin) is a conventional control‑path technique; applying it to Toshiba's controller is the "predictable use of prior‑art elements according to known methods," yielding nothing more than the expected simplification of control and reduction of gate count.

Combination 2 (RECORD‑REPAIR): Matsuzaki + Dworkin + Toshiba — done with a supported reason to combine

This is the deliberate fix for the precise defect that defeated IBM. IBM lost not because the art missed the feedback limitation, but because it (a) never showed how/why to modify Matsuzaki to feed three outputs to its controller, and (b) offered only similarity + "common sense" as the reason to combine. A petitioner can neutralize both:

• Supply the missing teaching with a reference whose controller genuinely receives the outputs. Dworkin's sub‑ALU 18 outputs go directly to controller 20 — the exact claimed topology — and Toshiba's architecture independently shows a single controller overseeing multiplier/adder/inverse units in an RSA+ECC engine.
• Plead a concrete reason to combine. Rather than "similar hardware," plead the express Toshiba motivation (single‑IC RSA/ECC consolidation to save chip area) plus Dworkin's own framing of the RSA→EC transition need, and support it with expert testimony (avoid the Wyers trap the Board flagged: "the lack of expert testimony supporting a sufficient reason to combine weighs heavily against Petitioner").
• Address the FWD head‑on. The Board found Matsuzaki's multiplier/sign‑inversion outputs go to the adder, not the controller; any petition must either (i) use Dworkin/Toshiba as the primary reference for the controller‑feedback topology, or (ii) show a specific, articulated modification that reroutes the outputs — an "explain how and why" showing, not an assertion.

Combination 3 (interface‑controller/mode‑selection theory): Toshiba + US6230179 (Motorola) + Dworkin

For claim 4 in particular, this combination maps the interface controller with unusual precision:

• US6230179 supplies the "interface unit (1208) that translates an n bit wide data path to a m bit wide data path" (→ bus interface) and a microsequencer (→ op‑code generator / cryptographic controller).
• The Motorola/Certicom spreading/despreading interface supplies the data‑width merge/split function.
• Dworkin supplies the three‑way output feedback to the controller.
• Toshiba's S1 selector supplies the RSA‑vs‑ECC (op‑code) mode selection.
• Motivation: all three are directed to integrating a narrow host bus with a wide cryptographic datapath and to controlling shared arithmetic resources — the same problem claim 4's interface controller solves.

Note: US6230179, US6397241, and US6671709 were already before the examiner (they appear on the '666 face). A theory built only on them is weak; their value here is as supplemental teaching for narrow sub‑elements, paired with a reference (Toshiba) the examiner did not rely on for the feedback/mode‑selection combination.

5. Dependent claims

6. Rebuttal landscape — weaknesses a defendant must anticipate

1. The FWD is a real obstacle, not a formality. The Board's finding that Matsuzaki/Dworkin do not teach the feedback limitation — and that "merely pointing out similarities … and invoking the words 'common sense' is not a sufficient articulation of a reason to combine" — is directly reusable by the patentee against any recycled theory. A new challenge must bring different or additional art (e.g., a primary reference that natively shows three‑way feedback to the controller) and a factually supported motivation.
2. The examiner already considered most cited references. US4484301, US4891781, US6230179, US6397241, US6671709, US7027597, and US4316055 are all on the face of the patent. Any single‑reference or same‑combinations‑as‑the‑examiner theory invites a § 325(d)/redundancy objection. Toshiba US 7,277,540 appears on the "Similar Documents" list rather than the examiner's citation list — it is the reference with the most untapped teaching.
3. Secondary considerations. None is documented in the record reviewed here; there is no evidence of long‑felt need, unexpected results, or industry praise specific to this architecture. The patent's survival of IPR2014‑00180 is not itself a secondary consideration, but it will be argued as a validity signal — see § 7.
4. "EGO" ambiguity in claim 4. If construed literally and narrowly, the mode‑selection limitation becomes harder to meet; a petitioner should either (a) establish, via prosecution history/certificate of correction, that the operative term is ECC, or (b) rely on the S1‑driven integer‑vs‑finite‑field selection in Toshiba regardless of label.

7. Bottom line for a § 103 challenge

• Claim 1 is the fulcrum and turns entirely on the feedback limitation. The prior‑art combination that best meets it is Toshiba US 7,277,540 + Dworkin (Ex. 1012), with Toshiba supplying the shared RSA/ECC co‑processor architecture, memory/switch/address‑controller, multiplier/adder/inverse units and controller, and Dworkin supplying the three‑way output feedback — motivated by Toshiba's own express desire to consolidate RSA and ECC arithmetic into one low‑area coprocessor and by the shared modular‑multiplication operation that the '666 specification itself concedes.
• Claim 4 additionally turns on the interface controller (bus interface, concatenater/splitter, op‑code generator). US6230179 (bus‑width interface + microsequencer) and the Motorola/Certicom spreading interface, combined with Toshiba's S1 selector, map these elements; the prior PTAB record's Matsuzaki + Dworkin pairing is the weakest leg because Matsuzaki's topology routes multiplier/inverter outputs into the adder rather than the controller.
• Dependent claims 2–3, 5–6 (Montgomery PE pair + FIFO, bitwise segmentation) and 7, 9 (384‑byte / 64‑bit) are, on this record, the weakest candidates for the patentee — they read on digit‑segmented multiplier hardware (Toshiba, US6230179, US6397241/US6671709) and predictable numerical optimization, respectively.
• The decisive procedural lesson from IPR2014‑00180: a proper § 103 case here is won or lost on the reason to combine. IBM's similarity‑plus‑"common sense" theory failed. Any new challenge must anchor motivation in an express statement of purpose (Toshiba's single‑coprocessor area rationale; Dworkin's RSA→EC transition framing) and support it with expert testimony.

8. Honesty flags / open items

1. Exact patent number of "Dworkin" (Ex. 1012) and of the Motorola/Certicom "spreading/despreading" interface reference — I could not confirm these numbers from the available results; I describe their disclosures as surfaced but do not assert identifiers I did not verify.
2. Claim‑level text of the IPR certificate (K1) and the precise FWD conclusion — I rely on the FWD PDF excerpts (Finnegan link) and prior‑section findings (all claims sustained) with high‑but‑not‑absolute confidence.
3. "EGO" vs. "ECC" in claim 4 — unresolved; treated literally per instruction.
4. Forward citations are not prior art — I have explicitly excluded the page's "Cited By" and "Families Citing this family" references (2005–2019) from any combination.
5. Toshiba's § 102(e) status — US 7,277,540 (filed 2000‑01‑19, granted 2007‑10‑02) predates the '666 priority, but its precise pre‑AIA § 102(e) effective date (and any foreign‑priority effect on that date) should be confirmed against the patent's face/continuity before it is relied on as the primary reference.
6. No live web search could be completed for several secondary references (Synopsys US9860055, NXP EP2978158, Unified Patents' winning Patroll submission) after the tool limit; the Patroll winning art (published 2025‑01‑14) remains the most promising non‑duplicative lead for a fresh petition and should be retrieved directly from https://patroll.unifiedpatents.com/contests/v4BnWmDzYWwnHPnbG.