Invalidity dossier
US 6230179
Finite field multiplier with intrinsic modular reduction
Current assignee: Certicom Corp
Added 9/21/2026, 9:33:28 AM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US6230179B1
Title: Finite field multiplier with intrinsic modular reduction
Patent number / application: US6230179B1; application US08/997,960, filed 1997-12-24.
Dates: Prior-art date 1997-04-18; filing date 1997-12-24; granted/publication date 2001-05-08; anticipated expiration 2017-12-24. Legal status listed as "Expired - Lifetime." The source notes this status is an assumption and not a legal conclusion.
Assignee/inventors: Original assignees listed as Certicom Corp and Motorola Inc; current assignees listed as Certicom Corp and Motorola Solutions Inc. Inventors: James Douglas Dworkin, Michael John Torla, P. Michael Glaser, Ashok Vadekar, Robert John Lambert, Scott Alexander Vanstone.
Purpose: The patent concerns a method and apparatus for performing finite field and integer arithmetic. Per the definitions section, the invention "relates to a method and apparatus for performing finite field and integer arithmetic." Finite field arithmetic supports elliptic curve (EC) cryptography, which requires addition, multiplication, squaring, and inversion (plus subtraction when the field is not of characteristic two), and modular operations. The excerpt explains that as users transition from RSA to EC cryptography, there is a need for an arithmetic processor supporting both with little or no performance penalty. Stated objects include an arithmetic processor usable with different field sizes, scalable for increased speed via simultaneous execution of multiple steps, and one that "performs both finite field arithmetic and integer arithmetic and in which both special purpose registers and general purpose registers, and arithmetic circuits, are shared."
Plain-language scope: In the excerpt's own terms, the invention provides shared registers and arithmetic circuits to carry out finite field and integer arithmetic, including modular reduction; a polynomial basis for the finite field hardware is assumed because it resembles the standard radix-power basis.
Source: https://patents.google.com/patent/[US6230179](/patent/US6230179)/en
What the excerpt does not establish: The supplied text is explicitly marked "[Excerpt only; consult the source for omitted text.]" It provides no claims, no detailed description of the multiplier's intrinsic modular reduction, no figures, and no prior-art references. It therefore does not establish the specific claimed scope, claim limitations, embodiments, or how the reduction mechanism operates. It also does not establish litigation, ownership-chain history, validity, or the content of any prior art. Classification codes and reassignment entries appear in the source but are not relied upon here beyond the assignee information stated. No missing facts have been supplied or inferred.
Generated 10/1/2026, 10:02:10 PM
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Litigation summary
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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