US 6108266

I'll search for authoritative information on this specific patent, including any litigation activity.

Let me run targeted searches on litigation and validity challenges for this specific patent number.

Let me verify whether this specific patent appears in any litigation or post-grant proceeding, and check the 2001 certificate of correction.

Summary — U.S. Patent No. 6,108,266

Note on scope of search: I searched for this exact number (6,108,266 / US6108266). I did not find any CAFC 2026 docket (or any active litigation/IPR) involving this patent. The CAFC activity I did find in 2026 involving VLSI Technology LLC (e.g., VLSI Technology LLC v. Intel Corp., No. 2024-1772, Fed. Cir. Apr. 14, 2026) concerns U.S. Patent No. 8,566,836 ("Multi-core System on Chip") — a different patent and a different technology area. I cannot confirm any enforcement history for 6,108,266 from the sources retrieved; treat that as "not found," not as "confirmed never litigated."

Bibliographic data (from the patent text)

Family members: JP 4672116 B2; TW 473736 B; CN 100587839 C; KR 100680519 B1.
U.S. prior art cited on the face: US 5,289,413; US 5,321,661; US 5,920,510.

Abstract (as issued)

A memory using programmable delay circuits to control address buffers. A programmable delay device is provided for each block of a plurality of blocks of the memory device; each block is associated with a bit array storing data for that block. The delay device delays activation of sense amplifiers from the time the block is selected, which corresponds to the duration of the addresses provided to the bit array within the block. Each delay in each block is programmed by a global fuse circuit so that all blocks are programmed to the same delay. After fabrication, all data paths in each block are measured under various voltage and temperature conditions to identify the slowest data path; all programmable delays are then programmed with a corresponding delay. A similar delay device is provided within the clock control circuitry to pulse-width control the clock signal provided to the address buffers, and is programmed by the same global fuse circuit so the delays are essentially the same.

Plain-language overview of the independent claims

Claim 1 (memory apparatus). A memory with: (a) an address buffer that takes an address input, produces a true address output and a complementary address output, and has a control input; (b) a set of fuses that supplies a delay-programming signal; (c) a clock circuit receiving an external clock; (d) a programmable pulse-width circuit driven by the clock output on one input and the fuse-programmed delay signal on another, whose output drives the address buffer's control input; (e) word line drivers turned on by enable signals; (f) sense amplifiers turned on by delayed enable signals; and (g) programmable delay circuits that generate those delayed enable signals from the enable signals, where the programmable delay is the same as the pulse width produced by the pulse-width circuit. The final limitation: when the control input is disabled, the address buffer drives both the true and complementary address outputs to the same logic state — i.e., the "return-to-zero" (RTZ) reset behavior.

Claim 2 (circuit usable in a memory having blocks, each selected by a block-select signal). A circuit comprising: fuses providing a delay-program signal indicating a delay; a clock circuit receiving the external clock that indicates entry into an active cycle; a programmable pulse-width circuit receiving the clock and the delay-program signal and driving the control inputs of the address buffers; programmable delay circuits that are responsive to the block-select signals and whose delay is responsive to the delay-program signal; sense amplifiers enabled by those programmable delay circuits; and word line drivers enabled by the block-select signals.

Claim 3 (dependent on claim 2). Narrows claim 2 by requiring that the programmable pulse-width circuit be programmed to a pulse width equal to the delay of the programmable delay circuits — the tracking/matching relationship between address pulse width and sense-amplifier timing.

Claim 4 (memory apparatus, broader in framing). A memory comprising: an address buffer; a memory array responsive to the address buffer; a first programmable delay circuit coupled to the address buffer; a word line driver coupled to the address buffer and memory array and enabled by an enable signal; a sense amplifier coupled to the memory array and enabled by a delayed enable signal; a second programmable delay circuit that produces the delayed enable signal from the enable signal; and a selection circuit coupled to the first and second programmable delay circuits whose output provides a selection signal indicating a delay (in the specification, the fuse circuit 110 supplying the DC delay code to both delay circuits).

Technology context (from the specification)

The patent addresses return-to-zero (RTZ) schemes used to precharge dynamic sense amplifiers in high-speed SRAM. The two pre-existing approaches are criticized: using the falling edge of the external clock (malfunctions at low duty cycle; wastes power at high duty cycle) and using a self-timed pulse (temperature, voltage, and process dependent, hurting yield or cycle time). The disclosed solution replaces both with a fuse-programmed delay that (i) sets the K_R/W clock pulse width feeding the address buffers (via delay circuit 108) and (ii) sets when the sense amplifiers fire (via delay circuit 122), with both delay circuits sharing the same delay code so the address active window tracks sense-amplifier activation. The illustrated embodiment is an 8 Mb late-write synchronous SRAM at ~333 MHz with 18 address bits.

Uncertainty flags

• The 2001-04-24 certificate of correction appears in the prosecution/legal-events record; I could not retrieve its substance, so the claim text above is the text as published and may have been affected.
• I found no CAFC 2026 (or other) docket, IPR, or district-court complaint naming 6,108,266 in the searches performed. Absence of a hit is not proof of absence.
• The number 6,108,266 does appear in assignment records: a 2017 corrective assignment removed "8108266" and substituted "6108266," and it is listed in Freestyle/NXP security agreements. These are recorded transfers/releases, not litigation.
• Patent term ended (anticipated expiration 2019-10-28), so any future enforcement would be limited to pre-expiration conduct and back damages.

I'll search for litigation involving US patent 6108266. Let me run several targeted searches.

Let me search more specifically for litigation databases and the patent number in quotes.

Known litigation involving U.S. Patent No. 6,108,266

Bottom line: I found no evidence of any litigated case in which U.S. Patent No. 6,108,266 ("Memory utilizing a programmable delay to control address buffers") was asserted as a patent‑in‑suit — i.e., no plaintiff/defendant case identifying the '266 patent in an infringement complaint, and no PTAB proceeding or Federal Circuit appeal in which it was the challenged or asserted patent.

What I checked and what I found

Important caveats on false positives

1. Do not confuse US 6,108,266 with US 8,108,266. The assignment record for the '266 patent contains the literal text: "CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324…" (Reel/Frame 041703/0536, recorded 2017‑02‑01). That language describes the correction of a different, earlier assignment record; it does not indicate litigation over the '266 patent. Note also that the '266 patent family record contains a similarly numbered but distinct patent, US 8,081,026, asserted in the D. Del. VLSI v. Intel case. Neither number is the '266 patent.
2. The '266 patent does appear in a litigation exhibit. A chain‑of‑title/security‑interest exhibit filed in a W.D. Tex. case (CourtListener RECAP, gov.uscourts.txwd.1020109, doc. 24‑13) lists the '266 patent among thousands of properties in collateral/assignment schedules. Inclusion in an assignment or security-interest exhibit attached to a case does not mean the patent was asserted in that case.
3. Patent is expired. Per the Google Patents legal‑status data, the '266 patent had an anticipated expiration of 2019‑10‑28 (maintenance fees paid at years 4, 8 and 12), giving a nominal term ending 2019‑10‑28 (plus any term adjustment). Status is "Expired – Lifetime." This makes current enforcement litigation on this patent essentially foreclosed, and would also bar a currently pending infringement claim.

Case table

Confidence and limitations

• High confidence that no U.S. district court case, ITC action, or PTAB proceeding is publicly indexed with U.S. 6,108,266 as the patent‑in‑suit. All searches constrained to that exact number returned only assignment records, patent‑profile pages (e.g., Patent Leaderboard inventor listings), and USPTO classification indices (e.g., EveryPatent).
• Lower confidence as to non‑U.S. proceedings or unindexed state/foreign actions. I did not retrieve results from the Chinese, Japanese, Korean or Taiwanese counterparts (CN1303102A / CN100587839C; JP4672116B2 / JP2001126486A; KR100680519B1 / KR20010039765A; TW473736B), so I cannot rule out foreign enforcement or invalidation actions on the family members.
• I also did not find evidence of any VLSI Technology LLC–style NPE campaign asserting this specific patent, despite VLSI Technology LLC appearing as current assignee and being an active litigant generally.
• If you require a definitive negative, the authoritative next steps would be a full PACER/Unified Patents docket‑level search on the exact number, plus a Darts‑IP / Orbis / Maxvall foreign litigation check for the family members.

I'll verify the structured data against live sources before drafting.

Proceedings overview

Total AIA trial proceedings on file for US 6,108,266: 0 — zero active, zero with claims invalidated, zero with claims sustained, zero settled, and zero institution denials. There is nothing for a defendant to read: no petition has ever been filed against this patent, so the defensive posture is not "hardened by IPR" and not "shot through with cancellations" — it is untested at the PTAB, and, more decisively, the patent expired on 2019-10-28, which caps any damages theory at zero for a suit filed today.

No proceedings to report

I was asked to list each proceeding most-impactful-first. There are none. I am stating that plainly rather than padding the section, because the absence is the finding.

Basis for the finding — and the limits of my verification:

1. Structured data (canonical): the "PTAB proceedings on file" block states the USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest.
2. Independent web check (2026-09-20): I searched for petitions, decisions, and docket entries tying the patent to IPR/PGR/CBM numbers, and for the patent number in PTAB, district-court, and Federal Circuit materials. Every hit that referenced "6108266" did so in one of three irrelevant contexts: (a) the assignment record (see the flag below), (b) inventor/portfolio listings, and (c) unrelated documents where "6108266" is a serial number, a trademark prior-registration number, or a Brazilian/Dominican filing code. No petition, institution decision, final written decision, or appeal.
3. Litigation context check: in the VLSI Technology LLC v. Intel campaign — the obvious place this patent would have surfaced, since VLSI Technology LLC is the current assignee of record (Google Patents) — the asserted patents were the '373, '759, '357, '522, '552, '025, '983, '485, '187, '672, '419, '130, '269 and others. US 6,108,266 is not among them, and I found no VLSI complaint asserting it. The Intel/OpenSky/PQA IPR cluster (IPR2021-01064, IPR2021-01229, IPR2022-00366, IPR2022-00480, IPR2022-00645, IPR2024-00479) all target other patents in VLSI's portfolio.

Confidence: high for the absence of PTAB proceedings; moderate for the absence of any assertion history, since I could not run a full docket-by-docket search across every district court on a patent this old.

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Flag: a records trap that will trip up a manual search

Anyone pulling the assignment history by hand may "find" an IPR-adjacent patent that isn't this one. The record contains a corrective assignment executed 2015-12-07 and recorded 2017-02-01 (Reel/Frame 041703/0536) whose literal text is:

"CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292."

So US 8,108,266 — a different patent, "Method for supplying an output supply voltage to a power gated circuit..." — sits in the same security-interest reel and is easy to mis-link. Per the operating rule to interpret identifiers literally: these are distinct patents, and no PTAB proceeding exists on 8,108,266 either, so the confusion buys a defendant nothing.

Note also the prosecution-history oddity already flagged in this record: US 6,105,145 ("Sensing circuit and method") shares a reel/frame (009665/0122, 010118/0139) with this patent's chain and appears in the same assignment abstract. Do not treat those reels as evidence of a common priority chain.

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Strategic summary

Claim status: all four claims are UNTESTED — none canceled, none sustained. US 6,108,266 issued on 2000-08-22 with four claims: independent claims 1, 2, and 4, plus claim 3 (which depends from claim 2). Because no IPR, PGR, CBR, reissue, or reexamination proceeding ever touched the patent, every claim retains its original issued scope. There is no narrowing disclaimer, no adverse judgment, and no estoppel-creating PTAB record anywhere in the file. If a demand letter cites this patent, the claims are exactly as issued — but the patent is expired, and that is the whole ballgame (below).

Estoppel landscape: empty, and irrelevant. There is no § 315(e)(2) estoppel against anyone, because there has been no petitioner. That is the only respect in which the absence of PTAB activity helps a defendant: every prior-art ground remains available, in district court or in a fresh IPR, with no § 325(d)/§ 315(e) overlay to work around. Conversely, there is no FWD you can point to as a validity finding, no institution denial whose reasoning you can borrow, and no PTAB claim construction you can cite. Any invalidity case must be built from scratch. The three references cited on the face of the patent — US 5,289,413 (Toshiba), US 5,321,661 (Oki), US 5,920,510 (Hitachi) — plus the family-cited art (JP H03-66094, JP H07-161190, JP H10-149682, JP H11-238381, US 5,808,959, KR 0138208, KR 0157901, KR 100259338) are the starting point, and note that the family includes a European counterpart, EP 1 033 721 B1 (granted 2012-11-14), with divisional EP 1 770 708 — useful for prosecution-history estoppel if a European file was more fully developed than the U.S. one.

Pattern signals: none, and that is diagnostic. No petitioner filed twice (necessarily). Patent owner VLSI Technology LLC — the Fortress-controlled entity that ran a famously aggressive IPR-appeal program in VLSI v. Intel — never had to defend this patent at the PTAB, which strongly suggests it was never asserted in a campaign. Defensive aggregators are absent from the chain: Unified Patents does not appear, and VLSI is a monetization entity, not a defensive one. The chain of title is Motorola → Freescale → NXP → VLSI Technology LLC (2016-08-16, Reel/Frame 039490/0701, corrected at 040014/0173), amid a thicket of security interests and releases through Citibank and Morgan Stanley that were all released by 2019. VLSI acquired a large NXP/Freescale portfolio in 2016; this patent appears to have come along as portfolio ballast rather than a targeted acquisition.

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Recommended next steps

If you are a defendant and a demand letter cites US 6,108,266, lead with expiration, not invalidity — the damages case is over before the merits.

1. The patent expired 2019-10-28. Term is 20 years from the 1999-10-28 filing; the patent's own legal record shows "Anticipated expiration" on 2019-10-28 and legal status "Expired – Lifetime" (Google Patents). Maintenance fees were paid through the 12-year window (2008-01-07 and 2012-02-22), so there was no intervening lapse; the patent ran its full statutory term. The European counterpart EP 1 033 721 lapsed 2019-09-19 after the 20th-year renewal was paid — consistent. There is no injunctive relief available for post-expiration conduct, and no ongoing royalty to negotiate.

2. Run the § 286 math and put it in your first response. 35 U.S.C. § 286 imposes a six-year lookback measured from the filing of the complaint. A complaint filed today, 2026-09-20, reaches back only to 2020-09-20 — which is entirely after the 2019-10-28 expiration date. The recoverable-damages window is empty. Even a complaint filed in, say, 2025 would have reached back only to 2019, capturing at most a few weeks of pre-expiration conduct. This is a dispositive, non-fact-intensive argument; consider a Rule 12 motion rather than litigating validity.

3. Do not reflexively file an IPR. The Board will institute on an expired patent, but the practical return is near zero here, and the § 315(b) one-year clock only starts when you are served with a complaint alleging infringement. If you are served, you have a year — but weigh a petition against the § 286 defense, which is cheaper and cleaner. If you do petition, note that for an expired patent the Board applies Phillips claim construction rather than the Phillips-style framework used for unexpired claims, so build the petition to that standard from the outset.

4. If you need the validity record for some collateral purpose (licensing, indemnity, an acquisition diligence file), the correct answer is that none exists: no FWD, no institution decision, no appeal, and no CAFC docket. Confirm directly against:

   • PTAB E2E (PTACTS) — search by patent number 6108266
   • USPTO Patent Center — full file wrapper and any post-issuance certificates
   • CourtListener — for any district-court or CAFC activity

5. Treat the absence of PTAB activity as weak evidence of strength, not strong evidence. Well-monetized patents attract IPRs; this one apparently never justified the filing fee. That reads as the portfolio owner's own assessment of the asset, not as a hardened patent. But say it that way in a brief — the expiration/§ 286 argument is the one that wins.

One caveat on my own work: the ODP block is authoritative and reports zero, and my independent searches found nothing to contradict it. But because I could not paginate the full PTAB E2E docket system or run a comprehensive multi-district assertion search, I flag this as a verified absence within the sources I could reach rather than a court-admissible negative. Before filing anything, run the PTAB E2E search in step 4 yourself and save the screenshot.

I'll research the assignment chain and asserter history before writing. Let me pull on the key threads in parallel.

Strong leads. Let me drill into the assignment-record correspondents and the VLSI/Fortress ownership structure.

Assignment Record Reconstruction — U.S. Patent No. 6,108,266

Primary sources used: the Google Patents legal-events record for US6108266A (https://patents.google.com/patent/[US6108266](/patent/US6108266)/en), the USPTO Patent Assignment Search (https://assignmentcenter.uspto.gov/ / https://assignment.uspto.gov/patent/index.html), the chain-of-title exhibit filed in VLSI Technology LLC v. Intel Corp., No. 6:19-cv-00254-ADA (W.D. Tex.) (CourtListener RECAP gov.uscourts.txwd.1020109, doc. 24-13), the Intellectual Property Security Agreement dated 2010-04-13 reproduced on Law Insider, and contemporaneous reporting/IAM coverage of the VLSI/Fortress chain.

Important sourcing caveat on correspondents. The Google Patents legal-events feed for the '266 patent does not expose the correspondent of record for each reel/frame. I could confirm the correspondent directly for two reels only — 039490/0701 and 040014/0173 — from the W.D. Tex. chain-of-title exhibit. For the older Motorola/Freescale/Citibank reels I relied on the USPTO "Assignment Abstract of Title" reproduced for a sibling Motorola patent (US 6,101,145) that shares the same bulk reel/frame numbers (these are portfolio-wide recordings covering thousands of properties). Those correspondents are therefore attributed at the reel level, not verified per-patent. I flag each such instance below.

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Inventors

Pattern assessment — no anomaly at filing. All three inventors were Motorola employees and assigned to Motorola in the ordinary course (one assignment instrument, one recording, no side letters visible in the record). This is the standard pre-spin-off Motorola pattern, not the "all inventors departed within 12 months" pattern that sometimes precedes a portfolio fire-sale.

Post-filing movement (weak signal, flagged as low confidence). Third-party aggregator Patent Leaderboard lists William R. Weier with 12 patents at Apple and Glenn E. Starnes with 10 patents at Freescale Semiconductor, which is consistent with the inventors dispersing when Motorola's Semiconductor Products Sector became Freescale in 2004 — but I could not verify individual departure dates or employment continuity from any primary source, so I do not treat inventor mobility as a finding here.

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Original assignee

Motorola, Inc. (1303 East Algonquin Road, Schaumburg, Illinois 60196) — the entity named on the issued patent and the assignee on reel 010353/0334.

• Line of business / product. Motorola was a diversified operating company; the patent arose in its Semiconductor Products Sector, and the specification describes an 8 Mb late-write synchronous SRAM operated at ~333 MHz — i.e., a commercial memory product family, not a paper design. Caveat: I have not verified a specific orderable part number embodying the claims, so "shipped a product embodying the claims" is supported by the specification's product framing but not independently confirmed to part-number level.
• Current status. Motorola, Inc. no longer exists as such. The semiconductor business was spun off as Freescale Semiconductor, Inc. in April 2004 (reel 015698/0657). Motorola itself split in 2011 into Motorola Mobility (later Google 2012 → Lenovo 2014) and Motorola Solutions. Freescale was acquired by NXP Semiconductors in 2015 (announced March 2015, closed December 2015) — a merger, not a bankruptcy. Freescale/NXP sold ~200 of these semiconductor patents to Fortress-controlled VLSI Technology LLC beginning in August 2016.

Chain-of-title summary: Motorola → Freescale (2004 spin-off) → VLSI Technology LLC (2016, Fortress/SoftBank-backed NPE), with the intermediate Citibank/Morgan Stanley entries being security interests, not ownership transfers.

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Assignment timeline

Reel/frame numbers and dates below are as recorded in the USPTO legal-events feed for US 6,108,266. Events marked (security mechanics) are collateral/pledge and release recordings — they are part of the record but are not transfers of title. Non-assignment entries (grant, certificate of correction, maintenance fees) are omitted from the numbered list and noted separately at the end.

1. 1999-10-19 (executed) / recorded 1999-10-28 — Reel 010353/0334

• Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST)
• Assignor: Weier, William Robert; Chang, Ray; Starnes, Glenn
• Assignee: Motorola, Inc. (Schaumburg, IL)
• Correspondent: not retrieved for this reel. Motorola's in-house IP department handled its contemporaneous filings (sibling-patent records show Motorola I.P. Dept., Suite R3108, P.O. Box 10219, Scottsdale, AZ — attn. Sharon K. Coleman / Anthony M. Martinez). Reel-level attribution, not per-patent verified.
• Context: initial inventor-to-employer assignment.

2. 2004-04-04 (executed) / recorded 2004-05-07 — Reel 015698/0657

• Conveyance: Assignment
• Assignor: Motorola, Inc.
• Assignee: Freescale Semiconductor, Inc. (6501 William Cannon Drive West, Austin, TX 78735)
• Correspondent: Freescale Semiconductor, Inc., attn. Jennifer B. Wuamett, 7700 W. Parmer Lane, MD:TX32/PL02, Austin, TX 78729 (sibling-patent record for the same reel; reel-level attribution).
• Context: internal corporate spin-off — the April 2004 Motorola Semiconductor Products Sector → Freescale separation, executed in bulk across the portfolio.

3. 2006-12-01 (executed) / recorded 2007-02-02 — Reel 018855/0129 (security mechanics)

• Conveyance: Security Agreement
• Assignor: Freescale Semiconductor, Inc. and affiliated Freescale entities
• Assignee: Citibank, N.A., as Collateral Agent (New York)
• Correspondent: not retrieved for this reel.
• Context: securitization — Freescale's 2006 LBO-era collateral pledge of substantially its entire IP portfolio.

4. 2010-04-13 (executed) / recorded 2010-05-13 — Reel 024397/0001 (security mechanics)

• Conveyance: Security Agreement
• Assignor: Freescale Semiconductor, Inc.
• Assignee: Citibank, N.A., as Collateral Agent
• Correspondent: not retrieved.
• Context: securitization / refinancing pledge. This is the agreement in which the '266 patent is expressly listed by patent number, application 09/428,440, and title in the property schedule, so the '266's inclusion in this lien is directly documented (not reel-level inference).

5. 2013-05-21 (executed) / recorded 2013-06-18 — Reel 030633/0424 (security mechanics)

• Conveyance: Security Agreement
• Assignor: Freescale Semiconductor, Inc.
• Assignee: Citibank, N.A., as Notes Collateral Agent
• Correspondent: not retrieved.
• Context: securitization — 2013 notes-collateral repledge.

6. 2013-11-01 (executed) / recorded 2013-11-06 — Reel 031591/0266 (security mechanics)

• Conveyance: Security Agreement
• Assignor: Freescale Semiconductor, Inc.
• Assignee: Citibank, N.A., as Notes Collateral Agent
• Correspondent: CPA Global Limited, Liberation House, Castle Street, St Helier, JE1 1BL, Jersey (sibling-patent record for the same reel; reel-level attribution). CPA Global is a large IP-management/annuity service vendor, not an NPE attorney — appears here as the recording house for the collateral agent.
• Context: securitization.

7. 2015-12-07 (executed) / recorded 2015-12-21 — Reels 037354/0225; 037356/0553; 037356/0143 (security mechanics)

• Conveyance: Patent Release
• Assignor: Citibank, N.A. (as collateral agent) → Assignee: Freescale Semiconductor, Inc.
• Correspondent (037356/0143): IP Research Plus, Inc., 21 Tadcaster Circle, attn. Penelope J.A. Agodoa, Waldorf, MD 20602 (sibling-patent record for the same reel; reel-level attribution).
• Context: release of the Citibank liens in connection with the Freescale/NXP transaction; three parallel releases recorded the same day across different security agreements.

8. 2015-12-07 (executed) / recorded 2016-01-12 — Reel 037486/0517 (security mechanics)

• Conveyance: Assignment and Assumption of Security Interest
• Assignor: Citibank, N.A. → Assignee: Morgan Stanley Senior Funding, Inc. (Maryland)
• Correspondent: not retrieved.
• Context: securitization — collateral-agent succession.

9. 2015-12-07 (executed) / recorded 2016-01-13 — Reel 037518/0292 (security mechanics)

• Conveyance: Assignment and Assumption of Security Interest
• Assignor: Citibank, N.A. → Assignee: Morgan Stanley Senior Funding, Inc.
• Correspondent: not retrieved.
• Context: securitization — collateral-agent succession. (This is the reel later corrected by reel 041703/0536; see item 15.)

10. 2016-05-25 (executed) / recorded 2016-06-16 — Reel 039138/0001 (security mechanics)

• Conveyance: Supplement to the Security Agreement
• Assignor: Freescale Semiconductor, Inc. → Assignee: Morgan Stanley Senior Funding, Inc.
• Context: securitization maintenance.

11. 2016-07-12 (executed) / recorded 2016-07-22 — Reel 039428/0845 (security mechanics)

• Conveyance: Patent Release (Release by Secured Party)
• Assignor: Morgan Stanley Senior Funding, Inc. → Assignee: NXP B.V.
• Context: release of security interest — clearing liens ahead of the NXP/Freescale IP sale to VLSI.

12. 2015-12-07 (executed) / recorded 2016-08-08 — Reel 039610/0020 (security mechanics)

• Conveyance: Assignment and Assumption of Security Interest
• Assignor: Citibank, N.A. → Assignee: Morgan Stanley Senior Funding, Inc.
• Context: securitization — collateral-agent succession.

13. 2016-08-16 (executed) / recorded 2016-08-19 — Reel 039490/0701 ⚠️ the title transfer

• Conveyance: Assignment of Assignors' Interest (ASSIGNMENT OF ASSIGNORS' INTEREST (SEE DOCUMENT FOR DETAILS))
• Assignor: Freescale Semiconductor, Inc.
• Assignee: VLSI Technology LLC, 1209 Orange Street, Corporation Trust Center, Wilmington, Delaware 19801
• Correspondent: Eric Scheuerlein, The Mueller Law Office, P.C., 12707 High Bluff Drive, Suite 200, San Diego, CA 92130 — directly confirmed from the W.D. Tex. chain-of-title exhibit for this reel.
• Recording scope: 22 properties, 6 pages.
• Context: transfer-to-asserter. This is the operative conveyance of the '266 out of operating-company hands into a Fortress Investment Group (SoftBank) controlled Delaware LLC. Fortress IP head Eran Zur is the authorized signatory on VLSI's acquisition assignments (per IAM/Lexology reporting), and VLSI's only business is patent assertion. Repeat-correspondent note: The Mueller Law Office also files the corrective recording immediately below.

14. 2016-08-16 (executed) / recorded 2016-09-13 — Reel 040014/0173

• Conveyance: Corrective Assignment — "to correct the signature page previously recorded at reel 039490 frame 0701"
• Assignor: Freescale Semiconductor, Inc. → Assignee: VLSI Technology LLC
• Correspondent: Eric Scheuerlein, The Mueller Law Office, P.C., 12707 High Bluff Drive, Suite 200, San Diego, CA 92130 — directly confirmed.
• Context: correction of the VLSI acquisition record (same parties, same date, same counsel — the same attorney appears on consecutive links of the chain).

15. 2015-12-07 (executed) / recorded 2017-02-01 — Reel 041703/0536 (security mechanics)

• Conveyance: Corrective Assignment — "TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292"
• Assignor: Citibank, N.A. → Assignee: Morgan Stanley Senior Funding, Inc.
• Correspondent: Penelope J.A. Agodoa / IP Research Plus, Inc., 21 Tadcaster Circle, Waldorf, MD 20602 (shown on the face of the W.D. Tex. chain-of-title exhibit alongside this reel). Repeat-correspondent note: the same recording agent appears on the 2015-12-21 release reel 037356/0143 — i.e., the same foreign/back-office filer across multiple links.
• Context: correction of a bulk securitization record. This is the entry that makes US 6,108,266 (and separately US 8,062,324) explicit in the file — and it is also the source of the commonly circulated "6,108,266 vs 8,108,266" confusion. It is a title-cleaning correction, not a new transfer.

16. 2016-09-12 (executed) / recorded 2016-09-21 — Reel 040925/0001 (security mechanics)

• Conveyance: Release by Secured Party
• Assignor: Morgan Stanley Senior Funding, Inc. → Assignee: NXP, B.V. f/k/a Freescale Semiconductor, Inc.
• Context: release of security interest.

17. 2016-06-22 (executed) / recorded 2016-11-07 — Reel 040928/0001 (security mechanics)

• Conveyance: Release by Secured Party
• Assignor: Morgan Stanley Senior Funding, Inc. → Assignee: NXP B.V.
• Context: release of security interest.

18. 2017-05-02 (executed) / recorded 2017-05-29 — Reel 042610/0451 (security mechanics)

• Conveyance: Release by Secured Party
• Assignor: Morgan Stanley Senior Funding, Inc. → Assignee: NXP USA, Inc. f/k/a Freescale Semiconductor, Inc.
• Context: release of security interest.

19. 2019-02-17 (executed) / recorded 2019-02-20 — Reel 048734/0001 (security mechanics) — ⚠️ uncertain linkage

• Conveyance: Corrective Assignment — "TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290…" (a different application number, not this patent)
• Assignor: Morgan Stanley Senior Funding, Inc.
• Correspondent: not retrieved.
• Context: appears in this patent's legal-events feed, but the corrective text concerns an unrelated application number. I cannot confirm the '266 patent is actually a property in this recording. Treat as record noise/entanglement rather than a transfer affecting the '266.

20. 2019-09-03 (executed) / recorded 2019-09-10 — Reel 050744/0097 (security mechanics)

• Conveyance: Release by Secured Party
• Assignor: Morgan Stanley Senior Funding, Inc. → Assignee: NXP B.V.
• Context: release of security interest.

21. 2015-12-07 (executed) / recorded 2019-12-10 — Reel 053547/0421 (security mechanics)

• Conveyance: Corrective Assignment — "REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935" (again, an unrelated application number)
• Assignor: Citibank, N.A. → Assignee: Morgan Stanley Senior Funding, Inc.
• Context: back-office cleanup of the 2015 collateral-agent succession. Note the four-year lag between execution (2015) and recording (2019), and the fact that the corrected numbers are not this patent.

22. 2016-06-22 (executed) / recorded 2020-01-17 — Reel 052915/0001 (security mechanics)

• Conveyance: Corrective Assignment (Release of Security Interest)
• Assignor: Morgan Stanley Senior Funding, Inc. → Assignee: NXP B.V.
• Context: cleanup.

23. 2016-09-12 (executed) / recorded 2020-02-17 — Reel 052917/0001 (security mechanics)

• Conveyance: Corrective Assignment (Release of Security Interest)
• Assignor: Morgan Stanley Senior Funding, Inc. → Assignee: NXP, B.V. f/k/a Freescale Semiconductor, Inc.
• Context: cleanup.

Non-assignment record entries (for completeness): patent grant 2000-08-03; certificate of correction recorded 2001-04-24 (contents not retrievable — flagging, consistent with the earlier-generated summary); maintenance fees paid 2004-01-29 (yr 4), 2008-01-07 (yr 8), 2012-02-22 (yr 12); anticipated expiration 2019-10-28, status "Expired – Lifetime."

Does Assignment Center have records for this patent? Yes — the record is extensive (23 recorded events, 25 reel/frame citations). The chain is not a "no post-issuance assignments — original assignee still owns it" case.

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Timeline diagram

timeline
    title Ownership of US 6108266
    1999 : Filed by Motorola Inc
         : Inventors assign rights to Motorola
    2000 : Patent issued
    2001 : Certificate of correction recorded
    2004 : Spun off to Freescale Semiconductor
    2006 : Pledged as Citibank collateral
    2010 : Re pledged to Citibank
    2013 : Pledged to Citibank Notes Agent
    2015 : Security interests released
         : Morgan Stanley takes collateral role
    2016 : Freescale assigns to VLSI Technology LLC
         : Corrective recording by Mueller Law Office
         : NXP and Morgan Stanley releases
    2017 : Morgan Stanley corrective recording
    2019 : Patent expires

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NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
The '266 leaves operating-company hands at reel 039490/0701, executed 2016-08-16, recorded 2016-08-19, from Freescale Semiconductor, Inc. to VLSI Technology LLC. Concrete tells, not name-based: (a) assignee address is 1209 Orange Street, Corporation Trust Center, Wilmington, DE 19801 — the CT Corporation registered-agent address, i.e., no operating presence; (b) assignee is a single-purpose Delaware LLC; (c) assignee makes no products — Intel established at trial that VLSI "does not conduct research, does not make products, does not sell products and has no patents of its own," and VLSI is described in a subsequent Delaware Chancery pleading as "a Delaware limited liability company and a non-practicing entity"; (d) the acquisition was funded and directed through Fortress Investment Group (SoftBank) with Fortress IP head Eran Zur signing VLSI's acquisition assignments.

2. Known asserter in the chain — PRESENT.
The current assignee, VLSI Technology LLC, is not one of the legacy names on the list you supplied (Acacia, Marathon, IV, Wi-LAN/Mosaid, Vringo, Pendrell, Round Rock, etc.), but it is an established, publicly documented high-frequency asserter: VLSI filed at least seven infringement suits against Intel since 2017, plus actions against Apple, HTC and ZTE through affiliated Fortress vehicles; Fortress itself is named in Unified Patents' filings as an entity Unified "has been adverse to" and is described there as an aggregator "extending the PAE model." RPX and Unified both track the VLSI/Fortress campaign. Note also the chain's collateral lineage overlaps the Inventory/Inventergy Fortress lending relationships reported by IAM.

3. Repeat correspondent across the chain — PRESENT (two distinct repeat filers).

• Eric Scheuerlein, The Mueller Law Office, P.C., 12707 High Bluff Drive, Suite 200, San Diego, CA 92130 appears on both the acquisition (039490/0701) and its corrective (040014/0173) — a directly confirmed recurrence across two consecutive links, on the exact transfers that moved the '266 to VLSI.
• Penelope J.A. Agodoa / IP Research Plus, Inc., 21 Tadcaster Circle, Waldorf, MD 20602 recurs on the Freescale/NXP/Citibank/Morgan Stanley securitization links — seen on 037356/0143 (2015-12-21 release) and on 041703/0536 (2017-02-01 corrective). Reel-level attribution for the first; face-of-document for the second.
• CPA Global Limited, St Helier, Jersey appears as recording agent on 031591/0266. (Vendor, not an NPE lawyer — noted for completeness.)

4. Cascading transfers — PRESENT.
Between 2015-12-07 and 2016-08-19 (≈8.5 months) the '266 record shows a rapid series of recorded events — releases from Citibank (037354/0225, 037356/0553, 037356/0143), two assignment-and-assumptions to Morgan Stanley (037486/0517, 037518/0292), an NXP release (039428/0845), a further Morgan Stanley recording (039610/0020), then the title transfer to VLSI (039490/0701) and its same-day corrective (040014/0173) — with a common correspondent cluster (IP Research Plus on the securitization side; The Mueller Law Office on the VLSI side). Caveat: most of these are security-interest mechanics rather than successive ownership changes, so the "chain of LLCs" flavor is weaker than the raw event count suggests.

5. Pre-litigation transfer — NOT PRESENT (for this patent).
The transfer to VLSI executed 2016-08-16. VLSI's first Intel complaint was filed 2017-10-02 (N.D. Cal.) — roughly 13.5 months later, outside the 6-month window. More importantly, I found no complaint, ITC action, or PTAB proceeding in which US 6,108,266 is the patent-in-suit, consistent with the earlier-generated litigation summary. The '266 appears in a VLSI chain-of-title exhibit (W.D. Tex. 6:19-cv-00254), which is not an assertion.

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7/11 proceeding appears in the chain. The Freescale→NXP step was a ~$11.8–12B merger/acquisition, and the NXP/Freescale→VLSI step was a negotiated portfolio sale (~200 patents) to a Fortress vehicle — not a court-supervised asset sale.

7. Privateering — PRESENT (portfolio-level; not patent-level).
The operative structure is the classic one: an operating company (Freescale/NXP) conveyed a semiconductor patent portfolio to a Fortress/SoftBank-controlled NPE (VLSI Technology LLC), which then asserted those patents against a competitor (Intel). Corroboration: Intel's Delaware Chancery action Intel Corp. v. Fortress Investment Group LLC, No. 2021-0021-MTZ, and Intel's SEC disclosures describing VLSI as an entity "formed by a hedge fund for the sole purpose of buying patents to assert against Intel." Caveat: the '266 patent specifically is not among the patents I could confirm as asserted, and the record does not show NXP directing the campaign (indeed Intel litigated whether it was licensed via NXP).

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain terminates at VLSI Technology LLC, an asserting entity. There is no RPX, AST, LOT Network, Unified Patents, or OIN acquisition in the record. The patent has not been neutralized.

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Verdict

NPE — high confidence.

The '266 was transferred out of operating-company hands at reel 039490/0701 (executed 2016-08-16, recorded 2016-08-19) from Freescale Semiconductor, Inc. to VLSI Technology LLC, a single-purpose Delaware LLC at CT Corporation's registered-agent address (1209 Orange Street, Wilmington, DE 19801) that makes no products and whose only business is assertion — a Fortress Investment Group/SoftBank vehicle whose IP head, Eran Zur, signed its acquisition assignments. Two independently strong signals are present (shell-entity transfer; known asserter / privateering), reinforced by a repeat correspondent across the acquisition and its corrective (Eric Scheuerlein, The Mueller Law Office) and a repeat recording agent across the securitization links (Penelope J.A. Agodoa, IP Research Plus). The two "not present" signals are nevertheless notable: there was no §6-month pre-litigation transfer for this patent, and no identified suit, IPR, or ITC action naming US 6,108,266 — so the NPE characterization attaches to the chain and current owner, not to proven enforcement of this particular patent. It is now expired (anticipated expiration 2019-10-28, "Expired – Lifetime"), so any residual enforcement value is limited to pre-expiration conduct.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 6108266) and https://assignment.uspto.gov/patent/index.html.

I'll search for the specific patent and its cited prior art references.

Let me gather more detail on the cited references and the prosecution record, including the certificate of correction.

USPTO record for U.S. Patent No. 6,108,266 — confirmed

Searching the exact number 6,108,266 (not 8,108,266) returns the record below. I did not auto-correct any identifier; the near-number 8,108,266 is a different patent and is excluded from this analysis (that near-number does appear in the '266 file's assignment-correction text, but it is not the patent at issue).

Prosecution caveat: The legal‑events record shows a Certificate of Correction dated 2001‑04‑24. I could not retrieve the contents of that certificate, so the claim text quoted in the previous sections (and used below) is the text as published. (Note: one search surfaced a Certificate of Correction for an unrelated patent, 8,580,264 — that is a false positive and has nothing to do with the '266 patent.)

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The prior-art citations on the face of U.S. 6,108,266

The patent lists three U.S. patent citations. There are no foreign patent citations and no non-patent literature on the face (the "Family Cites Families" items are family-member citations, not examiner citations against the '266 claims).

Statutory categories (pre‑AIA; the '266 application was filed 1999‑10‑28):

• US 5,289,413 and US 5,321,661 issued in 1994 — more than one year before 1999‑10‑28 → available as § 102(b) art.
• US 5,920,510 issued 1999‑07‑06, less than one year before the '266 filing date (Oct. 28, 1998 is the § 102(b) cutoff), and its underlying application was filed 1997‑09‑19 → available as § 102(a) and § 102(e) art, but not § 102(b).

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Per-reference analysis and § 102 anticipation

Framing note (MPEP 2131): Anticipation requires a single reference disclosing every claimed element arranged as in the claim. All four claims of the '266 patent are combination claims, so each reference must be assessed against the whole claim. My conclusion up front: none of the three cited references anticipates any of claims 1–4; they are background/§ 103‑type references. The mapping below shows what each reference actually discloses against the claim language.

Reference 1 — U.S. 5,289,413 (Tsuchida et al., Toshiba)

• What it discloses: A MOS/DRAM with word lines, folded bit‑line pairs, a sense amplifier and transfer gate per bit‑line pair, a column decoder whose outputs are connected via column‑select lines so that selecting one column preactivates an adjacent column before the corresponding column address arrives, latch registers that capture four bits in parallel, and a multiplexer that serially reads them out. The stated purpose is "improving the serial accessing speed" (page/ n***ibble/static‑column and serial modes), and it also discusses spare‑column replacement (claimed in claims 3–13 of the reference).
• Claim mapping: It does disclose a memory with sense amplifiers (relevance to claim 1/2 element "sense amplifiers enabled in response to …") and row/column decoders. It does not disclose: address buffers producing true and complementary address outputs that return to the same logic state (RTZ); a fuse‑programmed delay program signal; a programmable pulse‑width circuit driving an address‑buffer control input; programmable delay circuits that delay sense‑amp enable signals by an amount equal to the address pulse width; nor the "selection circuit … selection signal which indicates a delay" of claim 4.
• § 102 conclusion: Does not anticipate any of claims 1, 2, 3, or 4. No single‑reference disclosure of the RTZ/pulse‑width‑tracking combination. Its citation role is background on memory architecture and dynamic sensing.

Reference 2 — U.S. 5,321,661 (Oki Electric)

• What it discloses: A self‑refreshing (pseudo‑/virtual‑static) memory with a built‑in refresh timer, refresh controller, refresh address counter, and a refresh test circuit. Notable elements: an inverting delay line whose input and output are combined by a logic circuit "to generate a signal for resetting said address counter" (claim 12); a fuse‑programmable register for a pass value (claim 14; fuse cells R0…Rn each with a transistor, inverter, and fuse blown after fabrication); a test controller that disables/re‑enables the timer; and outputs including a serial data signal or pass/fail signal. The disclosure expressly notes the timer can be "fuse‑programmable … so that the timer can be adjusted after the chip is completed."
• Claim mapping: It discloses fuse‑programmable circuitry (relevance to claim 1/2 "a plurality of fuses for providing a delay program signal" and claim 4 "selection circuit … output … indicates a delay") and a delay line feeding a reset‑generating logic circuit (superficially resembling the delay→reset path in the '266 K‑control circuit 106/delay 108). It does not disclose: an address buffer with true/complement RTZ outputs; coupling a programmable pulse‑width circuit output to an address‑buffer control input; a programmable delay that times sense‑amplifier enablement to match the address pulse width; or word line drivers enabled by enable signals with sense amps enabled by delayed enable signals.
• § 102 conclusion: Does not anticipate any of claims 1, 2, 3, or 4. Best characterized as § 103‑type art on fuse‑programmable timing and self‑timed delay/reset generation.

Reference 3 — U.S. 5,920,510 (Yukutake et al., Hitachi) — closest reference

• What it discloses: A synchronous SRAM (and a system using it) in which an external address ADD is captured into an address latch 22 by a level latch whose through/latch state is controlled by an on‑chip pulse generation circuit 30. The pulse generation circuit sets the signal‑holding period "to a desired timing," and because the period is set in the chip, the device operates "independent of the duty ratio of [the] clock signal" — i.e., precisely the problem the '266 patent identifies with external‑clock‑edge RTZ. The reference's claims further recite that the holding period "can be selected by a program circuit or fuse circuit" (claim 9), that the external signal is an address signal (claim 15), and the device is an SRAM (claim 14). It also describes PLL/DLL/synchronous‑mirror‑delay variants and constant‑current delay stages for controlling dispersion.
• Claim mapping against claim 1:

• § 102 conclusion: Does not anticipate claims 1, 2, 3, or 4 — it is missing the RTZ behavior, the sense‑amplifier delayed‑enable path, and the pulse‑width/delay matching limitation (claim 3). However, it is the most relevant reference in the file: it is the closest art to the "programmable pulse‑width circuit … receiving the delay program signal … output coupled to the control input of the address buffer" element of claim 1 (and the analogous element in claims 2 and 4), and to the underlying motivation ("not dependent upon external clock specifications"). Expect it to be used as a primary § 103 reference, not as an anticipatory § 102 reference.

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Bottom line on prior art for U.S. 6,108,266

1. Only three U.S. patent citations appear on the face, mapped above: US 5,289,413; US 5,321,661; US 5,920,510.
2. No single cited reference anticipates any claim. US 5,920,510 is the closest and discloses the fuse‑programmable on‑chip pulse‑width/delay generation coupled to an address latch, but it lacks the (a) true/complement RTZ address‑buffer behavior, (b) delayed sense‑amplifier enable path from programmable delay circuits, and (c) the pulse‑width‑equals‑delay matching of claim 3.
3. The two 1994 references (Toshiba '413, Oki '661) read as background art — memory architecture/dynamic sensing and fuse‑programmable/self‑timed delay with reset generation, respectively — rather than § 102 anticipatory art.

Caveats and limitations (please read)

• I could not retrieve the 2001‑04‑24 Certificate of Correction, nor a PTO‑892/Notice of References for the '266 file; the prior‑art list and claim text above are as published, and the certificate may have altered claim wording.
• I did not retrieve the prosecution file wrapper (Office actions/rejections) for 09/428,440, so I cannot state which of the three references the examiner relied on for any specific rejection, or whether any reference was applied under § 102 versus § 103. My § 102 assessments are based on the references' own disclosures.
• Foreign/family art is outside this analysis. I did not retrieve the family members' search reports: JP 4672116 B2 / JP 2001126486 A; CN 1303102 A / CN 100587839 C; KR 100680519 B1 / KR 20010039765 A; TW 473736 B. A parallel search report (e.g., the JP or CN counterpart) could identify additional prior art not on the U.S. face.
• For completeness: a related Motorola/Chang disclosure, EP 1 033 721 A3 "Programmable delay control in a memory" (priority US 259,454, Mar. 1, 1999), and the similar document US 6,111,796 ("Programmable delay control for sense amplifiers in a memory") discuss the same assignee's programmable‑delay/sense‑amplifier‑timing theme. These are not cited prior art against the '266 claims (US 6,111,796 issued after the '266 filing), so they are context only.

If you want a definitive § 102/§ 103 position, the next step is to pull the full prosecution history for application 09/428,440 (the Office actions and the PTO‑892), plus the JP/CN counterpart search reports, from USPTO Patent Center / Global Dossier.

I'll ground this analysis in the actual prior-art references cited on the face of US 6,108,266 and in its family/"similar documents" record, since the task directs me to use the Prior Art section. Let me pull bibliographic and disclosure details on the key references.

The most probative hits so far are US 5,808,959 (delayed sense-amp control in a synchronous SRAM) and US 5,920,510 (pulse-width-independent signal holding with fuse-programmable delay). Let me also pull the "Similar Documents" that look like near-analogous art — US 6,111,796; US 5,978,286; US 6,141,272 — and the NEC/Japanese family citations.

Obviousness Analysis — U.S. Patent No. 6,108,266 under 35 U.S.C. § 103

Scope note. I use the prior-art material of record on the patent page: the examiner-cited references (US 5,289,413; US 5,321,661; US 5,920,510), the references cited in the family's foreign counterparts ("Family Cites Families"), the "Similar Documents" record, and the sibling Motorola filings surfaced there. Claim elements are those charted in the earlier sections; I do not repeat that mapping except where the obviousness analysis turns on it.

Governing framework. Application 09/428,440 was filed 1999-10-28, so pre-AIA § 103 applies (Graham v. John Deere), as construed by KSR Int'l v. Teleflex (487 F.3d 1315 (2007)) and MPEP 2143/2144. Because the patent expired 2019-10-28, any § 103 holding would arise in a back-damages/invalidity posture rather than in prospective enforcement. Also carried forward from the earlier sections: the 2001-04-24 certificate of correction (Reel/Frame not retrieved) may have altered claim text; if so, every mapping below must be re-run against the corrected claims.

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1. Prior-art inventory and § 102 status

The examiner of record considered only three references (US 5,289,413; US 5,321,661; US 5,920,510). US 5,808,959 / US 5,872,742 and the Japanese family-cited art do not appear in the "Patent Citations" of-record list — i.e., they were not before the U.S. examiner and would be fully available in an IPR or § 282 invalidity defense.

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2. Disclosure-to-element mapping

Result: every limitation except the literal RTZ "same-state output" limitation is expressly disclosed in the combination US 5,920,510 + US 5,808,959/US 5,872,742 + US 6,111,796 + US 5,321,661, and the RTZ limitation is the applicant's own admitted prior art.

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3. The combinations and the motivation to combine

Combination A — the core one (claims 1, 2, 4)

US 5,920,510 (or JP H10-149682) + US 5,808,959 / US 5,872,742 + US 5,321,661 + US 6,111,796.

Motivations, each tied to a specific source:

1. The references themselves state the same problem in the same terms as the '266 patent. The '266 background attacks (i) reliance on the external clock's falling edge (low-duty-cycle failure / high-duty-cycle power waste) and (ii) self-timed pulses that vary with temperature, voltage, and process. US 5,920,510 is directed to exactly that: "operations are performed in a stable manner without having to depend upon the pulse width of an external clock," and it locates the fix in an on-chip pulse generator whose period is fuse/program-circuit selectable after the chip is completed. That is the '266's stated inventive concept, in a synchronous-SRAM context, one year before the '266 filing date. This is the strongest possible "the references point to the combination" rationale (MPEP 2144.1(f)).
2. A predictable, mechanical substitution. Replacing the external-clock falling edge as the RTZ reset event with a fuse-trimmed internal pulse generator on the same clock path (US 5,920,510) yields only the expected result — the reset is no longer a function of the external duty cycle. Predictable-result rationale, MPEP 2144.1(a); In re Kemps.
3. Sense/address timing linkage is taught as a feedback relationship, not as a new idea. US 5,808,959 and its division US 5,872,742 generate the sense-amplifier control signal by delaying the word-line enable signal and terminate the enable in response to that delayed sense control. A POSITA reading that in 1999 would have recognized the already-solved half of the '266 problem — indeed the '266's own background says "there is no tracking mechanism between the reset of the addresses and the enabling of the dynamic amplifiers," which frames the linkage as an obvious improvement to make, not a discovery.
4. Per-block, block-select-keyed programmable delays with one global fuse code are taught for the same purpose. US 6,111,796 discloses block control circuitry receiving a block select signal, delay-adjust circuitry receiving a shared 4-bit fuse code, and programmable delay circuits enabling the amplifiers — with the two selection values chosen to "optimiz[e] the worst case of the access time of the memory." That is claim 2's architecture and claim 4's "selection circuit … provides a selection signal which indicates a delay," including the '266's express rationale (post-fabrication test → program the slowest path).
5. Fuse-blown post-fabrication trimming of an on-chip time constant was standard. US 5,321,661 (1994) describes blowing fuses after fabrication so a pass value / timer setting "can be changed according to the results of other tests." The '266 specification concedes that "[f]use-blowing is common in the memory art" and that redundancy and IC-identification fuses are blown on every device — an admission that the programming mechanism itself was routine.

Combination B — claim 3 (the "equal" limitation)

US 5,920,510 + US 5,808,959/5,872,742, optionally + US 6,111,796. Making the address-active window and the sense-enable delay numerically equal is a (i) result-effective design choice (In re Harza; MPEP 2144.1(a)), and (ii) a relationship the secondary reference already embodies functionally, since the enable window in the '959/'742 scheme ends when the delayed sense signal arrives. The '266 specification offers no criticality for equality (no data showing a non-equal relationship fails); it simply asserts the delay devices "each receive the same DC signals."

Combination C — claim 4 specifically

US 6,111,796 (first/second programmable delay circuits + fuse selection circuit with a continuous output) + US 5,920,510 (programmable pulse-width circuit on the address-buffer clock path) + US 5,808,959/5,872,742 (word-line driver enabled by an enable signal; sense amplifier enabled by a delayed enable). Claim 4 is the broadest framing of the same subject matter and is met essentially by the primary reference plus the pulse-width teaching.

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4. Where the challenge is weakest — and the § 103(c) wildcard

A. The RTZ "same logic state" limitation is admitted prior art. The only limitation not literally shown in the prior art is claim 1's final clause. Because the specification characterizes that exact behavior as the pre-existing "typical RTZ scheme," it is an admission of prior art (MPEP 2129; In re Fessmann; Riverwood Int'l v. RTC). It therefore cannot supply patentability, and a well-pleaded § 103 ground should say so expressly rather than hunt for an RTZ reference.

B. A genuine teaching-away argument exists against using US 6,111,796. The '796 background is critical of the fuse-based approach the '266 patent claims as its inventive core: fuses "take up space," and "using fuses to program a delay does not solve all of the problems associated with optimum control of the delay" — which is why the '796 patent's own solution uses two delay selection circuits rather than one global code. A patentee could argue the '796 patent teaches away from the '266's "one global delay code for all blocks." I would treat this as a manageable but real counter (§ 103 ground should instead use the '796 as claim-2 structural support and rest the "all blocks get the same delay" choice on the '266's own yield/margin rationale, plus US 5,321,661).

C. Pre-AIA § 103(c) may disqualify the strongest reference. US 6,111,796 is prior art only under § 102(e) (grant 2000-08-29, after the '266 priority date), and the record shows both the '266 and the '796 naming Ray Chang and being assigned to Motorola, Inc. at filing. Under pre-AIA § 103(c)(1), § 102(e)/(f)/(g)-only art that "was, at the time the invention was made, owned by the same person or subject to an obligation of assignment to the same person" may not be used in a § 103 rejection. If common ownership at invention is confirmed, US 6,111,796 and US 5,978,286 (if Motorola, as one search result indicates) drop out of a § 103 combination entirely — and the challenge must be rebuilt on the non-commonly-owned art: US 5,920,510 / JP H10-149682 (Hitachi), US 5,808,959 / US 5,872,742 (Alliance), US 5,321,661 (Oki), US 5,289,413 (Toshiba). That combination still reaches all limitations (per the table above) but carries more of the "block-select → programmable delay → sense amp" weight on the '959/'742 disclosure, which is where an evidentiary fight would move. The dispositive next step is to pull the assignment records and confirm chain of title as of the 1999 invention date.

D. Don't overlook the art the examiner never saw. US 5,808,959 / US 5,872,742 and JP H10-149682 (published 1998-06-02 — a true § 102(b) printed publication) appear only in the foreign family citations, not on the U.S. face. Combined with the admitted prior art, these give a § 103 ground that does not depend on the Motorola siblings at all.

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5. Bottom line

• Claims 1, 2 and 4 would have been obvious over US 5,920,510 (fuse/program-circuit-trimmed on-chip pulse controlling an address-input hold period, independent of external clock duty cycle) in view of US 5,808,959 / US 5,872,742 (word-line enable plus a delayed sense-amplifier control tied back to that enable), further in view of US 6,111,796 (per-block, block-select-keyed programmable delay driven by one shared fuse code, optimized to worst-case access time) and US 5,321,661 (post-fabrication fuse trimming of an on-chip timing value) — with the RTZ address-buffer limitation supplied by the applicant's own admitted prior art.
• Claim 3 would have been obvious as a result-effective design choice, and independently because the '959/'742 feedback scheme inherently ties the enable window to the delayed sense signal.
• The strongest unpredictable/threshold uncertainty is legal, not technical: pre-AIA § 103(c) may remove US 6,111,796 and US 5,978,286 from the combination, and the substance of the 2001 certificate of correction is still unverified.

Confidence: high on the disclosure content of US 5,920,510 and US 5,808,959/US 5,872,742 (full text retrieved and quoted). Moderate on US 6,111,796's precise per-block wiring (retrieved from the published description and claims, not the drawing sheets). Low on: US 5,978,286's identity/filing date (title conflict flagged, unresolved), US 6,141,272 (filing date never retrieved — I would not cite it), and the Japanese/Korean references, for which I have titles and dates from the patent page only and no translated text.