Invalidity dossier
US 4484301
Array multiplier operating in one's complement format
Current assignee: Unisys Corp
Added 9/23/2026, 9:22:01 PM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 4,484,301
Title: Array multiplier operating in one's complement format
Patent number: US 4,484,301 A
Application number: US06/242,214
Inventors: William L. Borgerding; Vithal R. Patel
Original assignee: Sperry Corp; current assignee listed as Unisys Corp
Priority/filing date: 1981-03-10
Publication (grant) date: 1984-11-20
Legal status listed: Expired – Lifetime (anticipated expiration 2001-11-20)
Purpose: The patent relates to digital apparatus for binary multiplication and teaches a method and apparatus for improving multiplication throughput within the arithmetic section of a digital computer. The stated advantage is an eight-bit multiplication cycle in fifty nanoseconds, described as a four-to-one improvement over taking roughly one hundred nanoseconds to multiply by only four multiplier bits.
Plain-language scope: A two's complement binary multiplication is performed piecemeal in one's complement format, multiplying the multiplicand by successive eight-bit bytes of the multiplier. A gate array assembly is divided into four ranks (A–D), each rank performing two-by-two addition of successive multiplicand bits with a partial sum and carry from the preceding rank. Multiplier bytes are preprocessed to account for binary "11" conditions; the preprocessed bits manipulate the multiplicand before addition. The multiplicand is left-shifted two bit positions per rank, while partial sum and carry are right-shifted eight bits after each multiply cycle. Final partial sum and carry are added, after adding a multiplier correction carry to the final partial carry, so the final product is in two's complement format. The described embodiment uses forty gate arrays sized for a sixty-bit mantissa in double precision floating multiply, with logic for fill bits and duplicate gate arrays for carry propagation between printed circuit boards. The excerpt names modes MI, MSI, MF, and FM.
Source: https://patents.google.com/patent/US4484301/en
What the excerpt does not establish: It does not provide the full text, complete claims, all drawing details, or the complete list of cited prior art. It also does not establish litigation, ownership transfers beyond the listed assignments, validity, or the accuracy of the listed legal status or assignees, which the source itself describes as assumptions.
Generated 10/1/2026, 9:34:20 PM
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Litigation summary
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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