US 7619912

I'll research this patent across USPTO and CAFC 2026 docket sources.

Let me dig deeper into the CAFC 2026 dockets and PTAB proceedings specific to '912.

Let me check for any decision or latest status in the '912 appeal (24-2304).

US Patent 7,619,912 — Research Summary

Scope note: I searched for the exact number 7,619,912 and excluded similar identifiers. Note a date discrepancy: your prompt says April 26, 2026, but my system date is 2026‑09‑28 and the freshest search results reference events through September 2026. I report status as of the latest available data and flag where things are moving.

1. Bibliographic data (authoritative, from the patent record)

Priority chain (literal, per the patent's own Cross‑Reference section): The '912 patent is a continuation of Ser. No. 11/173,175 (filed Jul. 1, 2005, now US 7,289,386), which claims benefit of provisional 60/588,244 (Jul. 15, 2004) and is a continuation‑in‑part of Ser. No. 11/075,395 (filed Mar. 7, 2005, now US 7,286,436), which claims benefit of provisionals 60/550,668 (Mar. 5, 2004) and 60/575,595 (May 28, 2004). Note the priority question (whether earlier filings support claim 16) was a central issue in the PTAB and on appeal.

Post‑issuance: The '912 patent was subject to inter partes reexaminations 95/000,578; 95/000,579; and 95/001,339, resulting in a reexamination certificate (cited as "7,619,912 C1"), which restated claims — including independent claim 16.

2. Abstract (verbatim)

"A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives a set of input control signals from the computer system. The set of input control signals corresponds to a second number of memory devices smaller than the first number of memory devices. The logic element generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices."

3. Plain-language overview of the independent claims

⚠️ Uncertainty flag: The authoritative text supplied to me was truncated once it reached the full claim set, so I cannot reproduce every independent claim verbatim or confirm exact independent‑claim numbering. The following is grounded in the Summary of the Invention, the specification, and the PTAB Final Written Decision (which reproduces the post‑reexamination claim 16 in full). Please treat claim numbering as provisional.

1. Rank‑multiplication apparatus claim (the "decoder"). A memory module (PCB + memory devices + a logic element) in which the logic element receives from the host a set of input control signals that correspond to a smaller number of memory devices than are actually populated, and generates a set of output control signals that correspond to the larger actual number. In plain terms: the module makes a server designed for fewer ranks see more physical ranks, using lower‑density DRAMs.

2. Method claim. A method of using such a module in a computer system: couple the module (whose devices are arranged in a first number of ranks), input a first set of control signals corresponding to a smaller second number of ranks, and generate a second set of control signals corresponding to the first (larger) number of ranks.

3. Means‑plus‑function claim. The same functionality recited in means‑for terms: means for coupling the module to the system, means for inputting the first (smaller‑rank) set of control signals, and means for generating the second (larger‑rank) set.

4. Isolation‑device claim. A module with a first and second memory device (each having a data line and a data‑strobe line), a common data signal line to the host, and an isolation device that selectively alternates between coupling the first data line and coupling the second data line to the common line. In plain terms: a switch/multiplexer that isolates devices from a shared data line to prevent signaling collisions (the patent's "BBARX" back‑to‑back adjacent read problem).

5. Independent claim 16 (the claim actually litigated and IPR'd — post‑reexamination text, verbatim from PTAB Paper 96): A memory module comprising a PCB; a plurality of DDR memory devices arranged in a first number of ranks; a circuit comprising a logic element and a register, the logic element receiving input signals comprising at least one row/column address signal, bank address signals, and at least one chip‑select signal, those input signals configured to control a second, smaller number of DDR devices/ranks; the circuit generating output signals configured to control the first, larger number of devices/ranks; the circuit responding to a command signal by selecting one or two ranks and transmitting the command to at least one DDR device of the selected rank(s); a phase‑lock loop device operatively coupled to the devices, logic element, and register; and wherein the command signal is transmitted to only one DDR memory device at a time.

Plain‑language gloss on claim 16: it adds the "circuit = logic element + register" architecture and a PLL to the basic rank‑multiplication concept, and limits command targeting so only one DRAM receives a given command at a time (allowing, e.g., refresh to be sent to both devices but read data to come from one).

4. CAFC 2026 docket status (specific to '912)

The '912 appeal of record is CAFC No. 2024‑2304, Netlist, Inc. v. Samsung Electronics Co., Ltd. (appeal from PTAB IPR2022‑00615).

• PTAB: Samsung petitioned (IPR2022‑00615, filed Feb. 17, 2022) on claim 16; Micron filed IPR2023‑00203 (Nov. 18, 2022) and was joined. Final Written Decision Paper 96, April 17, 2024: claim 16 unpatentable as obvious over Ellsberry (US 2006/0277355) under §103(a); the Board did not reach the Perego/Amidi grounds. Director review denied July 10, 2024 (Paper 103).
• Appeal: Netlist noticed appeal Sept. 10, 2024 → No. 2024‑2304. Samsung subsequently settled and withdrew; Micron continued as appellee. Netlist's opening brief (Feb. 18, 2025) frames the issues as (i) whether a "rank" must include multiple DRAM chips, (ii) whether Ellsberry teaches claim 16, and (iii) whether Ellsberry is prior art (i.e., whether the '436 patent/'244 provisional provide written‑description support).
• Oral argument: September 9, 2026 (panel Reyna, Linn, Stark). Per the oral‑argument summary, Micron conceded the Board's reliance on a website was improper but argued other record evidence independently supported the result.
• No merits decision in 24‑2304 was found in my searches. I could not confirm a final Federal Circuit ruling on the '912 as of the latest available data. Do not assume the appeal has been decided.

Related CAFC activity (distinct, not the '912 merits):

• No. 24‑2203 (Netlist v. Samsung) and 24‑2240/24‑2241 — separate patents ('918, '054, '060), argued Mar. 6, 2026; nonprecedential opinion Sept. 2, 2026.
• No. 24‑1707 (Netlist v. Micron, '339 patent) — precedential affirmance Sept. 2, 2026 (Ellsberry/Halbert obviousness; APA harmless‑error holding).
• Nos. 24‑1312/24‑1313 (Micron v. Netlist, IPR2022‑00744/‑00745) — affirmed Feb. 20, 2026.
• The Google Patents litigation panel also lists CAFC 25‑1936, CAFC 26‑1671, E.D. Tex. 2:22‑cv‑00294 / 2:22‑cv‑00293 / 2:23‑cv‑00628, D. Del. 1:21‑cv‑01453, and D. Idaho 1:25‑cv‑00323. I did not verify the subject matter of 25‑1936 or 26‑1671, so I cannot assert either concerns the '912 specifically.

District‑court context: A May 23, 2024 E.D. Tex. jury (2:22‑cv‑00294) found Micron willfully infringed the '912 and '417 patents and awarded $445M (~$425M on '912; ~$20M on '417). Post‑trial motions denied June 2025; Micron appealed. The '912 portion's collectability is tied to the outcome of appeal 24‑2304.

5. Explicit uncertainty statements

• Independent claim set: I cannot verify the exact count/numbering of the issued independent claims because the authoritative text supplied ends mid‑specification; the descriptions above are anchored to the Summary of the Invention and to claim 16 as restated in the reexamination certificate (reproduced in PTAB Paper 96).
• No final '912 CAFC decision found. Oral argument occurred Sept. 9, 2026; a decision may still be pending.
• CAFC 25‑1936 and 26‑1671 subject matter: unresolved.
• Priority‑date discrepancy: Google Patents labels the priority date 2004‑03‑05, while the Unified Patents portal shows 2004‑03‑04 for the same family. I did not resolve this one‑day discrepancy and flag it rather than pick one.

Key sources: US7619912B2 (Google Patents); PTAB IPR2022‑00615 Paper 96 (Apr. 17, 2024); CAFC No. 2024‑2304 docket and Netlist opening brief; CAFC oral‑argument page for 24‑2304 (Sept. 9, 2026); IPWatchdog and IP Case Updates coverage (Sept. 2, 2026) for related appeals.

I'll research litigation involving US 7,619,912 specifically. Let me run targeted searches.

Let me dig into specific case details and dockets.

Let me verify the PTAB proceedings and recent case outcomes.

Litigation Involving U.S. Patent No. 7,619,912

Identification of the patent (interpreted literally). US 7,619,912 B2, titled "Memory module decoder," inventors Jayesh R. Bhakta and Jeffrey C. Solomon, assignee Netlist, Inc. Application No. 11/862,931, filed September 27, 2007; granted November 17, 2009. Priority date listed as March 5, 2004. The patent issued from a continuation of application 11/173,175 (now U.S. 7,289,386) and a continuation-in-part of 11/075,395 (now U.S. 7,286,436). Google Patents' legal-status field shows "Expired – Lifetime," with an adjusted expiration of 2026-01-08 (this is a status assumption, not a legal conclusion). Note that PTAB dockets cite the patent as "7,619,912 C1," i.e., the patent as amended by the merged reexamination certificate that issued February 8, 2021 (see reexamination discussion below).

Source of record for the family litigation list: https://patents.google.com/patent/US7619912/en and the Stanford NPE Litigation Database entry https://npe.law.stanford.edu/patent/7619912.

A. District court cases

Explicitly not included: Netlist v. Samsung, E.D. Tex. 2:21-cv-00463 ("Samsung I," filed Dec. 20, 2021) and Netlist v. Micron E.D. Tex. 2:22-cv-00203 ("Micron I") do not appear to assert the '912 patent; my document review shows the '912 patent was asserted in the second Micron case (2:22-cv-00294) and the 2022 Samsung case (2:22-cv-00293). I also did not include E.D. Tex. 2:25-cv-00748 / 2:25-cv-00749 (filed July 28, 2025) because the sources I retrieved tie those to other patents (e.g., the '366 patent), not expressly to 7,619,912.

B. USPTO post-grant proceedings (these drive the district-court outcomes)

• IPR2022-00615, Samsung Electronics Co., Ltd. v. Netlist, Inc., filed Feb. 17, 2022, challenging claim 16 of U.S. 7,619,912 C1. Micron entities petitioned and moved for joinder in IPR2023-00203 (filed Nov. 18, 2022) and were joined as petitioners. The Board rejected Netlist's § 315(b) time-bar/real-party-in-interest argument (Google held not to be an RPI). Final Written Decision April 17, 2024 (Paper 96): claim 16 unpatentable. Director review denied July 10, 2024 (Paper 103). Appeals: Fed. Cir. No. 24-2304 (Netlist's appeal, filed Sept. 11, 2024). Google Patents also lists PTAB IPR2023-00203 and, in the CAFC column, 25-1936 and 26-1671 against this patent family.
• Note: the FWD for the companion '417 patent in IPR2023-00454 issued July 30, 2024; the E.D. Tex. stay order in 2:23-cv-00628 referred to both patents' decisions collectively.
• Merged inter partes reexamination: requests by Google, Inphi, and Smart Modular (SM) were filed in 2010 in Control Nos. 95/000,578, 95/000,579, and 95/001,339, merged Feb. 28, 2011; all claims including claim 16 were examined; claim 16 was repeatedly confirmed and the Federal Circuit affirmed in Google LLC v. Netlist, Inc., 810 F. App'x 902 (Fed. Cir. 2020). The reexamination certificate ("C1") issued Feb. 8, 2021.

C. Appellate proceedings (Court of Appeals for the Federal Circuit)

Google Patents' "family has litigation" record lists these CAFC dockets for this patent: 24-2304, 25-1936, and 26-1671. Only 24-2304 is substantively identified in my sources (Netlist's appeal of the IPR2022-00615 FWD; appellees include Samsung and the Micron entities). I do not have confirmed dispositions for 24-2304, 25-1936, or 26-1671, and the existence of a 2026 docket number indicates appellate activity was still ongoing as of the most recent material available to me. I will not speculate on outcomes I cannot verify.

D. Bottom line

Yes — there is substantial known litigation over 7,619,912, all involving Netlist, Inc. as patent owner/asserter (or as counterclaim-plaintiff) against Google, Inphi, Samsung, and Micron. Reported outcomes to date include two plaintiff-side jury verdicts specifically covering the '912 patent: $118,000,000 (Netlist v. Samsung, E.D. Tex. 2:22-cv-00293, Nov. 22, 2024) and $425,000,000 on the '912 patent alone (Netlist v. Micron, E.D. Tex. 2:22-cv-00294, May 23, 2024) — both rendered after which the PTAB found the challenged '912 claim unpatentable in IPR2022-00615 (claim 16, April 17, 2024), a decision now on appeal. The Google case (N.D. Cal. 3:09-cv-05718) and the Samsung DJ case (D. Del. 1:21-cv-01453) are stayed; the Netlist-v-Micron DJ action (E.D. Tex. 2:23-cv-00628) is stayed; and Samsung filed a new Delaware DJ action (1:25-cv-01371) expressly listing the '912 patent.

Caveats: (1) The '912 patent's legal status field shows expiration on 2026-01-08, so any ongoing or future cases can reach only past damages. (2) I was unable to verify the current disposition of several 2025–2026 dockets (2:25-cv-00748/749, 2:23-cv-01122, 1:25-cv-00323, and CAFC 25-1936 / 26-1671) within the search steps available; those entries should be confirmed on PACER/CourtListener before being relied upon. (3) Schoolhouse/forum posts (e.g., suggesting dismissal of 2:22-cv-00293 in 2025) are not authoritative and are flagged as unverified.

I'll start by verifying the PTAB activity against the canonical list and the pointers in the patent record.

Strong signal — the structured block is out of date. Let me pin down the details, plus the later-filed cases and the appeal disposition.

Now let me verify whether there was an earlier IPR on this patent (the "selectively electrically coupling" line of cases) and the current state of the 2024-2304 appeal.

PTAB / AIA Trial Proceedings — U.S. Patent No. 7,619,912 C1 ("Memory module decoder," Netlist, Inc.)

Data-integrity flag (read first). The structured block supplied with this task says the USPTO ODP returns no AIA trial proceedings for this patent. That is a stale / incorrect ingest. The public record shows two AIA trials on claim 16 of the '912 patent, both filed by Samsung/Micron, both resolved in April 2024 with a Final Written Decision holding claim 16 unpatentable, and an appeal now argued at the Federal Circuit. The patent itself also carries a reexamination certificate ("7,619,912 C1"), which is why PTAB papers caption it that way. Treat the ODP "no proceedings" entry as a null result, not as evidence of a clean patent.

Proceedings overview

Two AIA trials on file, and both went against the patent owner: 0 active, 0 settled, 0 institution denials, 2 claims-invalidated proceedings (IPR2022-00615; IPR2023-00203, which was joined into 00615) — both challenging claim 16 only, both resulting in a Final Written Decision on 2024-04-17 holding claim 16 unpatentable as obvious over Ellsberry (§ 103(a)), now on appeal (Fed. Cir. No. 2024-2304, argued 2026-09-09, decision pending). Bottom line for a defendant: the one claim that was ever tested at the PTAB is dead at the Board, and no other claim (1–15, 17–55) has ever been through an AIA trial — so the patent is neither "hardened" by PTAB wins nor fully cancelled, and its sole litigated claim is on life support pending appeal.

IPR2022-00615 — Samsung Electronics Co., Ltd. v. Netlist, Inc.

• Type: Inter Partes Review (the parent proceeding; Micron later joined as petitioner)
• Filed: 2022-02-17 (Netlist's own 10-Q confirms the filing date)
• Status: "Final Written Decision – Appealed" (Unified Patents/Exparte case record); trial closed 2024-04-17. Verbatim outcome field: "Unpatentable."
• Judge panel: Final Written Decision — Administrative Patent Judges Jon M. Jurgovan, Daniel J. Galligan, and Kara L. Szpondowski. Institution panel (Paper 20) — Jurgovan, joined by Galligan and Nabeel U. Khan.
• Petition grounds (all against claim 16, all § 103(a)):
  • Ground 1 — claim 16 obvious over Perego-422
  • Ground 2 — claim 16 obvious over Perego-422 + Amidi
  • Ground 3 — claim 16 obvious over Ellsberry (de facto § 102(a)/(e)-type reference whose prior-art status depended on a priority challenge)
• Institution decision: Instituted 2022-10-19 (Paper 20), § 314(a). The panel instituted in part on a reference of record that the examiner had previously rejected as not prior art, because Petitioner carried its initial burden to show the challenged claim was not entitled to its earlier priority date, making Ellsberry prior art (Banner Witcoff PTAB Highlights, 2022-10-31). The institution was then subjected to sua sponte Director Review: the Director granted review (Paper 38), stayed the proceeding, denied Patent Owner's rehearing/POP request (Paper 40), granted-in-part additional discovery on whether Google was a real party in interest (a § 315(b) time-bar theory arising from the 2009 Google litigation), and remanded; the Board ultimately found Google was not an RPI (Order on Remand, Paper 62/64), so the petition was not time-barred.
• Final Written Decision: Paper 96, 2024-04-17. Holding: "For the foregoing reasons, we determine that Petitioner establishes by a preponderance of the evidence that claim 16 of the '912 patent is unpatentable." Order: "ORDERED that claim 16 of the '912 patent has been shown to be unpatentable." Two interlocking rulings:
  1. Claim construction — "rank." "we determine that the intrinsic evidence of the '912 patent shows that the claim term 'rank' may include only one memory device." The panel relied on claim 16's own language (no lower bound on devices per rank) and on claim 55 ("each rank … comprises a plurality of the DDR DRAM chip packages"), reasoning that otherwise the claim-55 limitation would be superfluous.
  2. Priority. The Board found no written-description support in the '436 patent or the '244 provisional for claim 16 (the priority documents predate Ellsberry), which is what made Ellsberry available as prior art. Ground 3 was dispositive, so the panel did not reach Grounds 1 and 2 (Perego-422 alone; Perego-422 + Amidi). The FWD outcome table therefore shows only: 16 / § 103(a) / Ellsberry / Shown Unpatentable.
  • Claim-level granularity: claim 16 — unpatentable. No other claim was challenged, instituted, or decided. Do not read this FWD as invalidating claims 1–15 or 17–55.
  • Other FWD dispositions: Patent Owner's Motion to Submit Supplemental Information (re: a Micron corporate-rep deposition allegedly inconsistent with Micron's positions) — dismissed; Petitioner's Motion to Exclude — dismissed as moot.
• Settlement / termination: None. Full trial to FWD; no settlement or adverse-judgment termination.
• Director Review: Netlist filed a Request for Director Review (Paper 97), arguing the Board improperly denied claim 16 the '244 provisional's priority date by requiring the words "bank address" in haec verba, contrary to Blue Calypso and MPEP § 2164.01. Denied — Paper 103, 2024-07-10.
• Appeal: Yes. Netlist filed a notice of appeal 2024-09-10, Fed. Cir. No. 2024-2304, captioned Netlist, Inc. v. Samsung Electronics Co., Ltd. (short caption per the CAFC docketing notice). Issues: (i) whether "rank" can consist of a single DRAM device; (ii) whether the Board erred in finding claim 16 not entitled to the '436 patent / '244 provisional priority dates; (iii) whether Ellsberry discloses all limitations; (iv) APA/vacatur arguments on the dependent claims. Oral argument was scheduled for and held on 2026-09-09 (per Netlist's 10-Q); as of 2026-09-28 no decision has issued. Netlist's own framing of the claim history — "Claim 16 Survives Multiple Inter Partes Reexaminations and Is Restated to Its Current Form" (Netlist opening brief) — confirms claim 16 was rewritten in reexamination before the IPR.
• Defensive value: The Board has already held claim 16 unpatentable, and that holding will become the operative record if affirmed. But it is not yet final: pending the 2024-2304 mandate, you cannot treat the claim as cancelled. Because only claim 16 was in the trial, § 315(e)(2) estoppel reaches Samsung (and its privies) as to claim 16 alone — and a non-privy defendant can still take the same Ellsberry/Ellsberry-based obviousness shot.
• Links: PTAB proceeding portal — https://portal.unifiedpatents.com/ptab/case/IPR2022-00615 ; case record — https://ai-lab.exparte.com/case/ptab/IPR2022-00615/samsung-electronics-co-ltd-v-netlist-inc ; FWD text (mirrored) — http://fedcircuitblog.com/wp-content/uploads/2025/03/open-1.pdf ; USPTO PTAB decisions — https://www.uspto.gov/patents/ptab/decisions ; PTAB E2E — https://ptacts.uspto.gov/ptacts/

IPR2023-00203 — Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC v. Netlist, Inc.

• Type: Inter Partes Review, filed with a motion for joinder to IPR2022-00615
• Filed: 2022-11-18 (confirmed by Netlist's 10-Q and the PTAB record: "Micron Technology, Inc. et al. v. Netlist, Inc., IPR2023-00203 (PTAB filed Nov. 18, 2022)")
• Status: Final Written Decision (terminated); joined into IPR2022-00615 and decided by the same merits panel. The FWD states: "Micron … filed a petition and requested joinder to this proceeding. IPR2023-00203, Papers 1, 3. We granted the Micron entities' petition for inter partes review and joined them as parties on the petitioner side of this case. Id. at Paper 8. … We refer to Samsung and the Micron entities together as 'Petitioner' in this proceeding."
• Judge panel: Reported by a third-party docket aggregator as Bryan F. Moore, Jon M. Jurgovan, and Sheila F. McShane on the joinder/institution papers (Patexia). The merits FWD is the IPR2022-00615 panel (Jurgovan, Galligan, Szpondowski). Flagging this panel discrepancy rather than papering over it — verify on PTAB E2E.
• Petition grounds: Mirrors the Samsung petition — claim 16, § 103(a), over Perego-422 / Perego-422 + Amidi / Ellsberry. (One aggregator lists "claims 1–34" as challenged in IPR2023-00203; that appears to be a data artifact. Every primary source — Netlist's 10-Q, the FWD, and the joined-proceeding caption — describes claim 16 as the sole challenged claim in the joined trial. Do not rely on the "1–34" figure.)
• Institution decision: Granted 2023-06-07 (as reported by the aggregator), institution + joinder granted (Paper 8), with a copy of that institution decision entered in IPR2022-00615. Because of the joinder, the Director delegated authority adjusted the one-year FWD deadline to 2024-04-19.
• Final Written Decision: The Board issued the same 2024-04-17 FWD holding claim 16 unpatentable over Ellsberry; the two proceedings are treated as "the two IPRs" in Netlist's SEC filings ("On April 17, 2024, the PTAB issued a final written decision in the two IPRs finding Claim 16 of the '912 Patent unpatentable").
• Settlement / termination: None — resolved on the merits via joinder.
• Appeal: Covered by the appeal from the joined proceeding, Fed. Cir. No. 2024-2304 (Netlist's notice of appeal, 2024-09-10).
• Defensive value: Micron is now bound by § 315(e)(2) estoppel on claim 16 (as a joined petitioner and party) — it cannot re-run the Ellsberry-based attack on claim 16 in E.D. Tex. or the ITC. Note the practical consequence: Micron's only route on claim 16 in the co-pending cases was to argue the estoppel point, which it did in the 2023 stay briefing (acknowledging that to the extent the FWDs "confirm the validity" it could re-raise grounds, "other grounds" being the operative carve-out).
• Link: https://portal.unifiedpatents.com/ptab/case/IPR2023-00203

Unverified lead — flag before relying on it

An exhibit in the IPR2023-00203 record is titled "IPR2014-00882," and its text discusses the Federal Circuit's construction of "selectively electrically coupling" and "selectively isolating" and the remand in Netlist, 701 F. App'x 1003 (Fed. Cir. 2017) (vacating the Board's constructions as unreasonable and remanding). The '912 patent was the subject of a 2009 Google/Netlist lawsuit (referenced in the IPR2025-01431 record as "the 2009 lawsuit between Google and Patent Owner involving the '912 patent"). These facts are consistent with an earlier Google-filed IPR on the '912 patent, but I could not confirm in this session that IPR2014-00882 is directed to U.S. 7,619,912, nor its petitioner, institution outcome, or final disposition. Do not plead it as a proceeding on the '912 patent until verified on PTAB E2E. If confirmed, it matters mainly for the § 315(b)/(e) posture of Google as a petitioner, not for a new defendant.

Separately: the '912 patent was the subject of an ex parte reexamination (a third-party request filed 2010-05-07 attacking claims 1–51 on Murdocca + the '074 patent), which produced the C1 certificate and the current claim text. That is a reexamination, not an AIA trial, but it is the reason claim 16 reads as it does.

Strategic summary

What is canceled vs. sustained vs. untested. One claim — claim 16 — has been held unpatentable by the Board (FWD 2024-04-17), and it is the only claim ever presented in an AIA trial. Claims 1–15 and 17–55 are untested at the PTAB. So the correct statement is not "claims 1–5 have been canceled" — nothing near it. The correct statement is: the flagship apparatus claim of the '912 patent is on appeal after losing at the Board, and the rest of the claims have never been tested. One important overlay: the patent's own legal status record shows "Expired – Lifetime," adjusted expiration 2026-01-08, meaning as of today the '912 is expired — injunctive relief is off the table and any live exposure is past damages (subject to the § 286 six-year lookback), which materially reduces the settlement value of a demand letter. Verify that expiration and any term adjustment against the face of the patent and the reexamination certificate before relying on it.

Estoppel landscape (§ 315(e)(2)). Samsung and the Micron entities (and their privies, including any entity found to be an RPI) are estopped, as to claim 16 only, from asserting in district court or the ITC any ground raised or that reasonably could have been raised in the IPR — which sweeps in Perego-422 alone, Perego-422 + Amidi, Ellsberry, and any obviousness combination they could have articulated. For a new, non-privy defendant, nothing is estopped: the entire prior-art universe remains open on claims 1–15 and 17–55, and even on claim 16 you can still run Ellsberry (subject to issue preclusion arguments only after appellate finality) and, more attractively, the Perego-422 / Perego-422+Amidi grounds the Board never reached on the merits. Those are the most under-exploited grounds on this patent, because they exist in a public record, were never adjudicated, and are free for a non-petitioner to adopt.

Pattern signals. The '912 drew a two-front, coordinated attack: Samsung filed first (2022-02-17), then Micron filed and joined (2022-11-18) — an efficiency play that produced a single FWD binding both. Netlist litigates hard on the downside: it forced sua sponte Director Review at the institution stage (RPI/§ 315(b) theory against Google), sought additional discovery on real-party-in-interest, and filed a second Director Review request against the merits FWD (denied 2024-07-10) before appealing. There is no defensive aggregator (e.g., Unified Patents) in this particular chain — the petitioners are the accused infringers themselves and their subsidiaries. The broader pattern is a repeat-player campaign: Samsung has since filed a wave against Netlist's newer memory patents (PGR2025-00071 re U.S. 12,308,087; IPR2025-01402; IPR2025-01431 re U.S. 10,025,731; IPR2026-00017 re U.S. 9,824,035; PGR2026-00001 / IPR2026-00018 re U.S. 12,373,366), and Samsung's own briefs in that campaign describe the '912 as invalidated in 2024 alongside the '364, '185, '907 and '339 patents. Netlist, for its part, is a serial Director-Review and appellate litigant — which is exactly what's happening with claim 16.

Recommended next steps

1. Get the FWD in front of the file now. Quote the disposition verbatim in any validity analysis: "ORDERED that claim 16 of the '912 patent has been shown to be unpatentable" (IPR2022-00615, Paper 96, 2024-04-17), and the construction holding: "the intrinsic evidence of the '912 patent shows that the claim term 'rank' may include only one memory device." If a demand letter or an infringement contention is built on claim 16, it is built on a claim the Board has invalidated; the only caveat is that the invalidation is not yet final pending Fed. Cir. No. 2024-2304. Frame it as "invalidated by the PTAB, on appeal," not as "cancelled."
2. Docket-watch Fed. Cir. 2024-2304. Oral argument was held 2026-09-09; the panel's decision is now the gating event. If affirmed, claim 16 is effectively out of the case and the patent is reduced to untested claims 1–15 / 17–55 on an expired patent. If vacated/remanded, claim 16 comes back to life and the Board's "single-device rank" construction — and its priority holding — are back in play. Set a calendar reminder to check the CAFC docket weekly; there is no PTAB trial deadline left to track (both trials are closed).
3. Exploit the untouched record. Grounds 1 and 2 (Perego-422; Perego-422 + Amidi) were raised but never decided — a non-petitioner is free to run them. Pair them with a § 112 priority attack on claim 16's lineage (the Board's finding that the '436 patent and '244 provisional lack written-description support is a published, quote-able finding that transfers to any claim in this family relying on the same priority chain).
4. Run an expiration / damages check. Confirm the 2026-01-08 adjusted expiration and the reexamination certificate's effect on term. If the patent is expired, reframe the dispute entirely around pre-expiration damages and drop injunction exposure from your risk model.
5. Don't over-read the absence of more PTAB activity. Two IPRs on a single claim, with an intervening sua sponte Director Review and a 2.5-year appeal, is a heavily litigated history for one claim — not a quiet patent. The reason there are no IPRs on claims 1–15 / 17–55 is that the parallel litigations focused on claim 16 (and on other, newer Netlist patents), not because those claims are strong.

I'll research the assignment record for US 7,619,912, focusing on the recorded reassignments and correspondents of record.

Let me get the specific reel/frame numbers and correspondents of record for each link.

Assignment record — US 7,619,912 ("Memory Module Decoder")

Scope of this pass. I reconstructed the chain from the patent record's own legal-events data (Google Patents reassignment entries), the PTAB exhibit that reproduces the recorded SVIC security instrument (IPR2026‑00017, EX2006), and Netlist's SEC filings. I was not able to open the USPTO Assignment Center record set directly before hitting my research limit, so two of the four link‑level reel/frame citations below are marked unverified. I flag every gap rather than filling it.

Headline finding: every post‑issuance recordal on the '912 is a lien (security interest) or a release of a lien — not a transfer of ownership. No assignment to any NPE, holding LLC, or licensing entity has ever been recorded against this patent. Netlist, Inc. remains both the original and the current assignee of record.

Inventors

Pattern check: No unusual departure signal. Both inventors appear on the reexam certificate alongside Netlist as assignee, and both are co-named on the Bhakta et al. Netlist memory-module family (the '436, '386, '535, '537, '627 and related patents). There is no 12‑month pre‑fire‑sale abandonment pattern here — the patent was filed 2007‑09‑27 and issued to Netlist 2009‑11‑17, and Netlist has held it continuously for ~18 years. I could not independently verify either inventor's current employment; treat that as unknown.

Original assignee

Netlist, Inc. — Irvine, California (51 Discovery, Suite 150, Irvine, CA 92618 was its chief executive office in the same period). Delaware corporation; publicly traded (OTCQB: NLST).

• Primary line of business: advanced memory and storage. Historically a DRAM module designer (HyperCloud, NVvault); today it sells Lightning overclocked/low-latency DDR5 RDIMM and UDIMM modules, discrete DRAM, low-profile memory subsystems, and flash/SSD products, and is developing CXL NVvault and MRDIMM. It also resells constrained DDR4/DDR5 sourced partly through Hynix.
• Did it ship a product embodying the claims? Yes — the '912 claims a memory module with a decoder logic element that lets a host configured for fewer ranks address more physical ranks. That is exactly the hypercloud/high‑density DIMM architecture Netlist commercialized and now litigates over; Netlist's own branded module sales ("double-digit millions" per the Q2 2026 call, with total H1 2026 revenue of $214.7M) put it firmly on the product side of the line.
• Financial status: operating, not in bankruptcy. FY2025 revenue $188.6M; Q2 2026 revenue $109.8M; $40.7M cash and minimal debt at Q2 2026; a $10M working-capital line plus ~$74M unused equity line. It runs ~$9M/quarter in IP legal fees (Q1 2026: $8.97M), i.e., enforcement is a material budget line.
• Hybrid caution: ~80% of recent revenue is resale of third-party DRAM rather than Netlist‑designed product, and its patent program was historically financed by a third-party monetization arrangement (see 2013 entry below). Netlist is an operating company, but not a pure one.

Assignment timeline

Framing note before the list: the USPTO has no record of an ownership change on the '912. Everything recorded post‑issuance is a collateral pledge or its discharge. The original inventor→Netlist assignment (executed on or about the 2007 filing / 2009 issuance) is presumed recorded, but I could not surface its reel/frame; the patent face and the reexam certificate simply list Netlist as assignee.

1. 2013‑07‑18 (executed) / recorded 2013‑07‑2x — Reel/Frame: not verified

• Conveyance: Security Agreement (Intellectual Property Security Agreement, granting a first‑priority security interest in Netlist IP other than certain NVvault patents)
• Assignor: Netlist, Inc. (a Delaware corporation, styled "Debtor"/"Grantor")
• Assignee: DBD Credit Funding LLC ("Secured Party"), 1345 Avenue of the Americas, 46th Floor, New York, NY 10105 — the lending vehicle for Drawbridge Special Opportunities Fund LP / Fortress Investment Group
• Correspondent: not verified
• Context: securitization — collateral support for a $15M‑class term loan closed the same day, tied to a seven‑year "Patent Monetization" side letter. Not an ownership transfer.

2. 2015‑11‑18 (executed) / recorded 2015‑11‑20 — Reel 037150 / Frame 0897 (appears to be the covering recordal for the multi‑patent instrument; '912 is listed among the collateral)

• Conveyance: Security Interest (Intellectual Property Security Agreement)
• Assignor: Netlist, Inc. (Delaware corporation, "Grantor")
• Assignee: SVIC No. 28 New Technology Business Investment L.L.P. — a Korean limited liability partnership, described in the instrument as "Secured Party"
• Correspondent: DLA Piper LLP (US); name of submitter: Troy Zander. (Read from the recordation cover sheet quoted in IPR2026‑00017, EX2006, filed 2025‑12‑29. Treat the correspondent attribution as moderate confidence — the exhibit bundles several Netlist instruments.)
• Context: securitization — venture‑debt collateral pledge by the operating company. Not an ownership transfer.

3. 2015‑12‑03 (recorded) — Reel/Frame: not verified

• Conveyance: Termination of Intellectual Property Security Agreement
• Assignor: DBD Credit Funding LLC
• Assignee: Netlist, Inc.
• Correspondent: not verified
• Context: release of the 2013 lien on payoff/refinancing. Title remained with Netlist throughout.

4. 2023‑11‑20 (recorded) — Reel/Frame: not verified

• Conveyance: Release by Secured Party
• Assignor: SVIC No. 28 New Technology Business Investment L.L.P.
• Assignee: Netlist, Inc.
• Correspondent: not verified
• Context: discharge of the 2015 lien, leaving the '912 unencumbered roughly one month before Netlist filed Netlist v. Micron, No. 2:23‑cv‑00628 (E.D. Tex., filed 2023‑12‑22).

No fifth link. There is no recorded assignment to any Acacia/Marathon/IV/Wi‑LAN‑type entity, no shell‑LLC transfer, and no defensive aggregator in this chain.

Timeline diagram

timeline
    title Ownership and liens US 7619912
    2004 : Priority date
    2007 : Application filed
         : Assigned to Netlist Inc
    2009 : Patent issued
    2013 : Lien to DBD Credit Funding
    2015 : Lien to SVIC No 28
         : DBD lien terminated
    2023 : SVIC lien released
    2024 : Micron willful infringement verdict

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No link in the chain moves the patent to a licensing‑only LLC, and no link is a change of owner at all. The only non‑Netlist names in the record (DBD Credit Funding LLC, SVIC No. 28) are secured creditors holding liens, which under 37 CFR Part 3 does not vest title — the recordation data sheet in the '578 reexam file even carries the standard USPTO caveat that "the ownership of the patent is still reflected in the assignor." Supporting entries: 2013‑07‑18 DBD security agreement; 2015‑11‑18 SVIC security interest, Reel 037150/0897; both later released (2015‑12‑03 and 2023‑11‑20).

2. Known asserter in the chain — NOT PRESENT. No assignee matches a public NPE list (Acacia, Marathon, IV, IPNav, Wi‑LAN, Conversant/Mosaid, Vringo, Pendrell, Round Rock, etc.). Netlist carries an entity profile on the Stanford NPE Litigation Database only because the database indexes every patent‑assertion suit and Netlist is the asserting party — it appears there as a plaintiff alongside named product‑company defendants (Micron, Samsung), not as a classified NPE assignee. I would not treat that directory hit as a finding.

3. Repeat correspondent across the chain — UNCLEAR (insufficient sample). I have only one attributable correspondent on the chain: DLA Piper LLP (US), submitter Troy Zander, on the 2015 SVIC recordal (Reel 037150/0897). One appearance is not a recurrence signal under the stated rule, and DLA Piper does ordinary operating‑company financing/IP work. For completeness: the prosecution and reexam correspondence of record is Morrison & Foerster LLP (Customer No. 25224) for Netlist, with Orrick, Herrington & Sutcliffe LLP (IP Prosecution Department, Irvine, CA) listed for third‑party requester Smart Modular Technologies in reexam 95/000,578 — those are litigation/reexam addresses, not assignment correspondents, and should not be conflated.

4. Cascading transfers — NOT PRESENT. Four recorded events across ten years (2013→2023), and none of them transfers ownership. No chained LLCs, no shared correspondent address across consecutive links.

5. Pre-litigation transfer — NOT PRESENT (with a non-transfer analogue worth noting). No ownership assignment within six months of a suit. There is a timing echo: the SVIC lien release was recorded 2023‑11‑20, and Netlist filed its Micron module suit 2023‑12‑22 — i.e., the patent was deliberately cleared of collateral before a damages claim that ultimately produced a ~$425M '912 verdict (E.D. Tex., May 2024, willfulness found). This is "clean‑title before assertion," not an NPE transfer, but it is the cleanest piece of evidence that the chain was curated for enforceability.

6. Bankruptcy fire-sale — NOT PRESENT. Netlist never filed Chapter 7/11. It came close to distress in the 2013 loan period (hence the DBD/Fortress collateral pledge), but stayed listed and operating, and has since become cash‑generative.

7. Privateering — UNCLEAR / historically adjacent. The 2013 DBD/Fortress transaction bundled a security agreement with a seven‑year Patent Monetization Letter Agreement (Netlist pays the lender up to a capped share of patent‑assertion proceeds, capped legal spend at 40% of gross recoveries, plus warrants). That is third‑party financing of an operating company's own assertions — closer to litigation funding than to classic privateering. It is not a transfer of assertion rights to a separate NPE, and I found no evidence of a current third party asserting the '912 on Netlist's behalf.

8. Defensive aggregator — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. Unified Patents appears in this record only as the source of the PTAB/litigation metadata and as the portal where Samsung's IPRs surface — i.e., as an adverse challenger, not a purchaser. Note the direction of travel is opposite: Netlist in Aug 2026 cross‑licensed its entire portfolio to Samsung (with a $200M upfront fee) rather than selling to a defensive pool.

Verdict

Operating-company assertion.

Netlist, Inc. is the original and current assignee of record, has never transferred the '912 to any third party, and ships memory modules — including its own branded Lightning RDIMM/UDIMM line and the high‑density module architectures this patent family covers — while asserting the patent against genuine competitors (Samsung, Micron, Google, Supermicro). The only recorded third‑party interests are two financing liens — DBD Credit Funding (2013‑07‑18, released 2015‑12‑03) and SVIC No. 28 (recorded 2015‑11‑20, Reel 037150/0897, released 2023‑11‑20) — both of which are collateral, not conveyances, leaving Netlist's title intact. The mitigating detail worth carrying forward: Netlist's enforcement is partly funded by third‑party monetization economics and roughly 80% of its recent revenue is resale rather than its own product, so the "operating company" label is real but thinner than the surface suggests.

Verification link: https://assignmentcenter.uspto.gov/ (search patent number 7619912; mirror index at https://assignment.uspto.gov/patent/index.html). Google Patents legal‑events view for cross‑check: https://patents.google.com/patent/US7619912/en.

Explicit gaps: (a) reel/frame unverified for the 2013 DBD security agreement, the 2015‑12‑03 DBD termination, and the 2023‑11‑20 SVIC release; (b) original inventor→Netlist assignment reel/frame not surfaced; (c) DLA Piper/Troy Zander attribution read from a bundled PTAB exhibit rather than the Assignment Center record itself — moderate confidence; (d) one‑day priority‑date discrepancy (2004‑03‑04 vs 2004‑03‑05) noted in the prior section remains unresolved and does not affect the ownership analysis.

I'll research the cited prior art references for US 7,619,912, building on the sections already produced (I will not repeat the bibliographic/claim/CAFC content, and I'll flag that the "prior art" here is distinct from the litigated prior art like Ellsberry).

Let me pull the actual front-page "References Cited" list (US patents, foreign documents, and NPL) and verify individual citations.

Good — I now have the front-page citation skeleton. Let me verify the identities/dates of the key cited references and get the complete front-page list.

Prior Art Analysis — US 7,619,912 B2 ("Memory Module Decoder")

Scope note (builds on the prior section, does not repeat it). The previously generated section already established the bibliographic data, priority chain, post‑reexamination claim 16, and the CAFC/PTAB status. Those are not repeated here. Two things from that section matter directly to this task and I carry them forward:

1. The '912 is now "US 7,619,912 C1" (reexam certificate: claims 2, 5, 7, 9, 21, 23, 25, 26, 30, 33, 42, 44, 51 cancelled; claims 1, 15, 16, 28, 39, 43 amended; new claims 52–91 added). So "which claim does reference X anticipate" must be answered against the C1 numbering, not the 2009 printed numbering.
2. Pre‑AIA §102 applies (earliest priority 2004‑03‑05), so the relevant categories are §102(a)/(b) (patents and printed publications before the invention/publication date) and §102(e) (U.S. applications/patents by another with earlier effective filing).

Date discrepancy flag (repeated deliberately): the task header says April 26, 2026, but my system date is 2026‑09‑28 and the freshest sources reach September 2026. I flag this rather than silently pick one.

Tooling limitation, stated honestly: I was able to retrieve the front‑page citation list and the post‑grant prior‑art record, but I hit the research-step ceiling before individually verifying every one of the ~50 face‑of‑patent U.S. citations. References I could not independently verify are marked [unverified]. I have not fabricated titles, dates, or inventors for those.

1. The critical distinction: two different "prior art" sets

For the '912 these are not the same set, and conflating them is the most common error when people analyze this family.

This is the headline finding: the prior art most relevant to the '912 is not on the patent's front page.

2. §102 vs. §103 — a necessary caveat before the tables

You asked, for each reference, which claims it "potentially anticipates under §102." Strictly:

• No reference has been held to anticipate any claim of the '912. Every holding in IPR2022‑00615 was §103(a) obviousness (Paper 96, Apr 17, 2024, Grounds 1–3; claim 16 unpatentable). The Board did not reach the Perego/Amidi grounds; it decided on Ellsberry alone under §103.
• Anticipation under §102 requires a single reference disclosing all limitations "arranged as in the claim." The mapping below is therefore "potential §102 exposure," not an adjudicated result. Where a reference discloses most but not all elements, it is an obviousness reference, not an anticipation reference.

3. Set B — the operative prior art (most relevant), with claim mapping

Supporting evidence for the Set B analysis (maps to specific claims rather than being generic):

• FWD reference table: Perego‑422 US 7,363,422 B2 (Apr 22, 2008), Ex. 1035; Amidi US 2006/0117152 A1 (Jun 1, 2006), Ex. 1036; Ellsberry US 2006/0277355 A1 (Dec 7, 2006), Ex. 1037 — [docketalarm IPR2026‑00017 Ex. 1033 / PGR2025‑00071 Ex. 1100].
• Grounds 1–3 as instituted: Ground 1 = claim 16 §103(a) over Perego‑422; Ground 2 = §103(a) over Perego‑422 + Amidi; Ground 3 = §103(a) over Ellsberry — [IPR2022‑00615 petition analysis].
• Amidi's FIG. 5 selection table and CPLD chip‑select generation — [IPR2018‑00364/‑00365 petition text, cmosedu.com].
• Amidi's motivation and "emulate a two rank memory module on the four rank memory module" language — same source.

4. Set A — face‑of‑patent citations, split by technical relevance

The front page lists ~50 U.S. patent documents, one foreign document, and at least one NPL item. Grouping them by the claim limitation they could touch is more useful than a flat list.

4a. Address re‑mapping / "phantom" density (touches the density‑multiplication claims)

4b. Bus switches / load isolation (touches the isolation‑device claims)

4c. Rank/bank select decoding (touches the decode logic)

4d. Memory‑device/buffering art (touches the "plurality of memory devices" + register/PLL elements)

US 5,699,542 A — Mehta et al. (1997‑12‑16); US 5,702,984 A — Bertin et al. (1997‑12‑30); US 5,703,826 A — Hush et al. (1997‑12‑30); US 5,745,914 A and US 5,802,395 A — Connolly et al. (1998‑04‑28; 1998‑09‑01); US 5,581,498 A — Ludwig et al. (1996‑12‑03); US 5,590,071 A — Kolor et al. (1996‑12‑31); US 4,392,212 A — Miyasaka et al. (1983‑07‑05); US 4,633,429 A — Lewandowski et al. (1986‑12‑30); US 4,961,172 A — Shubat et al.; US 4,980,850 A — Morgan; US 5,966,736 A — Gittinger et al. (1999‑10‑12); US 6,018,787 A — Ip (2000‑01‑25); US 5,963,464 A — Dell et al. (1999‑10‑05). [All titles unverified.] These are register/buffer/memory‑system background; none maps to the logic‑element claim as a §102 single reference.

⚠️ OCR reliability warning. The front‑page B‑list was retrieved in OCR form, and in several places the number and the inventor name appear to be offset by one line (for example, the front page shows 6,018,787 A 1/2000 Ip immediately before 6,070,217 A 5/2000 Connolly et al., while Unified Patents attributes the in‑line‑bus‑switch title to US 6,070,217 A). Verify each number↔inventor↔title pairing against the PDF before relying on any individual pairing in §4. This is exactly the kind of error the "interpret identifiers literally" rule is meant to catch — I am flagging the conflict rather than silently correcting it.

4e. Foreign patent document

4f. Non‑patent literature (NPL)

5. Consolidated §102 exposure map (against the C1 claim set)

6. Explicit uncertainty statements

1. No §102 anticipation has ever been adjudicated for the '912. All three IPR grounds were §103(a); the FWD decided on Ellsberry alone. Every "potentially anticipates" entry above is my technical assessment, not a holding.
2. The most relevant art is off the face of the patent. Amidi '152, Ellsberry '355, and Perego‑422 are Set B references; none appears in the front‑page "References Cited."
3. Which reference is "most relevant" depends entirely on the priority holding. Amidi (filed Jan 2004) qualifies as prior art regardless; Ellsberry (filed 2005‑06‑01) qualifies only if claim 16 is not entitled to the 2004‑03‑05 / 2004‑05‑28 provisionals — the exact issue argued on appeal in CAFC 24‑2304. If claim 16 gets 2004, Ellsberry drops out entirely and Amidi becomes decisive.
4. Perego‑422's filing/priority date is unverified. Its 2008‑04‑22 issue date is after the '912's 2004 priority, so §102(e) status depends on an earlier U.S. filing I could not confirm.
5. ~20 face‑of‑patent citations remain individually unverified (titles and, in some cases, number↔inventor pairings). I flagged the apparent OCR off‑by‑one conflict rather than guessing.
6. Claim‑number mapping for C1 claims 28/39/43 is provisional. The Certificate text I could retrieve fixed the amended set (1, 15, 16, 28, 39, 43) and 52–91 but did not let me pin which of 28/39/43 is the isolation claim.
7. Date contradiction carried forward (prompt 2026‑04‑26 vs. system 2026‑09‑28) and the unresolved 2004‑03‑04 vs. 2004‑03‑05 family priority discrepancy (Unified Patents vs. Google Patents).

Primary sources: US 7,619,912 B2 PDF, "References Cited" front page; US7619912B2 (Google Patents); PTAB IPR2022‑00615 Paper 96 (Apr 17, 2024), reference table and Grounds 1–3; IPR2022‑00615 petition analysis and Ex. 1036/1037 exhibits; Unified Patents patent page for 7619912 (98-item patent‑art list); US 2006/0117152 A1 (Amidi) family data; IPR2018‑00364/‑00365 petition text on Amidi; US reexamination certificate (E.D. Tex. 2:22‑cv‑00293 Dkt. 85‑2).

I'll research the prior art cited on the '912 record and in the PTAB proceedings, then build the §103 analysis.

Let me retrieve the "References Cited" list from the '912 record and the key primary references' details.

Obviousness Analysis — US 7,619,912 B2 ("Memory Module Decoder") under 35 U.S.C. § 103

Note on scope and sources. The Google Patents "Prior Art" section for US 7,619,912 records only the indexing keywords memory, memory module, signals, memory devices, ranks; I could not retrieve the full "Patent Citations / Cited By" tables (search limit reached). I therefore ground this analysis in (a) the references relied on in the patent's own reexaminations and IPRs, which are the operative prior art of record for §103, and (b) the reference disclosures reproduced in the PTAB/CAFC filings. I continue the numbering/claim caveats from the prior summary and flag contradictions inline.

1. Legal framework and the person of ordinary skill

Under Graham v. John Deere and KSR Int'l v. Teleflex, obviousness asks four things: scope/content of the prior art, differences from the claims, the level of ordinary skill, and objective indicia of non-obviousness. A combination is proper where the references are analogous, the modification is "a predictable variation," or there is an articulated reason (design incentive, market pressure, known technique, "obvious to try").

POSITA (as framed by the parties in IPR2022-00615): a person with a bachelor's degree in electrical engineering or computer science and roughly 3–5 years of experience designing memory modules, familiar with JEDEC DDR/DDR2 standards (JESD79, JESD79‑2, JESD21‑C) and with DRAM module architecture (ranks, chip-select signals, address/command buses, registered DIMMs, PLL/register/buffer devices). I state this as the parties' framework; I did not independently verify the Board's exact level-of-skill finding.

2. The prior art of record

3. Claim-by-claim §103 mapping

⚠️ Claim-numbering caveat (carried over from the prior summary): I do not have the issued claim set verbatim. The mappings below are anchored to the Summary of the Invention, the specification, and post-reexamination claim 16 as reproduced in PTAB Paper 96.

3.1 Claim 16 (the litigated independent claim)

The limitations break into: (a) PCB; (b) plurality of DDR devices in a first number of ranks; (c) a circuit comprising a logic element and a register, receiving input signals including row/column address, bank address, and chip-select signals configured for a second, smaller number; (d) generating output signals configured for the first, larger number; (e) responding to a command by selecting one or two ranks and transmitting the command to a device of the selected rank(s); (f) a PLL; (g) command transmitted to only one DDR device at a time.

(i) Ellsberry alone (Ground 3). This is the ground the Board sustained — claim 16 held unpatentable as obvious (FWD Paper 96, Apr. 17, 2024, summarized at fedcircuitblog FWD PDF):

• (a)/(b): Ellsberry's module/DIMM with DDR/DDR2 DRAMs ([0013]–[0017], ¶¶28–31).
• (c)/(d): control unit 204 is the "circuit"; its control block is the logic element, its address latches/mapping the register; it receives address, command and chip-select over the DIMM interface and outputs two chip-selects derived from one logical module address — i.e., an input set configured for fewer ranks controlling a larger physical set.
• (e)/(g): the control unit "causes the memory bank switch … to activate the correct memory bank" (Port A/B), and in the Fig. 12 single-chip-select configuration each bank holds one device, so a command reaches only one DDR device at a time.
• (f): external PLL 238 regenerating the module clock ([0030]).

Note the axis of dispute: Netlist contends "rank" requires a plurality of DRAMs, so Ellsberry can never satisfy (g); the Board construed "rank" to permit single-device ranks. That construction, and the priority question in §4 below, are the live issues on appeal.

(ii) Perego-422 alone / Perego-422 + Amidi (Grounds 1–2). The Board did not reach these (Ellsberry was dispositive), but the petition (IPR2023-00203 Petition) maps Perego's buffer (request/address logic + latches) to the logic-element/register circuit, its "independent target subsets" to ranks, and relies on Amidi for the explicit rank-multiplication input/output relationship. Because Amidi's CPLD expressly converts chip-selects for N ranks into chip-selects for 2N ranks, it supplies the one limitation Perego is weakest on.

3.2 The decoder independent claims (the rank-multiplication claims)

The broad independent claims require only: PCB + a plurality of memory devices + a logic element that (i) receives input control signals corresponding to a smaller number of memory devices/ranks and (ii) generates output control signals corresponding to the larger actual number.

• Amidi, alone or + JESD79/JESD79‑2/JESD21‑C, is a complete §103 case. Amidi teaches exactly the claimed input→output transformation using a logic device, and its stated purpose is to use cheaper lower-density DRAMs. This is not merely my inference: during the inter partes reexaminations (95/000,578; 95/000,579; 95/001,339), original claim 15 — the broad ancestor of claim 16 — was rejected as obvious over Amidi in view of certain JEDEC standards, which is what forced the amendments that produced the current claim 16. See Netlist's own concession and the reexamination history recounted in Appellees' brief (Netlist v. Samsung Response Brief). Any claim not carrying claim 16's added limitations is, on that record, squarely obvious.
• Ellsberry alone likewise teaches the smaller→larger "emulation" relationship ("a plurality of memory devices may appear as a single memory device to the operating system").
• Perego-422 + Amidi supplies the same limitation via the buffer/CPLD combination.

3.3 The method claim (couple module; input a first set of control signals for fewer ranks; generate a second set for more ranks)

The "coupling" step is conventional (JESD21‑C DIMM edge connector). The input/generate steps are the rank multiplication taught by Amidi (and Ellsberry). The additional instructions of the specification (row→column address translation, e.g., converting extra row address A13 into column address A12 for ×4 pairs) are shown in the patent itself to be routine address translation, and are also the kind of predictable address-mapping exercise Ellsberry's control unit performs ("map a received logical address to a physical address"). No non-obvious step remains once the decoder claims fall.

3.4 The means-plus-function claim

Under §112 ¶6 the "means" are the disclosed logic element (PLD/ASIC/FPGA/CPLD), register and switching structures. Amidi (CPLD), Ellsberry (control-unit ASIC) and Perego (buffer ASIC) each disclose a corresponding structure performing the recited function; the claim therefore rises and falls with the decoder claims.

3.5 The isolation-device claim (first/second device each with a data line and a data-strobe line; a common data line; an isolation device that alternately couples the first or the second data line to the common line)

This is the "BBARX"/data-bus-isolation claim. §103 case:

• Ellsberry discloses a memory bank switch (bidirectional drivers 402/404) that selectively couples one bank (Port A) or the other (Port B) to a shared data bus, and expressly states the switch "reduces resistive and/or capacitive loading of the data bus … while emulating a standard memory device interface" (¶31) and permits read/write to one bank "while sending no-operation commands to the other memory bank" (Summary [0010]). That is the claimed alternation, with the very motivation (load isolation + avoiding timing collisions) recited in the specification.
• Halbert supplies tristate buffers for enabling/disabling data paths, if Ellsberry's drivers are read narrowly.
• Motivation: the '912 specification itself frames the problem (post-amble vs. pre-amble collision on tied DQS lines, Fig. 5) and Amidi/Ellsberry both motivate load isolation.

Counter-argument to flag: Ellsberry ¶9 disparages FET switches as "too slow and imprecise to reliably comply with JEDEC standards" — Netlist argued this "teaches away." The Board treated that passage as directed at a different prior-art disclosure and note the isolation claims are not limited to FETs. This is a genuine, contestable point rather than a clean win for either side.

4. The dispositive preliminary question: prior-art status of Ellsberry

Every Ellsberry-based ground depends on Ellsberry being prior art, which depends on claim 16's effective filing date:

• Ellsberry was filed June 1, 2005. The '912's priority chain runs Mar. 5, 2004 (prov. 60/550,668 → '436 via 11/075,395) and Jul. 15, 2004 (prov. 60/588,244 → '386 via 11/173,175).
• The Board found the '244 provisional lacked written description of "bank address" signals, and the '436 patent lacked a "circuit comprising a logic element and a register," so claim 16 was not entitled to a pre-June-2005 date; Ellsberry therefore qualified at least under §102(e). See the FWD discussion quoted in the IPR2023-00203 institution decision (courtlistener) and Netlist's reply (Document-10).
• Consequence for §103: if the Federal Circuit reverses the priority ruling on appeal 24-2304, every Ellsberry ground collapses and the §103 case against claim 16 must rest on Perego-422 ± Amidi (Grounds 1–2), which the Board never reached.

5. Articulated motivations to combine (KSR)

The record supplies several independent, legally cognizable rationales:

1. Cost / price-per-bit arbitrage. The '912 specification itself states higher-density DRAMs cost "much more than twice the price of lower-density" devices — "there is an economic incentive for utilizing pairs of the lower-density DRAM devices." Micron's petition makes the same point as the primary motivation for Perego + Amidi. A motivation appearing in the challenged patent's own Background is strong evidence it was known.
2. Backward/forward compatibility and flexibility. Perego expressly touts a flexible buffer usable across memory generations; Amidi supplies the rank-multiplication interface. Combining them yields a module that works with a controller configured for a different device type — the stated goal of both.
3. Known technique / predictable result. Both references "disclose how to make a module with one type of memory devices and add an interface that can communicate with a memory controller configured to control a different type" (Petition §VI.A.1). Emulating 2N ranks from N chip-selects is a routine application of a known CPLD/buffer technique.
4. Design incentive/load management. Ellsberry's stated aim (reduce bus loading, avoid termination-cycle delays) independently motivates the isolation-device claim.
5. Industry standards as evidence of the ordinary artisan's knowledge. JEDEC JESD79/JESD79‑2/JESD21‑C show that bank-address and chip-select signals, DIMM edge connectors, and rank organizations were conventional, supplying any "gap" in the primary references (as the Board held in rejecting Netlist's argument that JEDEC compliance could not be drawn upon).

6. Objective indicia (secondary considerations)

• PTAB: the FWD stated there was "no objective evidence of non-obviousness" of record in IPR2022-00615.
• Netlist's countervailing evidence to weigh: (i) long-felt need / industry adoption — the May 23, 2024 E.D. Tex. jury found willful infringement by Micron and awarded ~$425M on the '912 (total $445M with the '417), and a Nov. 22, 2024 Samsung verdict added $118M; (ii) licensing — Samsung and SK hynix took licenses; (iii) copying — Google's early adoption. The classic defect in these arguments is nexus: the commercial success must be tied to the claimed invention rather than to Netlist's presence in a standard-driven market, and much of the verdict value flows through the DDR4 LRDIMM/RDIMM products rather than the claimed decoder alone. I cannot quantify the nexus evidence from the available materials.

7. Bottom line

• Claim 16: a legally sufficient §103 case exists on Ellsberry alone (sustained by the Board), with a fallback Perego‑422 + Amidi combination. Its validity turns on two contestable issues — the construction of "rank" and the priority/written-description ruling that makes Ellsberry prior art at all.
• All broader decoder/method/means claims: strong §103 case over Amidi + JEDEC, corroborated by the reexamination rejection of original claim 15.
• Isolation-device claim: defensible §103 case over Ellsberry (bank switch/drivers) + Halbert (tristate buffers), with a teaching-away defense (Ellsberry ¶9) that is genuinely arguable.

8. Explicit uncertainty statements

• I could not retrieve the full "Patent Citations"/"Cited By" lists from the Google Patents page for '912; the analysis above uses the prior art of record in the IPRs/reexaminations plus references cited on the patent's face (e.g., JESD79D).
• Claim text: the issued independent claims are not reproduced verbatim in the material available to me; the claim-by-claim mapping is anchored to the Summary of the Invention and to post-reexam claim 16 (Paper 96).
• Identifier note (no auto-correction): documents variously cite the Ellsberry reference as "US 2006/0277355" and, in at least one filing, as "2006/027355." I treat US 2006/0277355 A1 as the correct number but record the discrepancy.
• CAFC 24-2304 status: no merits decision was found in prior research; do not assume the §103 holdings above are final.
• The prior summary flagged a date discrepancy (prompt date vs. system date); I did not resolve it and rely only on the events the search results actually record.

Key sources: US7619912B2 (Google Patents); PTAB IPR2022-00615 FWD Paper 96 (fedcircuitblog); IPR2023-00203 institution decision (courtlistener); Micron petition (docketalarm); Netlist reply brief (fedcircuitblog); Netlist/Appellees response brief (fedcircuitblog); US 2006/0277355 A1 (Unified Patents); IPR2022-00615 petition analysis (ai-lab.exparte.com).