US 6100557

I'll search for authoritative information on this patent number, including any 2026 litigation activity.

Let me verify any recent PTAB/CAFC activity specific to this patent number.

US 6,100,557 — "Triple Well Charge Pump"

Search scope and caveats first. I searched for the literal identifier 6100557 and its punctuated form 6,100,557. I did not find any 2026 CAFC docket activity for this patent number, and I could not directly query USPTO PatentCenter or the CAFC docket system itself — so treat the "no 2026 appeal" conclusion as a negative search result rather than a database-verified clearance. Two near-miss hits are worth flagging because they are different patents and my rule is not to conflate them:

• IPR2025-01452 (SK hynix Inc. v. Advanced Memory Technologies LLC, filed Aug. 29, 2025; Director discretionary denial Jan. 9, 2026) concerns U.S. 7,777,557, not 6,100,557.
• A petition excerpt referring to a parent "which issued as the '557 patent (challenged in co-pending IPR2025-01452)" likewise traces to U.S. 7,777,557.
• A Brazilian design registration DI 6100557-6 (Nelson Aziby do Nascimento) surfaced in search; it is entirely unrelated.

Two docket items are genuinely tied to 6,100,557 per the patent record, but both are historical: ITC Inv. No. 337-TA-909 and IPR2014-01117 (petitioner Spansion; terminated by settlement, per the patent page's legal-events entry dated 2014-09-02).

Bibliographic data (authoritative, from the patent document)

Abstract (verbatim)

"An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently."

Plain-language overview of the independent claims

Claim 1 — the "triple well transistor in a charge pump" claim.
Build the charge pump in a semiconductor body of one conductivity type (P-type substrate), with a first well of that same type (P well) sitting inside a second well of the opposite type (deep N well) that surrounds it. Then provide a chain of pumping transistors that step a voltage up (or down, to a negative value) from first to last in response to clock signals, where the last transistor's output ends up meaningfully above — or negative relative to — the power supply. At least one of those transistors has its source and drain of the opposite conductivity type (N+) inside the P first well, and the first well, the second well, and the source region are all tied to a common potential. In practice this makes the isolated P well act as the body and creates an inherent PN diode between that P well and the N+ drain.

Claim 11 — the cross-coupled pumping-stage claim.
Same well architecture, but the claim focuses on the stage topology: multiple charge-pump stages in series, where at least one stage has a first transistor and a second transistor cross-coupled — the second transistor's gate connects to the first's drain, their sources connect to each other, and the second transistor's drain connects back to the first transistor's gate. Both transistors' source and drain regions sit inside the first (P) well, and the sources are coupled to that first well. This is the paired-transistor arrangement shown in FIG. 1 (e.g., transistors 102 and 106).

Claim 13 — the "every stage" cross-coupled claim.
Identical in substance to claim 11, except the well structure is recited as belonging to the respective charge pump stages in the plurality — i.e., each stage in the series has its own first (P) well and surrounding second (N) well, with the cross-coupled pair's sources tied to the first well. This is the broadest-per-stage variant of the concept.

Dependent claims in brief: claims 2–4 set the supply voltage range (≈5 V down to ≈1.5 V; specifically 3 V or 2 V); claims 5–6 set the clock frequency (above 10 MHz; approximately 22 MHz); claims 7–8 specify the last transistor's output is positive or negative, respectively; claims 9–10 add means for coupling the clock signals to the transistors, specifically a MOS transistor (the capacitor-connected transistors 112–119); claim 12 adds that the first and second wells are tied together with the sources.

The technical point of the invention

The disclosed advantage is twofold, and both flow from the same layout:

1. An inherent "extra diode." The P well–to–N+ drain junction is a parasitic diode that would normally be a liability. Here it is deliberately put to work as a low-resistance forward-conduction path that helps charge the next stage, so the pumping transistors' pass gates can be made smaller, reducing parasitic capacitance and power.
2. Suppressed body effect. Because the source, P well, and deep N well share a common potential, V_BS is clamped near the ~0.7 V junction cut-in instead of exceeding 10 V as in prior-art regulator NMOS pumps. That keeps threshold voltage low, so the transistors turn on faster and the pump can run at higher frequency — the specification states efficient operation at 22 MHz versus roughly 10 MHz for prior art, output ≈10.5 V from a 3 V supply (FIG. 1 positive pump) and ≈−8 V from a 3 V supply (FIG. 6 negative pump, which additionally uses P-channel capacitors 522–531).

Notes on scope and uncertainty

• The claim language uses "particular conductivity type" for the body/first well and "opposite conductivity type" for the second well and the source/drain. Read literally against the specification, this is the P-substrate / deep N well / P well / N+ source-drain NMOS stack of FIG. 3 — a triple-well NMOS. Claim 1 does not expressly require a P-type body or N-channel device, so I would not over-read the conductivity types beyond what the language states.
• Figures 5A–5C and Tables 2–5 are the specification's own comparative data (inventive triple-well pump vs. prior-art pump at 7.3 MHz and 22 MHz, at V_DD = 2 V and 3 V). The Tables 2 and 3 columns for V_out = 8 V appear internally inconsistent in the OCR'd text (e.g., "0.9" in Table 3 where Table 2 shows "0.1"); I would verify against the printed patent before relying on any single number.
• The '557 patent is expired as of Oct. 10, 2016, so it cannot be presently asserted, which is consistent with my finding of no active 2026 litigation for this number. It remains citable as prior art, and it is cited in later PTAB petitions (e.g., as the "Hung et al." triple-well reference discussed in the Halo LSI / related proceedings).

Sources: Google Patents, https://patents.google.com/patent/[US6100557A](/patent/US6100557A)/en; Justia, https://patents.justia.com/patent/6100557; USPTO/PTAB petition exhibit hosting the printed patent front page, https://www.docketalarm.com/cases/PTAB/IPR2014-01117/; EPO Global Patent Index family record for EP 0931379, https://data.epo.org/gpi/EP0931379A4.pdf.

I'll search litigation databases for US 6100557.

Now let me search for the ITC investigation outcome and related district court/CAFC proceedings.

Let me dig into the district court docket, the IPR termination, and the German proceedings.

Litigation involving US 6,100,557 ("Triple well charge pump," Macronix International Co., Ltd.)

Interpreted literally, US 6,100,557 (application 08/849,561; priority/filing 1996‑10‑10; granted 2000‑08‑08) is a Macronix patent. I found three related proceedings — one ITC Section 337 investigation, one PTAB inter partes review, and a German infringement action — all of which were resolved in a single January 2015 global settlement between Macronix and Spansion. I found no CAFC appeal, no ANDA case, and no other litigation involving this patent.

1. ITC Investigation No. 337‑TA‑909 — Certain Non‑Volatile Memory Devices and Products Containing Same

Sources: USITC notice of investigation, https://www.usitc.gov/secretary/fed_reg_notices/337/337_909_notice01282014sgl.pdf and 79 FR 6227 (Feb. 3, 2014), https://regulations.justia.com/regulations/fedreg/2014/02/03/2014-02154.html; partial termination as to Tellabs, https://www.govinfo.gov/content/pkg/FR-2014-09-10/pdf/2014-21484.pdf; Spansion Form 10‑K disclosure (trial dates, IPR filings, settlement effective Jan. 22, 2015), http://business.bigspringherald.com/bigspringherald/action/getedgarpdf?accesscode=143774915002287; Google Patents litigation link for this patent, https://portal.unifiedpatents.com/litigation/International%20Trade%20Commission/case/337-TA-909.

2. PTAB Inter Partes Review — IPR2014‑01117

Companion petitions filed the same day against the other two patents asserted in the 909 investigation: IPR2014‑01118 (U.S. 6,002,630) and a further petition on U.S. 6,552,360. Sources: https://natlawreview.com/article/pto-litigation-center-report-july-22-2014 (filing date 7/21/2014; patent owner Macronix; petitioner Spansion entities; status "Pending"); docket copy at https://www.docketalarm.com/cases/PTAB/IPR2014-01117/Inter_Partes_Review_of_U.S._Pat._6100557/; joint motion to terminate in the parallel '630 IPR describing the common settlement, https://www.docketalarm.com/cases/PTAB/IPR2014-01118/Inter_Partes_Review_of_U.S._Pat._6002630/docs/01-28-2015-Patent_Owner/Motion-18-Joint_Motion_to_Terminate_Proceeding.pdf.

Note the Google Patents sidebar attribute for this patent: "PTAB case IPR2014‑01117 filed (Settlement)" — https://patents.google.com/patent/US6100557/en.

3. German infringement action (European counterpart of the '557 patent)

Macronix filed a patent infringement complaint against Spansion in Germany; the patent asserted there was described by Spansion as "the European counterpart of the '557 patent." Spansion's July 21‑22, 2014 announcement confirms this filing in connection with the same dispute. The January 27, 2015 settlement announcement expressly covers "Macronix's patent infringement complaint against Spansion in Germany," with all patent cases dismissed worldwide.

• Plaintiff: Macronix (Macronix International Co., Ltd.)
• Defendant: Spansion (Spansion Inc./Spansion LLC group)
• Jurisdiction: Germany (specific court, venue and case number were not identified in the sources I was able to retrieve — I will not guess)
• Filing date: on or about mid‑July 2014 (announced July 22, 2014)
• Outcome: settled and dismissed as part of the January 2015 global settlement.

Sources: Spansion press release, https://epsnews.com/2014/07/22/spansion-challenges-macronix-claims/ (and mirrored PRNewswire release); Macronix/Spansion joint settlement announcement, Jan. 27, 2015, https://www.mxic.com.tw/en-us/about/news/Pages/201501004.aspx. The likely European family member listed on Google Patents is EP 0 931 379 B1 ("Triple well charge pump") at https://patents.google.com/patent/US6100557/en — this is the patent I would expect to be the German action's counterpart, but the sources I retrieved do not state the EP number for the German suit, so treat that identification as probable, not confirmed.

4. Related U.S. district court actions — status and a caveat

• Macronix International Co., Ltd. v. Spansion Inc. et al., N.D. Cal. No. 4:14‑cv‑01890 (transferred from E.D. Tex. No. 3:13‑cv‑679; transfer effective April 28, 2014; asserted seven Macronix patents). The case was stayed (order Dec. 12, 2014, Judge Beth Labson Freeman) pending ITC Investigation No. 337‑TA‑922, and was resolved by the January 2015 global settlement. Caveat: the sources I retrieved do not identify which seven patents were asserted in this docket, so I cannot confirm that the '557 patent was one of them. Source: https://www.courtlistener.com/opinion/[7305143](/patent/7305143)/macronix-international-co-v-spansion-inc/; https://unicourt.com/case/rc-db1-macronix-international-co-ltd-v-spansion-inc-et-al-[155677](/patent/155677).
• Spansion LLC v. Macronix International Co., Ltd. et al. (N.D. Cal.) and the parallel ITC investigations 337‑TA‑893, ‑910 and ‑922 asserted Spansion's patents (e.g., U.S. 6,369,416; 6,900,124; 7,018,922; 6,459,625; 7,151,027; 6,731,536; and '826, '757, '324, '330) — not the '557 patent. These were dismissed by joint stipulation (e.g., N.D. Cal. C 13‑cv‑03566‑VC, dismissal order Jan. 30, 2015; and the 337‑TA‑910 termination by settlement, 80 FR notice of March 12, 2015, https://www.govinfo.gov/content/pkg/FR-2015-03-18/pdf/2015-06172.pdf). They are context for the same corporate dispute but do not assert the '557 patent.

Summary of outcomes

Bottom line: US 6,100,557 was asserted by Macronix against Spansion in ITC Investigation No. 337‑TA‑909 (claims 1‑3, 7, 9‑13), challenged by Spansion in PTAB IPR2014‑01117, and asserted (via its European counterpart) in a German action. All three were resolved by the Macronix–Spansion global settlement announced January 27, 2015; there is no final merits ruling, no exclusion order, no IPR final written decision, and no appellate decision on this patent that I could locate. The patent itself expired 2016‑10‑10 (anticipated expiration, per Google Patents).

I'll start by reconciling the structured ODP block against the proceeding identifiers visible in the patent's own legal-events history, then verify each with web sources.

Now let me pin down the procedural posture of IPR2014-01117 — specifically whether it was ever instituted, the termination judgment, and the panel.

Strong result — I found a real IPR (IPR2014-01117) that the ODP block missed. Let me verify the petition grounds and confirm whether any other proceedings exist on this patent.

⚠️ Threshold discrepancy — flagged before anything else

The structured "PTAB proceedings on file" block states the USPTO ODP feed returns no AIA trial proceedings for US 6,100,557. That is not accurate as a historical matter. This patent's own Google Patents legal-events history records:

2014-09-02 | IPR | Aia trial proceeding filed before the patent and appeal board: inter partes review — TRIAL NO: IPR2014-01117 — Opponent name: SPANSION, INC., SPANSION LLC SPANSION (THAILAND)

and the litigation tag PTAB case IPR2014-01117 filed (Settlement). Web sources confirm a real, docketed PTAB proceeding. IPR2014-01117 exists. The ODP "no proceedings" result is almost certainly a coverage gap for pre-institution, settled-and-terminated 2014-era proceedings — precisely the category that tends to fall out of modern ODP AIA-trial datasets. I am using the confirmed proceeding below, and flagging the ODP entry as unreliable rather than treating it as canonical.

Proceedings overview

Total count: 1 AIA trial proceeding on US 6,100,557 — IPR2014-01117 (Spansion v. Macronix), status settled/terminated before institution; 0 claims invalidated, 0 claims sustained on the merits, 0 institution denials on the merits, 0 active proceedings.

Bottom-line defensive posture: the PTAB never touched this patent's claims. There is no canceled or narrowed claim to point to and no FWD to cite — but that cuts against a PTAB-based defense, not for it. The only validity ruling ever issued was none. A defendant's real leverage here is not PTAB history; it is that the patent expired on 2016-10-10 (20 years from the 1996-10-10 PCT filing, per the Google Patents legal-status field), which collapses the § 286 damages window for any complaint filed today. The settled IPR is valuable as a prior-art roadmap, not as an invalidity judgment.

IPR2014-01117 — Spansion Inc., Spansion LLC, and Spansion (Thailand) Ltd. v. Macronix International Co., Ltd.

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2014-07-21 (Notice of Filing Date Accorded to Petition issued 2014-07-31, Paper 6)
• Status: Terminated — settled. Verbatim from the Board's judgment (Paper 13, 2015-01-29): "This case is in the preliminary proceeding stage; no institution of a trial has been made." Plain English: the petition was never instituted; no trial ever began; no claim was adjudicated.
• Judge panel: Michael P. Tierney (writing), Kalyan K. Deshpande, and Peter P. Chen, Administrative Patent Judges.
• Petition grounds: The petition challenged claims 1‑3, 7, and 9‑13 of the '557 patent (per Spansion's own SEC Form 10-Q: "On July 21, 2014, Spansion Inc., Spansion LLC, and Spansion (Thailand) Ltd. filed a petition for inter partes review of claims 1-3, 7, and 9-13 of U.S. Patent No. 6,100,557"). As an IPR, the statutory basis was limited to § 102 anticipation and/or § 103 obviousness over patents and printed publications. Dozens of exhibits were filed on 2014-07-21, including US 5,394,365 (Tsukikawa), US 5,489,870 (Arakawa), US 5,502,629, US 5,297,097, US 5,673,232, US 5,422,586, US 5,455,532, US 5,734,290, US 5,973,979, EP 629,047, a Tsukikawa et al. back-bias-generator article, Xilinx Low Voltage Systems (Feb. 1995), and dictionary excerpts. Caveat: the exhibit list does not establish which reference maps to which ground, and I have not verified a ground-by-ground mapping. Because no institution decision issued, no ground was ever construed, briefed to decision, or adjudicated.
• Institution decision: None issued. The joint motion to terminate landed on 2015-01-28, inside the window for the Board's decision on institution (the § 314(b) deadline ran from the 2014-07-31 accorded filing date); the Board entered judgment the next day without ever deciding institutiality.
• Final Written Decision: None. No FWD was ever issued. Nothing in the record cancels, confirms, or construes a single claim of US 6,100,557. Anyone who tells you a PTAB panel invalidated or upheld these claims is wrong.
• Settlement / termination: On 2015-01-28 the parties filed a Joint Motion to Terminate Proceeding (Paper 11) and a Joint Request to File Settlement Agreement as Business Confidential Information (Paper 12; settlement agreement filed as Ex. 1026). On 2015-01-29 the Board granted both under 35 U.S.C. § 317 and 37 C.F.R. §§ 42.73, 42.74, ordering the settlement kept separate from the patent file. The monetary terms are confidential. Context: Spansion's SEC filings state the broader dispute (including ITC Inv. No. 337-TA-909, where Macronix asserted claims 1‑3, 7, and 9‑13 of the '557 patent) was settled effective 2015-01-22 by a settlement agreement between the parties. Spansion then filed a Petitioner's Request for Refund (Paper 14, 2015-02-06) and the Board issued a Notice of Refund (Paper 15, 2015-02-11) — the classic signature of a pre-institution settlement.
• Appeal: None. There was no FWD to appeal. I found no Federal Circuit docket or opinion involving the '557 patent. The PTAB track here ended at the Board.
• Defensive value: Nothing is canceled, so there is no quick-kill citation. But the petition is a fully public, Spansion-funded invalidity workup aimed at exactly the claims Macronix commercially asserted (1‑3, 7, 9‑13) — free ammunition to re-brief in district court, where IPR estoppel does not apply to Spansion (and § 315(e) estoppel never attached at all, because the IPR was never instituted and produced no FWD — estoppel requires institution and a final written decision).

Sources: Board judgment PDF (Docket Alarm): https://www.docketalarm.com/cases/PTAB/IPR2014-01117/Inter_Partes_Review_of_U.S._Pat._6100557/docs/01-29-2015-Board/Termination___Settlement-13-Judgment.pdf · Patexia docket for IPR2014-01117: https://services.patexia.com/lawsuits/Spansion-Inc-et-al-v-Macronix-International-Co-Ltd-id-63428/documents/sort_by/created/sort_dir/desc · Spansion 10-Q (petition scope, claims 1‑3, 7, 9‑13): https://getfilings.com/sec-filings/141107/Spansion-Inc_10-Q/#6 · ITC Notice of Institution, Inv. No. 337-TA-909: https://www.usitc.gov/secretary/fed_reg_notices/337/337_909_notice01282014sgl.pdf · Spansion press release / EE Times: https://www.eetimes.com/spansion-challenges-macronix-claims/ · PTAB E2E portal (case lookup): https://ptab.uspto.gov

Strategic summary

Claim status: everything is UNTESTED; nothing is canceled. US 6,100,557 issued with 13 claims (independents 1, 11, and 13; dependents 2‑10 and 12). The only challenge ever mounted — claims 1‑3, 7, 9‑13, the same set Macronix asserted at the ITC — died at the preliminary stage by settlement. Claims 4‑6 were never even challenged. For a defendant, that means there is no claim-level kill shot from the PTAB; the entire claim set remains live and presumptively valid under § 282. The offsetting reality is term: per the Google Patents legal-status record the patent's anticipated expiration was 2016-10-10, with maintenance fees paid through the year‑12 window (2011-09-22), so this is a lapsed-by-term, not lapsed-for-fee, patent. On a complaint filed in 2026, § 286's six-year lookback reaches only post-expiration conduct — damages exposure is effectively nil absent an already-pending, earlier-filed case. Treat any present-day demand letter citing 6,100,557 as a pre-expiration-accrual or licensing-shakedown posture, not a live injunction threat.

Estoppel landscape: essentially none, in either direction. Under 35 U.S.C. § 315(e)(2), estoppel bars a petitioner from raising, in a civil action, grounds it raised or reasonably could have raised only where the IPR was instituted and "results in a final written decision under section 318(a)." Neither condition is satisfied here — the Board expressly found "no institution of a trial has been made" — and § 317(a) confirms that no estoppel attaches to a petitioner whose proceeding is terminated by settlement. So Spansion was never estopped, and every ground in its 2014 petition (including the ground-by-ground mappings the Board never reached) remains fully available to be re-run in district court. Conversely, Spansion's pre-institution art cannot be used to infer claim scope: there is no institution decision, no POPR analysis made public in adjudicated form, and no FWD construction to borrow. If you are a Spansion successor or privy, you also face no adverse estoppel — you are free to file a fresh IPR, though the expired term makes that exercise academic unless you need an invalidity judgment for a pending pre-2016 damages case.

Pattern signals. Repeat petitioner: No — one petition only on this patent. Spansion did, however, file a coordinated three-patent salvo against Macronix in July 2014, hitting the other two patents Macronix asserted in the same ITC action (the '360 and '630 patents, per Spansion's 10-Q and press release). That was a single litigation-driven campaign, not serial harassment of the '557 patent. Aggressive PO appellate behavior: No — Macronix never obtained an appealable FWD on this patent; the '557 PTAB track produced zero precedential or appellate rulings. Defensive aggregator: No. The portal.unifiedpatents.com link in the Google Patents record is Unified Patents' litigation database merely hosting the IPR2014-01117 docket entry — Unified was not a petitioner and is not in the chain of title or privity. Do not mistake that data-provider link for aggregator involvement. Corporate context worth noting for privity analysis (and I flag it as background rather than docket-verified): Spansion was acquired by Cypress Semiconductor in 2015, and Cypress was in turn acquired by Infineon Technologies in 2020 — so "petitioner/privy" arguments today would run through that acquisition chain, though it is moot given that no estoppel attached.

Recommended next steps

• Do not brief a PTAB-invalidity defense. There is no FWD and no cancellation order to quote. The single Board document that matters is the 2015-01-29 Judgment (Paper 13), which says only that the case settled pre-institution: "This case is in the preliminary proceeding stage; no institution of a trial has been made … the joint motion to terminate the proceeding is GRANTED … the proceeding is TERMINATED." Quote that to rebut any assertion that the patent was "PTAB-validated" or "PTAB-invalidated" — both are false.
• Lead with the expiration + § 286 argument. Confirm the expiration date against the USPTO PatentCenter maintenance-fee and expiration screens (https://patentcenter.uspto.gov) before relying on it, but if 2016-10-10 holds, any complaint filed in 2026 can recover only for acts on or after roughly 2020-09-30 — all after expiry. That is a Rule 12(b)(6) / summary-judgment dispositive issue on damages, and often a reason to refuse a nuisance settlement outright.
• Mine the settled petition as your invalidity workup. Request the IPR2014-01117 file via PTAB E2E and pull Petition Paper 4 plus Exhibits 1001‑1025 (US 5,394,365; US 5,489,870; US 5,502,629; US 5,297,097; US 5,673,232; US 5,422,586; US 5,455,532; US 5,734,290; US 5,973,979; EP 629,047; the Tsukikawa back-bias article; Xilinx Low Voltage Systems (1995)). Two of these — US 5,394,365 (Tsukikawa) and US 5,489,870 (Arakawa) — are the same references cited on the face of the patent by the examiner, which makes them strong § 102/§ 103 candidates in any surviving pre-2016 damages case. Note also that the '557 patent's own specification concedes the extra-diode/body-effect mechanics, and the asserted claims were drafted around "common potential" of first well, second well, and source — a narrowness worth attacking on written description and indefiniteness in parallel.
• No active proceedings, so no trial-stage milestones to track. There is no institution-decision deadline, no oral hearing date, and no statutory one-year FWD deadline running. Reliance on the ODP "no PTAB activity" feed is unsafe for this patent; if you need a certified negative, order the full file history from PTAB E2E and confirm no later-filed petition exists — my two independent checks (Google Patents' "Family has litigation" tag and the ODP feed) both surface only IPR2014-01117.
• Cross-check the parallel tracks before relying on this summary. The same dispute also ran through the ITC (Inv. No. 337-TA-909, asserted claims 1‑3, 7, 9‑13 of '557, settled 2015-01-22), N.D. Cal. (Case No. 4:14-cv-01890 and related), Germany (European counterpart EP 0 931 379 B1), and the JA/KR family members (JP3415854B2, HK1021268B). Confirm the settlement's scope and whether any covenant-not-to-sue or license touches your product — that agreement (Ex. 1026) was granted business-confidential treatment and is not public.

Confidence notes: The proceeding number, parties, filing date, panel, termination date and pre-institution posture are high confidence (Board judgment text). The challenged claim set (1‑3, 7, 9‑13) is high confidence (Spansion SEC filing). The exhibit list is high confidence but the ground-by-ground art mapping is NOT verified — I have deliberately not assigned references to grounds. The 2015-01-22 settlement effective date comes from a Spansion SEC filing as reproduced by a secondary source (medium-high). The 2016-10-10 expiration date comes from the Google Patents legal-status field and is consistent with a 20-year term from the 1996-10-10 PCT filing (medium-high — verify at PatentCenter). Cypress/Infineon acquisition chain is general background knowledge, not docket-verified here.

I'll research the assignment record and litigation history for US 6100557 before assembling the report.

Let me check for any post-issuance assignments and the correspondence/assignment recording details.

Ownership & Assignment Reconstruction — US 6,100,557

"Triple well charge pump" · App. 08/849,561 (PCT/US1996/016317 national stage) · Filed 1996-10-10 · Issued 2000-08-08 · Priority 1996-10-10 · Status: Expired – Lifetime (anticipated expiration 2016-10-10)

Sourcing note / limits on this reconstruction: The USPTO Assignment Center requires an interactive session and could not be queried directly for this analysis. The assignment data below is taken from the Google Patents legal-events mirror (which reproduces the Assignment Center's reel/frame, conveyance, assignor/assignee and execution dates) plus the patent's own front page and the ITC/PTAB public record. Critically, the "correspondent of record" field — the attorney/firm that filed each recording — was not exposed in any source I could reach. I have not fabricated it. Where the patent names a prosecution attorney, I have flagged that separately and explicitly as a different field.

Inventors

• Employer attribution is inferred, not recorded: the front page lists no assignor employers, and there is no separate employment/assignment instrument in the visible record other than the inventors→Macronix assignment itself (reel 009394/0130). The inference rests on two facts: the assignment executed within ~6 months of the §371 filing names the inventors personally as assignors to Macronix, and inventor Wan recurs as a named inventor on later Macronix filings (e.g., US 6,285,240, also assigned to Macronix).
• Unusual-pattern check: not present. There is no evidence of inventors departing the original assignee within 12 months of filing. To the contrary, the same inventor group/colleague appears on subsequent Macronix applications, indicating retention. There is therefore no fire-sale precursor pattern in the inventor data.

Original assignee

Macronix International Co., Ltd. — No. 16, Li-Hsin Road, Science Park, Hsin-Chu, Taiwan. Front page assignee of record; current assignee per Google Patents legal events.

• Primary business: Integrated device manufacturer (IDM) of non-volatile memory — Mask ROM / XtraROM® (worldwide #1 ROM share since 1999) and NOR Flash (top-3 globally; #1 in Serial NOR in the mid-2010s). Founded December 1989 in the Hsinchu Science Park; listed on the Taiwan Stock Exchange (TWSE: 2337) since March 1995.
• Did they ship a product embodying the claims? Yes. The patent is directed to on-chip charge pumps used for erasing/programming non-volatile memory; Macronix designs and fabricates NVM in its own fabs (Fab 2 8-inch, Fab 5 12-inch) and asserted the patent on the strength of its own US manufacturing/licensing activity ("industry in the United States" showing in ITC No. 337-TA-909). Macronix is uncontroversially an operating company, not a licensing vehicle.
• Current status: Operating. Macronix remains an active public company and NVM supplier; no bankruptcy, dissolution, or acquisition of the assignee was found.

Assignment timeline

There is exactly one recorded assignment in the chain. No post-issuance transfers of any kind (no security agreements, mergers, name changes, or licensing-only LLC conveyances) appear on the patent.

• 1997-03-27 to 1997-04-22 (executed; signing dates per the recorded instrument) / recorded 1997-05-12 — Reel 009394 / 0130
  • Conveyance: Assignment of assignors' interest (standard "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: Chun-Hsiung Hung; Ray-Lin Wan; Yao-Wu Cheng (individually)
  • Assignee: Macronix International Co., Ltd. (Hsinchu, Taiwan)
  • Correspondent: Not available in the sources queried. The Assignment Center correspondent field for reel 009394/0130 was not retrievable. Separately — and this is not the assignment correspondent — the patent's front-page attorney/agent/firm of record is reported as Mark A. Haynes (patent prosecution counsel, carried forward from the PCT/national-stage prosecution). Do not treat the prosecution attorney as the recording correspondent without confirming against the Assignment Center entry for 009394/0130.
  • Context: Ordinary inventor-to-company assignment at national-stage entry — this is the initial ownership instrument, not a corporate transaction.

No further assignments recorded. Post-issuance legal events are maintenance-fee payments only (4-year 2004-02-09; 8-year 2007-12-03; 12-year 2011-09-22), consistent with the patent remaining in Macronix's hands through expiry on 2016-10-10. Under the Assignment Center's own logic, the absence of transfers means the original assignee (Macronix) still owns the patent.

Non-assignment legal events relevant to ownership/assertion

• 2013-12-27 / 2013-12-31 — Macronix International Co., Ltd. and Macronix America, Inc. file an ITC §337 complaint against Spansion and downstream respondents.
• 2014-01-28/29 — ITC institutes Inv. No. 337-TA-909, asserting inter alia claims 1–3, 7, and 9–13 of the '557 patent (alongside US 6,552,360 and US 6,002,630).
• 2014-07-21 — Spansion, Inc.; Spansion LLC; and Spansion (Thailand) Ltd. petition for IPR2014-01117 against the '557 patent (petition filed 7/21/2014; proceeding logged 2014-09-02).
• 2015-01-29 — PTAB Judgment terminating IPR2014-01117 following a joint motion to terminate based on settlement; the ITC investigation is likewise terminated on settlement (Commission notice published 2015-03-18).
• 2016-10-10 — Anticipated expiry; patent now expired.

Timeline diagram

timeline
    title Ownership of US 6100557
    1996 : PCT application filed by Macronix
    1997 : Inventors assign rights to Macronix
         : Reel 009394 Frame 0130 recorded
    2000 : US 6100557 issues to Macronix
    2013 : Macronix files ITC complaint vs Spansion
    2014 : ITC probe 337-TA-909 instituted
         : Spansion files IPR2014-01117
    2015 : Spansion and Macronix settle
    2016 : Patent expires 10 October

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The chain contains no transfer to a licensing-only entity. The sole recorded conveyance (reel 009394/0130, recorded 1997-05-12) runs from the three individual inventors to the operating company Macronix. No "IP / Holdings / Licensing / Ventures" assignee appears anywhere on this patent.

2. Known asserter in the chain — not present. The assignee of record is Macronix International Co., Ltd., an operating NVM IDM. It does not appear on Acacia / Marathon / Intellectual Ventures / Wi-LAN / Conversant / Pendrell / Round Rock or comparable high-frequency-plaintiff lists. The assertion history here is a genuine competitor dispute — Macronix (complainant) v. Spansion (respondent), plus Spansion's reciprocal ITC action (invoked in the March 2015 Commission notice) — not an NPE campaign.

3. Repeat correspondent across the chain — not present / insufficient data. With only one assignment link, recurrence cannot be established. The sole recorded instrument's correspondent field could not be retrieved from the sources queried, so I cannot name an attorney or firm of record for it. Reporting the prosecution attorney of record (reported as Mark A. Haynes) as the assignment correspondent would be a category error; it is flagged here only so the distinction is not lost.

4. Cascading transfers — not present. One assignment, executed 1997, recorded 1997. Zero chained LLC transfers; zero transfers in the 2013–2014 pre-litigation window or at any other time.

5. Pre-litigation transfer — not present. The patent was assigned to Macronix in 1997 and asserted by Macronix itself 16+ years later in its own name. No assignment falls within 6 months before the ITC complaint (2013-12-27) or the IPR petition (2014-07-21).

6. Bankruptcy fire-sale — not present. No sale of this patent in any insolvency proceeding was found. Caveat to avoid a false positive: Spansion — the adversary in 337-TA-909, and the IPR petitioner — did file Chapter 11 in 2009 and emerged in 2010. That is Spansion's bankruptcy, not the patent owner's, and it did not produce a transfer of US 6,100,557. Do not read the Spansion bankruptcy into this chain.

7. Privateering — not present. Macronix asserted the patent directly, as named complainant, together with its wholly owned US subsidiary Macronix America, Inc. No NPE was interposed to assert on Macronix's behalf; there is no assignment to a third-party assertion vehicle and no evidence of a back-end licence arrangement structuring a proxy suit.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. (Note: Unified Patents hosts data about the IPR2014-01117 docket at https://portal.unifiedpatents.com/ptab/case/IPR2014-01117; that is a database listing for the Spansion-filed IPR, not a Unified Patents ownership interest in the patent.)

Verdict

Operating-company assertion.

Macronix International Co., Ltd. — an operating NVM IDM that designs and fabricates its own ROM and NOR Flash products — acquired the '557 patent by inventor assignment at reel 009394/0130 (executed March–April 1997, recorded 1997-05-12) and held it unbroken through expiry on 2016-10-10, with no intervening transfer of any kind. It then asserted the '557 patent in its own name at the ITC (Inv. No. 337-TA-909, instituted 2014-01-28/29, asserting claims 1–3, 7 and 9–13) against a direct competitor, Spansion, and its downstream customers; Spansion counter-petitioned for IPR (IPR2014-01117, filed 2014-07-21) and the parties settled in January 2015. Every NPE indicator is absent, and several would have required a post-issuance assignment that simply does not exist on this patent.

Note for downstream use: the patent expired 2016-10-10 and any maintenance-fee lapse/expiry means it can no longer support assertion; and the chain, per the single recorded instrument at reel 009394/0130, has never left Macronix.

Verify at: https://assignmentcenter.uspto.gov/ (search patent 6,100,557) · mirror: https://assignment.uspto.gov/patent/index.html · patent record: https://patents.google.com/patent/US6100557/en

If you need the missing correspondent of record for reel 009394/0130 confirmed, that single field must be pulled from the Assignment Center result page for that reel/frame — it is the one data point I could not verify from public secondary sources.

I'll verify the patent and its cited prior art against live sources rather than relying on the earlier sections.

Now let me verify the two EP references and check a discrepancy I noticed in the printed front page.

Prior-Art Analysis — US 6,100,557 ("Triple Well Charge Pump")

1. Identification of the patent (literal-number check)

I searched the literal string 6100557 and the punctuated form 6,100,557. Results confirm a single match to the target patent; I explicitly discarded the unrelated near-misses flagged in the earlier section (US 7,777,557 / IPR2025-01452; Brazilian design DI 6100557-6).

Primary sources: Google Patents https://patents.google.com/patent/US6100557A/en; the printed front page reproduced as Exhibit 1001 in IPR2014-01117 (https://www.docketalarm.com/cases/PTAB/IPR2014-01117/.../Exhibit-1001-US_Patent_No__6,100,557.pdf); WO 98/16010 (https://patentimages.storage.googleapis.com/9b/ba/f0/b18b6d8e8a6d52/WO1998016010A1.pdf).

⚠️ Discrepancy to flag. The earlier section listed five cited references. The printed front page (Exhibit 1001) actually shows a sixth U.S. reference — US 5,612,921 (Chang et al., 3/1997, cl. 257/399) — which does not appear in Google Patents' machine-readable "Patent Citations (5)" list. The two lists therefore disagree by one entry. Both lists agree on the other five. I did not have a search step left to retrieve the substance of US 5,612,921, so its disclosure is unverified below.

2. The six references cited on the face of US 6,100,557

Every cited reference was published/filed before the Oct. 10, 1996 priority date, so each is facially available as prior art under pre-AIA § 102(a)/(b) (and § 102(e) for the U.S. patents). Critically, all six are "References Cited" considered by the examiner; none was applied to reject the claims, and the patent issued with all 13 claims intact. Any "anticipation" below is therefore a hypothetical re-analysis, not the prosecution record.

(i) US 5,394,365 — Tsukikawa, Mitsubishi Denki K.K.

• Full citation: U.S. Patent 5,394,365, "Charge pump circuit having an improved charge pumping efficiency," filed Apr. 16, 1992, issued Feb. 28, 1995 (cl. 365/189.09).
• Disclosure: Charge pump (negative substrate bias or positive boosted voltage) in which a junction diode is formed in a well region of a first conductivity type surrounded by a semiconductor layer of the second conductivity type, and isolated from every other device region; the well provides the diode's anode or cathode (claims 18–20). Bulks of the diode-connected MOS transistors are tied to the output node to keep the bulk–source junction reverse-biased.
• § 102 assessment: This is the closest structural reference to claim 1 — it discloses the isolated-well-surrounded-by-opposite-type-layer architecture (claim 1 elements "first well" + "second well surrounding") inside a charge pump. However, claim 1 additionally requires at least one of the pumping transistors to have its source and drain of the opposite type formed in the first well, with the first well, second well and source region all at a common potential. Tsukikawa's isolated well houses the diode, and its bulk is biased to the output, not commonly tied with source/wells.
  Claim(s) potentially implicated: claim 1 (and, by structural analogy only, claims 2–10 as dependents). In my view this is realistically a § 103 reference, not a clean § 102 anticipation.

(ii) US 5,489,870 — Arakawa, Sony Corp.

• Full citation: U.S. Patent 5,489,870, "Voltage booster circuit," filed Mar. 18, 1993, issued Feb. 6, 1996 (cl. 327/536).
• Disclosure: Booster circuit using an n-well 132 formed in the substrate with an n⁺ diffusion layer 134, i.e., a well-based booster charge-transfer arrangement.
• § 102 assessment: Discloses a well-based voltage booster, but not the triple-well source/drain-in-first-well/common-potential transistor, and not the cross-coupled two-transistor stage of claims 11/13. No claim is anticipated on the retrieved record. Best characterized as background/§ 103 art bearing on claim 1's general "semiconductor body + wells + pumping transistors in response to clocks" environment.

(iii) US 5,502,629 — Ito et al., Fujitsu Ltd.

• Full citation: U.S. Patent 5,502,629, "DC-DC converter," priority Mar. 31, 1994, issued Mar. 26, 1996 (cl. 363/60). 15 claims. (A related Fujitsu filing, US 5,245,524 to Nakagawa/Ito, appears as a same-family-style charge-pump DC-DC converter.)
• Disclosure: Charge-pump-type DC-DC converter with four MOS switches and two capacitors. A variable voltage is applied to the back gate of a selected MOS transistor; when that transistor is ON a control transistor ties its source to its back gate (lowering on-resistance); when OFF the back gate is driven to prevent a parasitic bipolar transistor from turning on. FIG. 14 shows an N-well back gate in a P-substrate with source/drain formed therein (conventional, single-well — not triple-well).
• § 102 assessment: This is the most relevant cited reference on the "source and body at the same potential" concept (claim 1 element "source region … coupled to a common potential"; claim 11/13 "sources … coupled to the first well"). But it lacks the second well surrounding the first well (triple-well stack) and the cross-coupled stage topology.
  Claim(s) potentially implicated: claim 1 (common-potential body concept, in combination); realistically § 103, not anticipation, because the "second well surrounding said first well" limitation is absent.

(iv) US 5,612,921 — Chang et al.

• Full citation (from the printed front page only): U.S. Patent 5,612,921, Chang et al., issued Mar. 1997, cl. 257/399.
• Disclosure: Not verified. My retrieval step budget was exhausted before I could pull this reference.
• § 102 assessment — caveat: Because its issue date (Mar. 1997) post-dates the Oct. 10, 1996 priority date, it can only qualify as prior art under pre-AIA § 102(e) (U.S. patent granted on an application filed before the applicant's invention), which would require confirming its filing date. I could not confirm that. Treat this entry as open/unresolved, not as an anticipation candidate. Note also that Google Patents' citation list omits it — see the discrepancy flag above.

(v) EP 0 319 063 A2 — N.V. Philips' Gloeilampenfabrieken

• Full citation: European Patent Application EP 0 319 063 A2 (granted as EP 0 319 063 B1), "Voltage multiplier circuit and rectifier element," priority Nov. 17, 1987, published June 7, 1989. (Google Patents: https://patents.google.com/patent/EP0319063B1/en)
• Disclosure (verified): A voltage multiplier (charge-pump) whose rectifier elements are FETs having internal diodes formed by a p-n junction between source/drain and the surrounding region; switching means tie those internal diodes to the source when the FET is conducting and to the drain when blocked, so the internal diodes stay blocked. The reference expressly notes the "back-gate bias voltage remains zero" and discusses the parasitic bipolar transistor whose collector, base and emitter are the substrate, the well, and the drain, respectively. It teaches NMOS in a P-well for high negative outputs and PMOS for positive outputs, with a multi-phase clock generator applying mutually phase-shifted clocks to successive booster capacitances, phased so the parasitic bipolar does not conduct.
• § 102 assessment: Structurally this is the most triple-well-like cited reference (substrate/well/drain bipolar stack; FETs with p-n junctions to the well; back-gate bias management; multi-phase clocking). It is, however, the inverse design philosophy: Philips deliberately blocks the internal well-to-drain diode, whereas the '557 patent exploits it as an "extra diode."
  Claim(s) potentially implicated: claim 1 (well + FET-with-p-n-junction structure; multi-phase clocked charge pump); potentially claims 5–6 / 9–10 on multi-phase clocking and capacitive coupling. Because it lacks the recitation of source/drain in the first well with first well, second well and source at common potential, I would expect § 103, not § 102, to carry this reference. It is arguably the strongest § 103 combination partner with US 5,502,629.

(vi) EP 0 678 970 A2 — Nippon Steel Corp.

• Full citation: European Patent Application EP 0 678 970 A2, "Semiconductor booster circuit," priority Apr. 20, 1994, published Oct. 25, 1995. (Listed in Google Patents "Similar Documents" as related to US 6,603,346, "Semiconductor booster circuit having cascaded MOS transistors," and to US 5,982,224, "Low-power charge pump circuit having reduced body effect.")
• Disclosure: A semiconductor booster circuit with cascaded MOS charge-transfer transistors/capacitors.
• § 102 assessment: Verified only at the level of title/field. I could not retrieve the passages needed to test it against claim 1's well-and-common-potential limitations, so I will not assert an anticipation mapping. On the available record it is background art on the booster/charge-pump environment of claim 1.

3. Consolidated § 102 mapping (with confidence levels)

Bottom line on anticipation. None of the cited references, on the record I could verify, anticipates claims 1, 11 or 13 outright. The reason is consistent: each reference disclosed at most one of the two pillars of the '557 claims — an isolated well (Tsukikawa), a common-potential body/source bias (Ito), or a well/drain p-n junction in a clocked multiplier (Philips) — but not the combination in which the pumping transistor's own source and drain sit in the first well, with the first well, second well and source all at a common potential (claims 1, 11, 13). That combination is what the examiner credited over this art. The references remain meaningful § 103 material and, because the patent expired Oct. 10, 2016 and its IPR (IPR2014-01117, Spansion) terminated by settlement, they have only historical/defensive significance now.

4. Methodological limitations (stated explicitly)

• I could not directly query USPTO PatentCenter/PAIR or the PTAB docket; the authoritative bibliographic data above is taken from the printed patent front page (PTAB Exhibit 1001) and Google Patents, which disagree by one reference (US 5,612,921).
• I did not retrieve the full text of EP 0 678 970 A2 or US 5,612,921; my disclosure descriptions for those two are unverified and I have not asserted an anticipation mapping for them.
• The instructions say to search the USPTO database for 6100557 specifically; I did so by literal number and returned only matches to that number, discarding US 7,777,557 and the Brazilian design DI 6100557-6 as unrelated.
• "Potentially anticipates under 35 U.S.C. § 102" is used here in the technical sense of disclosing every limitation of a claim; my assessments are preliminary and would require full-text verification of each reference (claims and specification) before being relied upon.

I'll ground this §103 analysis in the actual cited references. Let me pull details on each of the five front-page citations, since I need their disclosures — not just their titles — to build (or reject) combinations.

Excellent — the Mitsubishi reference (US 5,394,365) appears to disclose an isolated well of one conductivity type surrounded by an opposite-type layer, which is directly on point. Let me pull the full text of that reference and the other four.

Both Mitsubishi's US 5,394,365 and Fujitsu's US 5,502,629 look unusually close to the claimed structure. Let me retrieve the remaining references (Sony, Philips, Nippon Steel) and more of the Mitsubishi disclosure.

Obviousness Analysis — US 6,100,557 ("Triple Well Charge Pump") under pre‑AIA 35 U.S.C. § 103(a)

Scope note: the "'557" below is literally the patent under analysis, US 6,100,557 A / US6100557A (Appl. No. 08/849,561; PCT/US96/16317). I have kept every identifier exactly as it appears on the patent page. My previous section listed only the titles of the five front‑page citations; I have now retrieved substantive disclosure for four of the five, and that changes the picture materially — the earlier framing ("prior art = five unexamined titles") understated how close two of these references are. That is flagged explicitly in §7.

1. Legal framework and critical date

POSITA definition I am applying: a person with a B.S. in electrical engineering or applied physics and 3–5 years designing CMOS integrated circuits, including on‑chip charge pumps and high‑voltage generation for non‑volatile memory — familiar with Dickson/Schenkel pump topologies, the MOS body‑effect/threshold equation, and the parasitic‑bipolar/latch‑up constraints of isolated wells. This is the level assumed by the '557 specification itself, which states that associated circuits such as precharge and voltage regulation "are well known by persons of ordinary skill in the art."

Status of the five front‑page citations as § 103 art

Two of the five (§ 102(a)/(e) art) are usable in a § 103 combination notwithstanding that they issued inside the one‑year grace period; the pre‑AIA § 103(c) common‑ownership carve‑out does not apply (Fujitsu and Sony are not commonly owned with Macronix). All five were cited on the face of the '557 and therefore are presumed considered by the examiner.

2. What the reference disclosures actually contain (verified)

2.1 US 5,502,629 — Ito et al. (Fujitsu) — the most dangerous reference

This is a charge‑pump‑type DC‑DC converter that produces a negative output (converter 1, −V_CC) or a positive output (converter 60, 2V_CC) by switching capacitors C1/C2 with MOS transistors M1–M4 driven by a toggle flip‑flop in response to a clock CLK. Its FIG. 5 sectional view is, element for element, the well stack claimed:

"An N‑type separation layer 5 is formed in a P‑type semiconductor layer 4. A P‑type well (i.e., body or back gate) 6 is formed in the separation layer 5. A drain region 7 and a source region 8 are formed in the well 6… The substrate 4 is grounded. A voltage higher than or equal to the ground potential is applied to the separation layer 5 by means of a power source 9. Thus, a reverse bias condition is established between the substrate 4 and the separation layer 5 and between the well 6 and the separation layer 5."
(http://www.everypatent.com/comp/pat5502629.html; https://patents.google.com/patent/US5502629)

And, critically, Ito expressly ties the body well to the source terminal — the exact "common potential" coupling of claim 1 — and states the reason in the same terms as the '557:

"The source of the transistor M5 and the drain of the transistor M7 are connected to the back gate (i.e., well 6) of the transistor M3. The transistor M5 connects the back gate of the transistor M3 to the ground GND while the transistor M3 is turned on. As a result, no voltage difference exists between the source and back gate of the transistor M3, so that the resistance of the transistor M3 when turned on is reduced."

Ito's stated object is "suppressing the operation of a parasitic bipolar transistor inherently formed in MOS transistor circuitry used for DC‑DC power converters," and its background notes the low‑supply‑voltage trend in portable devices. That is the same problem statement the '557 uses (higher pump current and faster charge‑up at low V_DD).

2.2 US 5,394,365 — Tsukikawa (Mitsubishi)

A charge pump "for producing a negative substrate bias voltage, or a positive boosted voltage in a MOS (insulated gate type) semiconductor memory device." Its FIG. 1 pump's NMOS bulks are deliberately tied to the output node "in order to reliably reverse‑biasing PN junction between the bulk and the source/drain region," and the specification expressly describes the well/drain junction going forward biased and turning the diode on during pumping. Most importantly, Tsukikawa's claims 18–20 recite:

"…wherein said junction diode is formed in a well region of the first conductivity type surrounded by a semiconductor layer of a second conductivity type and separated from any other region forming an element."
"…wherein said well region provides an anode region of the junction diode."
(https://www.freepatentsonline.com/[5394365](/patent/5394365).html)

A further embodiment puts "P channel MOS transistors 20 and 21 … in an N type well 43 surrounded by a P type well 44" (https://patents.searchlight.law/doc/US5394365) — i.e., the complementary form of the same isolated‑well arrangement.

2.3 EP 0319063 A2/B1 — Philips

A multi‑stage voltage multiplier (rectifier elements D1…Dn, booster capacitances, a cascade producing a negative output V_EE) whose rectifier elements are field‑effect transistors and whose well ("region") is actively connected to the source or drain of the transistor:

"…internal diodes, formed in the field effect transistor by a p‑n junction between a source and a drain … and the region on the other side, [are connected] to either the source in the conductive state or to the drain in the blocked state … When the region is connected to the source of the field effect transistor in the conductive state of the latter, the back‑gate bias voltage remains zero."
(https://patents.google.com/patent/EP0319063B1/en)

EP 0319063 also discloses the cross‑coupled well‑biasing pair ("a source of the second and the third field effect transistor being connected to a source and a drain, respectively, of the first field effect transistor, a control electrode of the second and the third field effect transistor being coupled to the drain and the source, respectively, of the first field effect transistor"), a multi‑phase clock generator, and states "Such a construction comprising NMOS transistors in a P‑well is suitable for generating high negative voltages."

2.4 US 5,489,870 — Sony (Arakawa) — partially verified

The only substantive text I could retrieve shows a well‑isolated structure in a grounded substrate: "an n‑well 132 … is formed on the surface of the semiconductor substrate 131 constituted by a grounded single crystal silicon substrate, and the n.sup.+ diffusion layer 134 is [formed in] the n‑well 132" (https://uspto.report/patent/grant/[5489870](/patent/5489870)). Its EP equivalent is EP 0616329 A2 (Sony, priority 1993‑03‑18), cited side‑by‑side with the others in the FR 2759507 citation list (https://patents.google.com/patent/FR2759507A1) — which also confirms the German equivalent of Tsukikawa is DE 4312239 A1. I could not obtain the full disclosure; treat Arakawa as cumulative.

2.5 EP 0678970 A2 — Nippon Steel — not verified

Title "Semiconductor booster circuit." I could not retrieve its disclosure. Its title and 1995 publication date make it a plausible cumulative reference for well‑based booster stages, but I will not assume what it teaches. Verify before relying on it.

3. Ground I (primary) — Ito '629 in view of Tsukikawa '365: claims 1–10 and 12

3.1 Element‑by‑element mapping to claim 1

Ito alone discloses elements 1–5 essentially verbatim; the only element warranting a secondary reference or a design‑choice finding is the express three‑way common‑potential coupling (P well + N separation layer + source region). That is supplied by Tsukikawa (well and bulk tied to the pumped node so the well/drain junction operates as a conducting diode) and by EP 0319063 (region tied to source; "back‑gate bias voltage remains zero"). And it is independently obvious: leaving the deep N well below the P well's potential forward‑biases the P‑well/N‑well junction — the standard latch‑up/parasitic‑bipolar precaution that Ito and EP 0319063 both discuss at length. A POSITA has a ready reason to tie the isolating well to the highest local positive node (which is exactly what the '557 specification says one may do: "the second well can be set to the highest positive potential of the charge pump").

3.2 Motivation to combine (KSR rationales)

1. Same field, same problem, same solution space. Both references are on‑chip charge pumps for low‑voltage MOS memory/portable devices; the '557's own background frames the problem as needing a pump that "generat[es] more current and at a faster rate."
2. Known technique applied to a known structure with predictable result (KSR rationales (A)/(C)). Tying body‑to‑source to suppress body effect and lower V_T is textbook MOS design; Ito applies it to the very transistor type claimed and states the on‑resistance benefit. Tsukikawa applies the isolated‑well‑as‑diode concept to the very circuit type claimed.
3. Simple substitution of one known element for another (KSR rationale (B)). Substituting an isolated‑P‑well‑in‑deep‑N‑well pumping NMOS (Ito) for a conventional NMOS in a standard pump does not change the pump's principle of operation.
4. Reasonable expectation of success. Body‑effect suppression → lower V_T → faster turn‑on → higher forward conduction current is the familiar V_T = V_T0 + γ(√(2Φ_F + V_BS) − √(2Φ_F)) relation the '557 itself recites; both references predict it before the '557 did.
5. Design incentive/obvious design choice (rationale (D)) for the specific "common potential" tie and for sharing/isolating wells per stage.

3.3 Dependent claims 2–10, 12

• Claims 2–4 (V_DD ≈ 5 V to 1.5 V; 3 V; 2 V): Ito's entire premise is declining supply voltages in portable devices. Selecting a 2 V or 3 V supply is a result‑effective variable chosen by routine optimization. The '557 demonstrates no criticality — its Tables 2–5 show a continuous monotonic trend, not a threshold.
• Claims 5–6 (clock > 10 MHz; ≈ 22 MHz): pump output current scales with f·C; frequency is an ordinary design choice. EP 0319063 expressly discloses a multi‑phase clock generator (a ring oscillator of inverters). No unexpected result is established (see §6).
• Claims 7–8 (positive or negative last‑stage output): met squarely. Ito produces both (converter 1 → −V_CC; converter 60 → 2V_CC); Tsukikawa produces negative substrate bias or a positive boosted voltage.
• Claims 9–10 (means for coupling clock signals; a MOS transistor): EP 0319063's "booster capacitances" driven by a multi‑phase clock; Ito's capacitors C1/C2; Tsukikawa's capacitor 3. Using a MOS transistor as the coupling capacitor is a routine implementation choice well supported by the art and admitted in the '557 specification (transistors 112–119 "function as capacitors").
• Claim 12 (first and second wells coupled together with the sources): a one‑step design choice from Ito's body‑to‑source tie, and expressly taught for the region/well by EP 0319063.

Conclusion Ground I: claims 1–10 and 12 are, in my assessment, likely unpatentable over Ito in view of Tsukikawa (or Ito in view of EP 0319063). Claim 1 is also arguably anticipated by Ito alone if Ito's source 9 is read as holding separation layer 5 at the same ground potential as well 6 and the source of M3.

4. Ground II (alternative primary) — Tsukikawa '365 in view of Ito '629: claim 1

Treat Tsukikawa as the primary reference for the architectural element (isolated well of the first conductivity type surrounded by a layer of the second conductivity type, the well forming the anode of a junction diode with the drain region, and the bulk tied to the pumped node so the diode conducts) and Ito as the secondary reference for (i) the triple‑well pumping transistor whose source and drain are N‑type in a P well inside an N layer, and (ii) the express motivation to tie the body well to the source. Motivation is the same as Ground I: both references recognize that the well/source/drain junction in an isolated‑well pump transistor can be exploited and that body bias must be controlled; combining them yields only the predictable aggregate. This is a straightforward "known technique to improve a similar device in the same way" rationale (KSR (C)).

5. Ground III — EP 0319063 in view of Ito '629, and Ground IV — claims 11 and 13

5.1 Ground III (claim 1; claims 9–10 strengthened)

EP 0319063 supplies the multi‑stage cascade, the multi‑phase clock, the booster capacitances, and a well ("region") that is deliberately coupled to the transistor's source/drain for back‑gate control; Ito supplies the triple‑well pumping transistor and the body‑to‑source on‑resistance rationale. Its own text states the well/region construction "comprising NMOS transistors in a P‑well is suitable for generating high negative voltages" — squarely claim 8's negative‑output embodiment.

5.2 Ground IV — claims 11 and 13 (the cross‑coupled stage)

Claims 11 and 13 add the stage topology: a first transistor and a second transistor with the second's gate coupled to the first's drain, sources coupled together, and the second's drain coupled to the first's gate, both source/drain regions in the first well, with the sources coupled to that well.

The topology itself is admitted prior art on the face of the '557: the specification states "The way voltage is being pumped up is similar to a conventional charge pump," and the patent is classified by the USPTO/EPO in H02M 3/073 — "Charge pumps of the Schenkel‑type", the class for the cross‑coupled (Schenkel) latch pump. The examiner also cited art (Tsukikawa FIG. 1; EP 0319063's cross‑coupled well‑biasing pair with "a control electrode of the second and the third field effect transistor being coupled to the drain and the source, respectively, of the first field effect transistor") showing cross‑coupled two/three‑transistor cells in charge pumps.

Accordingly, the only inventive contribution of claims 11/13 over the admitted conventional stage is the well architecture — which is the same element already rendered obvious by Grounds I–III. Claims 11 and 13 are obvious, with the strongest rationale being (i) "known charge‑pump stage topology" + "the well structure of Grounds I–III" (KSR (A)), and (ii) for claim 13's per‑stage wells, routine layout design, reinforced by the '557's own admission that the triple‑well structure "can be used in practically all charge pump circuits." Note also that the '557 itself (FIG. 4) shares one well pair across two transistors, so claim 13's requirement that each stage have its own first/second wells is a matter of duplication, not invention.

6. Rebuttals, teaching‑away, and secondary considerations (where the case is genuinely contestable)

I do not think this is a one‑sided case. Three real counter‑arguments exist:

1. Teaching away / discouragement (strongest defense). The '557's asserted benefit is that the P‑well/N+ drain junction conducts forward as an "extra diode." Both EP 0319063 and Ito teach the opposite: EP 0319063 keeps the "internal diodes … blocked" and, when the transistor is off, disconnects the region from the source/drain so "the parasitic bipolar transistor whose collector, base and emitter are formed by the substrate, the well and the drain … will not become conductive"; Ito adds dedicated control transistors M5/M7 (and M14/M15, M17) precisely "to prevent a parasitic bipolar transistor, inherently formed in the selected MOS transistor, from turning on." A POSITA reading these references would be affirmatively steered away from letting the well/drain junction carry pumping current, because in a deep‑N‑well/p‑substrate process that injects majority carriers into the substrate and invites latch‑up.
   Rebuttal to the rebuttal: claim 1 does not require the diode to conduct — it requires only the well/source/second‑well common‑potential coupling. EP 0319063 does connect the region to the source ("the back‑gate bias voltage remains zero") in the conductive state, which is the claimed coupling. So the teaching‑away argument defeats the motivation, not the disclosure — a genuine § 103 fight, and one that may be why the examiner allowed the case.

2. Every reference was before the examiner. All five citations appear on the face of the '557 and the claims issued. That is evidence — not conclusive — that the specific combination was not considered obvious by the examiner. Because the file wrapper reasons for allowance are not in my retrieved record, I cannot say what the examiner relied on.

3. Secondary considerations. The specification offers its own results data (Tables 2–5: e.g., >2× output current for the inventive pump at 22 MHz vs. 7.3 MHz; better performance at V_DD = 2 V than 3 V; "can operate effectively down to 1.5 volt"). If corroborated by test data, that is a nexus argument for non‑obviousness. But there is no evidence of commercial success, licensing, or industry praise in the record before me, and — as flagged in my prior section — Tables 2 and 3 appear internally inconsistent in the OCR'd text (e.g., a "0.9" in Table 3 where Table 2 shows "0.1"), so the numbers should be verified against the printed patent before being relied on as objective evidence.

Contradiction worth flagging against the earlier section: the '557 specification asserts that prior‑art regulator NMOS charge pumps suffer "more than 10 volts of substrate bias." That premise is in tension with the disclosure of its own examiner‑cited references, which already manage body/well potential in charge pumps (Ito's body‑to‑source tie; EP 0319063's zero back‑gate bias in the conductive state). If the asserted problem was already solved in the art, the non‑obviousness story weakens and the motivation‑to‑combine story strengthens. I flag this rather than resolve it, because I have not read the '557's file history.

7. Bottom line and confidence

Confidence: moderate‑to‑high on the structural mapping for US 5,502,629 and US 5,394,365 (I retrieved the operative text and quotes above). Low on US 5,489,870 and unknown on EP 0678970 — I could not retrieve their disclosures, so I have deliberately not assigned them any load‑bearing role; if either discloses an isolated‑well pump transistor tied to its source, the case becomes correspondingly stronger, and this should be verified.

I could not determine (and therefore do not assert): the grounds actually raised in IPR2014‑01117 (petitioner Spansion, terminated by settlement per the legal‑events entry dated 2014‑09‑02), or the examiner's reasons for allowance. A settled IPR yields no institution decision or merits ruling, so it is neutral on validity — but it also means no estoppel attaches to any ground that was or was not raised.

Practical caveat: the '557 expired Oct. 10, 2016 (anticipated expiration), so it cannot presently be asserted. This § 103 analysis therefore matters only for its use as citable prior art against later claims and for any collateral validity question — not for a live infringement defense.

Sources: https://patents.google.com/patent/US6100557A/en (patent text, claims, citation list); https://www.freepatentsonline.com/5394365.html and https://patents.searchlight.law/doc/US5394365 (US 5,394,365 claims 18–20, bulk/diode operation); http://www.everypatent.com/comp/pat5502629.html and https://patents.google.com/patent/US5502629 (US 5,502,629 FIG. 5 well stack; back‑gate/source connection); https://patents.google.com/patent/EP0319063B1/en and https://patentimages.storage.googleapis.com/03/2b/aa/aa7de1db21fe5b/EP0319063B1.pdf (EP 0319063 region/back‑gate and cross‑coupled switching means); https://uspto.report/patent/grant/5489870 (US 5,489,870 well/substrate snippet); https://patents.google.com/patent/FR2759507A1 (corroborating the same five‑reference citation set and the DE 4312239 A1 / EP 0616329 A2 equivalents).