US 7777557

Here's a concise summary of US Patent 7777557:

US Patent 7777557

• Title: Booster circuit
• Current Assignee: Advanced Memory Technologies LLC (originally Panasonic Corp)
• Inventor: Seiji Yamahira
• Filing Date: January 17, 2008
• Issue Date: August 17, 2010
• Abstract: A boosting circuit includes a first boosting cell row and a second boosting cell row. It also features an analog comparison circuit that compares the potential of boosting cells on the same stage and outputs either the lower or higher of these potentials. This output potential from the analog comparison circuit is then used to control the potential of an N well, which helps suppress the amplitude of the N well potential and allows a single N well region to be shared.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a booster circuit composed of multiple "boosting cells." Each boosting cell has a triple-well structure (a first-conductivity type first well region on a substrate, and a second-conductivity type second well region within the first well region) and at least one switching element to transfer electrical charges. The circuit includes a first row (N stages) and a second row (M stages) of these boosting cells. Crucially, it features at least one "analog comparison circuit" that compares the output potential of boosting cells on the same stage in both rows. This comparison circuit then generates a "well bias potential," which is applied to the first well region of the switching elements within the boosting cells of the first and second rows.
• Claim 13: This claim builds upon the core concept by including "backflow preventing circuits" in addition to the boosting cells in both the first and second boosting cell rows. The analog comparison circuit, in this case, compares the "intermediate potential" of the backflow preventing circuits from both rows and outputs a well bias potential. This potential is then applied to the first well region of the switching elements within the backflow preventing circuit itself, or to boosting cells at the (i+1)-th, i-th, or stages anterior to the i-th stage in either row.
• Claim 14: This claim outlines a booster circuit with boosting cells, each having the aforementioned triple-well structure and at least one switching element for charge transfer. It includes first and second boosting cell rows. The key feature is that the potential of the first well region of the switching elements in the boosting cells of both rows is controlled based on the output potentials of the boosting cells in the first boosting cell row and the output potentials of the boosting cells in the second boosting cell row.

CAFC 2026 Dockets:

A review of the CAFC 2026 dockets (specifically May 2026) did not show any scheduled cases for US patent 7777557. However, the Google Patents page for US7777557B2 indicates that the patent family has litigation, including a PTAB case (IPR2025-01452) filed in 2025 (though "Not Instituted - Procedural") and a US case filed in the Texas Eastern District Court (2:24-cv-01078) in 2024. There is no authoritative information to confirm active CAFC litigation for this specific patent in 2026.