US 7102422

I'll search for this specific patent number across multiple sources.

Let me retrieve the complete claim set and check for any litigation activity.

Let me do a final check for litigation and the remaining independent claims.

US Patent 7,102,422 B1 — Analyst Summary

Source basis: Google Patents (patents.google.com/patent/US7102422B1/en), Justia Patents (patents.justia.com/patent/7102422), and the pre-grant publication US 2002/0125935 A1. No CAFC 2026 docket activity was found for this number (see caveat at end).

Bibliographic Data

Note on inventor name: Google Patents and Justia list the inventor as "Kikuzo Sawada," while the related pre-grant publication US 2002/0125935 A1 lists "Kikuza Sawada." I am reporting both spellings as they appear rather than silently correcting one.

Related family: The application 08/423,089 also generated divisional application 10/060,346 (filed Feb. 1, 2002), which issued as US 6,603,346 B2 (pre-grant pub. US 2002/0125935 A1). European family members include EP 0678970 B1 / EP 1134879 B1 / EP 1237266 B1 and DE 69529013 T2.

Abstract (as issued)

A semiconductor booster circuit includes a plurality of stages, each of which has a MOS transistor and two capacitors. The MOS transistor, having a drain, a source and a gate, is formed in a well of a substrate portion. One capacitor has a terminal connected to the drain of the MOS transistor, while the other capacitor has a terminal connected to the gate of the MOS transistor. A first clock signal generating means generates a first clock signal via another terminal of one capacitor. A second clock signal generating means generates a second clock signal, with a larger amplitude than a power supply voltage, via another terminal of another capacitor. The plurality of stages are cascaded together, and in each of the stages the source of the MOS transistor is electrically connected to the well in which the transistor is formed, while the wells are electrically insulated from each other.

Plain-Language Overview of the Independent Claims

The confirmed independent claims retrieved are claims 1, 2, and 7. (I could not retrieve the full claim set beyond claim 7; see "Uncertainty" below.)

Claim 1 — "Both fixes combined"
A charge-pump/booster circuit made of multiple cascaded stages. Each stage has (a) a MOS transistor formed in its own well, (b) a first capacitor tied to the transistor's drain, and (c) a second capacitor tied to the transistor's gate. A power supply voltage is fed to the drain of the first stage and is boosted stage-by-stage so the output source node is higher than the supply. Two clock generators are required: one drives the first capacitors with a first clock; the other drives the second capacitors with a second clock having larger amplitude than the power supply voltage. The two key structural limitations: within each stage the transistor's source is tied to its own well, and the wells of the different stages are electrically insulated from each other. (This is the two-technique combination: well-per-stage body biasing plus boosted gate drive.)

Claim 2 — "Well isolation / body-tied source"
An independent claim covering the first technique largely by itself. Same cascaded multi-stage booster with one capacitor per transistor drain, supply fed to the first stage, output higher than supply. The distinguishing feature is the structural body-bias arrangement: the transistor is formed in a well, and (per the claim's structure) the wells of the stages are electrically insulated from one another with the source tied to its well. This is the claim that captures suppression of the "substrate effect" (threshold-voltage rise as the pumped output climbs).

Claim 7 — "Boosted-amplitude gate clock / dual-capacitor topology"
An independent claim ("A semiconductor booster circuit having MOS transistors connected in cascade…") covering the second technique. Each stage has a transistor, a first capacitor on the drain, and a second capacitor on the gate. Supply is applied to the first-stage drain and boosted to a higher output at the last stage's source. A first clock generator drives the first capacitor; a second clock generator drives the second capacitor with a clock amplitude larger than the power supply voltage. By driving the gate with an over-supply clock signal, the transistor is fully turned on even at low supply voltages, which removes the threshold-voltage drop that limits conventional pumps.

Dependent claims (for context): Claims 3–6 depend from claim 2 — claim 3 specifies N-type wells holding P-channel MOS transistors; claim 4 adds the second capacitor plus a pass/transfer MOS transistor between gate and source gated by the first capacitor; claim 5 specifies two anti-phase first clocks and two differently-timed second clocks on adjacent stages; claim 6 ties one stage's gate to the next stage's capacitor.

Technical Takeaway

The patent addresses the classic limitation of integrated charge pumps: as pumped output rises, the source-to-body bias (substrate/body effect) raises each transistor's threshold voltage Vt, saturating the achievable output — so increasing the number of stages stops helping. The specification notes conventional designs are limited to e.g. ~12 V at Vdd = 2.0 V even with 100 stages. The invention attacks this two ways: (1) giving each transistor an isolated well tied to its own source (eliminating body effect, using the well/substrate PN junction's forward-bias voltage V_F ≈ 0.7 V instead of Vt), and (2) driving the transfer gates with a clock whose amplitude exceeds the supply. The specification reports ~47 V at 20 stages versus ~20 V for the prior art under comparable parameters.

Uncertainty / Due-Diligence Notes

1. Complete claim set not fully retrieved. Justia's listing and the search excerpts confirmed independent claims 1, 2, and 7, but I was not able to retrieve the full text of claims beyond claim 7. The specification's SUMMARY describes four aspects (first through fourth), the fourth aspect being grouping of substrate portions whose potentials are controlled independently per group (positive- and negative-high-voltage variants). This strongly suggests at least one additional independent claim (likely directed to the grouped/independently-controlled substrate portions) that I could not verify verbatim. Treat the claim list above as covering claims 1, 2, and 7 with confidence, and possibly incomplete.

2. No CAFC 2026 docket entry found for US 7,102,422. A targeted search for litigations/dockets matching this number returned no Federal Circuit 2026 activity. One search result discussed a "'422 Patent" in Cox (MoCA-related, C.D. Cal., case 2:23-cv-010437), but that patent issued October 1, 2019, from a 2017 application, with 20 claims — which contradicts US 7,102,422's Sept. 5, 2006 issue date. Per the instruction to interpret numbers literally and not auto-correct, these are different patents sharing a "422" suffix; that litigation is not about US 7,102,422.

3. Legal status ("Expired – Lifetime," anticipated expiration September 5, 2023) is as reported on Google Patents and is an assumption, not a legal conclusion, per that source's own disclaimer.

4. I did not independently verify the USPTO PatentCenter/Assignment records directly; the assignment data above is from Google Patents' reassignment listing (Nippon Steel Corporation, 1995).

Grounding URLs:

• https://patents.google.com/patent/US7102422B1/en
• https://patents.justia.com/patent/7102422
• https://patentimages.storage.googleapis.com/2d/74/54/cd51767d3c3c0b/US20020125935A1.pdf

I'll search for litigation involving US patent 7102422 across patent litigation databases.

Let me search more specifically across patent litigation databases.

Summary of Findings

I could not identify any litigation involving U.S. Patent No. 7,102,422.

I searched general patent-litigation and PTAB-oriented sources (Unified Patents portal references, Docket Alarm / CourtListener materials, Justia, Google Patents, and general web queries keyed to the exact number and to the patent's title and assignee). None of those returned a docket, complaint, or PTAB proceeding naming US 7,102,422 as an asserted or challenged patent.

Important caveat about a false positive

One result that surfaced was a Louisiana district court opinion discussing a "'242 Patent" concerning movable key pieces on a game board and prior art like the "Swift reference." That is a different patent — it has nothing to do with US 7,102,422 (Nippon Steel's "Semiconductor booster circuit having cascaded MOS transistors"). Do not attribute that case to US 7,102,422. This is exactly the kind of similar-number confusion to avoid.

Per-requested table

Why no litigation is plausible / likely

Based on the patent bibliographic data I retrieved:

• Assignee: Nippon Steel Corporation (original and current assignee listed).
• Priority date: 1994-04-20 (JP 10467394, JP 10467294); filing date 1995-04-18.
• Grant/publication date: 2006-09-05.
• Legal status: Expired – Lifetime, with anticipated expiration 2023-09-05.

Because the patent expired in September 2023, it is no longer enforceable, which substantially reduces (though does not retroactively erase) the possibility of infringement suits. Even so, my searches surfaced no historical district court or Federal Circuit litigation, and no PTAB (IPR/PGR/CBM) challenge involving this number.

Limits on this answer

• I did not obtain a direct hit from the Unified Patents litigation caselist, PACER, or a Docket Navigator/lexmachina record for this exact patent. The tools available to me returned search-engine snippets rather than a definitive "no results" query against those databases.
• Therefore, my conclusion is a negative finding based on the sources searched, not proof of absence. If you need a litigation-grade negative, I recommend running the exact number on Docket Navigator, Lex Machina, Unified Patents Portal (https://portal.unifiedpatents.com/patents), and PACER (party-name search on "Nippon Steel" as well), since those databases index quiet or short-lived suits that may not surface in general web search.

Bottom line: No known litigation involving US 7,102,422 was found; the patent is expired (anticipated expiration 2023-09-05), and the one "'242 Patent" result located concerns an unrelated game-board patent and must not be confused with this number.

I'll verify the structured data against live sources before reporting.

Proceedings overview

Total AIA trial proceedings on file for US 7,102,422: ZERO. The structured "PTAB proceedings on file" block — sourced from the USPTO Open Data Portal API — returns no IPR, PGR, or CBM proceedings as of the most recent ingest, and my independent web searches (Google Patents, Justia, PTAB-related materials, news/litigation roundups) surfaced no IPR/PGR/CBM petition, no PTAB Final Written Decision, no CAFC appeal, and no settlement/termination involving this patent. Breakdown by status is therefore: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

Bottom line for a defendant: there is no PTAB record to mine, and there never will be a useful one going forward — the patent expired on 2023-09-05 (per the ODP legal-status entry "Expired – Lifetime"; anticipated expiration 2023-09-05). That makes the defensible posture here not "this patent is hardened by surviving IPRs" but rather "this patent is off the board." The absence of PTAB activity is not a signal of strength; for a 1995-filing/2006-granting charge-pump patent that expired in 2023, there was little economic reason for anyone to spend IPR fees on it. Any assertion you receive today can only be directed at pre-2023-09-05 past conduct.

No proceeding subsections

Because the canonical structured list is empty and no proceeding number could be verified in public sources, I am not creating any ### {PROCEEDING_NUMBER} entries — inventing one would be fabrication. If a recently-filed petition exists that the ODP hasn't indexed (possible only for recent filings; extremely unlikely given the 2023 expiration), it would appear in PTAB E2E at https://ptacts.uspto.gov/ptabweb/ and could be surfaced by a party-name search on the patent owner (Nippon Steel Corp. / Nippon Steel & Sumitomo Metal / Nippon Steel Corp. as current assignee per ODP).

Strategic summary

Claim status: UNTESTED, not CANCELED and not SUSTAINED. No claim of US 7,102,422 has ever been adjudicated by the PTAB. There is no IPR estoppel to leverage and no canceled claim to point to. What I can verify from the patent text itself (authoritative, fetched 2026-09-24 from https://patents.google.com/patent/US7102422/en) is the claim set as issued: independent claims 1 and 2, with dependents 3, 4, and 5 at least (claim 4 adds the "another capacitor connected to the gate + another MOS transistor between gate and source" structure; claim 5 adds opposite-phase first clock signals to adjacent stages). The full claim set should be read directly from the patent, not from any secondary source. Every one of those claims is untested in any AIA forum.

The real defensive landscape is the calendar, not the PTAB. Key ODP-derived facts: application 08/423,089 filed 1995-04-18; earliest priority 1994-04-20 (JP 10467394A, JP 10467294A); granted 2006-09-05; expired 2023-09-05. That date is consistent with the pre-URAA term rule — because this application was filed before 1995-06-08, the term is the greater of 17 years from grant (2006-09-05 + 17 = 2023-09-05) or 20 years from filing (2015-04-18), so the 17-years-from-grant date controls. A defendant's first move on any demand letter citing this patent is the expiration date, not a prior-art search. Note also that an expired patent can still be the subject of an IPR in principle, but the practical utility is limited to wiping out past damages exposure, and the patent owner here never faced a petition.

Family-wide diligence is the gap I'd flag. The Google Patents record shows priority links to JP3354708B2, JP3354709B2, and JP3354713B2, and a US 6,603,346 B2 (application 10/060,346, filed 2002-02-01) in the same family — which, by the same term logic, would itself have expired around 2022-02-01 absent term adjustment. Sibling/continuation patents are where stale charge-pump portfolios often still have teeth, and I have not verified whether any of them have been asserted or challenged. That is the one place your diligence budget should go.

Pattern signals: none available. No repeat petitioner, no serial IPR filer, no Unified Patents or other defensive aggregator appears anywhere in the record for this patent, and the ODP "Current Assignee" field lists a single operating company (Nippon Steel Corp.) rather than a monetization vehicle — i.e., there is no evidence of an active assertion campaign. I could not confirm any district court litigation involving US 7,102,422 from the sources available; treat that as an unverified negative, not a confirmed one.

Recommended next steps

1. If you have a demand letter citing US 7,102,422: lead with expiration. The patent expired 2023-09-05 (ODP legal status: "Expired – Lifetime"). Confirm the expiration certificate / maintenance-fee history for the 12-year window via USPTO Patent Center (https://patentcenter.uspto.gov/) so the record is airtight, then quantify what pre-expiration conduct, if any, the accuser can actually reach.
2. Do not budget for an IPR defense. There is no PTAB proceeding to coordinate with, no § 315(e)(2) estoppel to invoke, and no FWD to cite. An IPR on an expired patent buys you very little.
3. Check the family before you relax. Pull the prosecution/continuity chain for application 08/423,089 and verify the status, expiration, and assertion history of US 6,603,346 B2 and the JP siblings (JP3354708B2, JP3354709B2, JP3354713B2). A live or recently-expired sibling is the realistic vehicle for any assertion against you.
4. If you nonetheless need to confirm the negative on the record: search PTAB E2E by patent number and by the patent owner's names (Nippon Steel Corp.; Nippon Steel & Sumitomo Metal Corp.), and check the Federal Circuit docket and CourtListener for any appeal captioned with Nippon Steel involving this patent. Report the results in writing — a documented "no proceedings" finding is itself useful if an accuser implies the patent has been validated.
5. Treat the empty PTAB record honestly in any opinion you draft: say "no PTAB proceedings on file as of the USPTO ODP ingest," not "the patent has survived IPR challenges." Those are different statements, and only the first is supported.

Sources consulted: USPTO Open Data Portal "PTAB proceedings on file" block (canonical, empty); https://patents.google.com/patent/US7102422/en (full text, claims, dates, assignee, legal status, priority links); https://patents.justia.com/patent/[7102422](/patent/7102422) (claims 1–5 text). PTAB E2E (https://ptacts.uspto.gov/) returned no matching proceedings for this patent number in the material retrieved. No PTAB FWD and no CAFC opinion for this patent was located to cite.

I'll research the assignment record for US 7102422 before drafting. Let me start with several searches.

Assignment & Ownership Analysis — US 7102422 B1

Patent: US 7,102,422 B1 — "Semiconductor booster circuit having cascaded MOS transistors"
App. No.: 08/423,089 · Filed: 1995‑04‑18 · Granted: 2006‑09‑05 · Anticipated expiration: 2023‑09‑05
Family: JP 10467294 / JP 10467394 (priority 1994‑04‑20), JP 14111394 (1994‑05‑31); siblings US 10/060,346 → US 6,603,346 B2, JP 3354708 B2, JP 3354709 B2, JP 3354713 B2, EP 1134879 B1, EP 0880783 B1.

Source-access caveat (read first). The USPTO Assignment Center (assignmentcenter.uspto.gov) and the legacy Assignment Search index were not reachable/returning record-level data for this patent in this session, and neither the reel/frame, the recorded correspondent, nor any post-issuance conveyance could be independently pulled. What follows is grounded on (a) the Google Patents full-text legal-events table for US7102422B1 (https://patents.google.com/patent/US7102422/en) and (b) corroborating searches. I have not fabricated any reel/frame, correspondent name, or assignee that I could not source. Where a data point is missing, it is marked not retrieved.

Inventors

Pattern notes:

• Both named inventors are listed as assignors directly to Nippon Steel Corporation in the 1995 record, consistent with standard employee-invention assignment practice at a large Japanese industrial firm. No inventor‑retention, no later inventor-side reassignment appears.
• I found no evidence of inventors departing the assignee within 12 months of filing (the classic portfolio-fire-sale precursor). To the contrary, the corporate-history record shows the business unit, not the inventors, was divested years later: Nippon Steel bought NMBS/Minebea's DRAM unit (1993), renamed it Nippon Steel Semiconductor, and in September 1998 agreed to sell its 56% stake and the Tateyama fab line to UMC, exiting chip manufacturing (reported sale price ≈¥5 billion / ~¥15.2 billion for the 56% stake in some accounts; the group booked ~¥120 billion special loss). That is a business-unit divestiture, and I found no indication this patent was conveyed with it.
• Inventor-employer reconstruction is inferential (from the assignment recordation), not from a contemporaneous employment document.

Original assignee

Nippon Steel Corporation (6‑1, Marunouchi 2‑chome, Chiyoda‑ku, Tokyo, Japan) — named as assignee on the issued patent and still shown as current assignee by Google Patents.

• Primary line of business: integrated steel production — one of the world's largest steelmakers. Its LSI/electronics division and subsidiary Nippon Steel Semiconductor pursued DRAM and related IC work (charge pumps for EEPROM/flash are squarely LSI-division technology), but this was a peripheral, ultimately abandoned line.
• Product embodying the claims: The subject matter (a cascaded-MOS charge pump / booster with isolated well substrates and boosted gate clocks) is a design-block technology for on-chip high-voltage generation in EEPROM/flash. I found no evidence Nippon Steel commercialized a discrete booster product embodying these claims; the relevant "product" context is its memory/LSI activity, which it exited.
• Current status of the original assignee: Operating. Nippon Steel has never been dissolved or bankrupt. Corporate name trail: Nippon Steel Corporation → Nippon Steel & Sumitomo Metal Corporation (merger, 2012‑10‑01) → renamed back to Nippon Steel Corporation (2019‑04‑01). Caveat: whether those name changes were ever recorded as Change-of-Name conveyances against this patent is not retrieved — Google Patents simply shows "Nippon Steel Corp," which is consistent with either an unrecorded name change or a post‑2019 name.

Assignment timeline

Chronological record of what is actually evidenced. Only one conveyance could be confirmed; no post-issuance assignment to any third party appears in the Google Patents legal-events table.

• 1995‑04‑18 (executed / same-day recorded per Google Patents legal events) — Reel NNNNNN/NNNN not retrieved

  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST)
  • Assignor: Kikuzo Sawada; Yoshikazu Sugawara (inventors)
  • Assignee: Nippon Steel Corporation
  • Correspondent: not retrieved — the Assignment Center record did not surface in this session; no correspondent name or firm can be stated without fabrication.
  • Context: Original inventor-to-employer assignment at filing — not a fire-sale, reorg, or securitization.

• 2002‑02‑01 — no assignment; this is a priority/continuation link to US application 10/060,346 (granted as US 6,603,346 B2), not a conveyance.

• 2006‑09‑05 — grant of the patent (no conveyance).

• 2023‑09‑05 — anticipated expiration; Expired – Lifetime (no lapse-for-fee event, no conveyance).

Post-issuance assignments to any NPE, aggregator, or successor: none found. Google Patents' "reassignment" entries contain only the 1995‑04‑18 Nippon Steel recordation; there is no Security Agreement, Merger, Change of Name, License, or Release recorded against this patent in the sources I could reach. If the Assignment Center holds additional records, they were not retrievable here and this finding is therefore bounded by that limitation — verify directly at https://assignmentcenter.uspto.gov/ by searching patent number 7102422.

Timeline diagram

timeline
    title Ownership of US 7102422
    1994 : Japanese priority filings
    1995 : US application filed
         : Inventors assign to Nippon Steel
    1998 : Nippon Steel exits chip making
    2002 : Continuation filed
    2006 : Patent granted
    2023 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No licensing-only LLC (no "IP / Patents / Holdings / Ventures" suffix, no registered-agent address, no Delaware/Texas single-purpose entity) appears anywhere in the reachable record. The chain begins and ends at the original operating company.

2. Known asserter in the chain — not present. Neither Nippon Steel Corporation nor any affiliate matches the checked lists (Acacia, Marathon, IV, IPNav, Wi‑LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg entities). No such entity is recorded against US7102422.

3. Repeat correspondent across the chain — unclear / not retrievable. With only a single confirmed link, there is no chain across which recurrence could be measured, and the correspondent on that single 1995 record could not be pulled. No correspondent name or firm will be asserted here.

4. Cascading transfers (chained LLCs < 24 months) — not present. No second transfer exists in the record at all, so there is no cascade.

5. Pre-litigation transfer — not present. I found no infringement litigation naming US7102422. The only third-party reference surfaced is a citation of US 7,102,422 B1 as prior art in an EPO search report (annex to EP 4,202,929), which is prosecution citation, not assertion. With no suit, there is no pre-suit assignment window to test.

6. Bankruptcy fire-sale — not present. Nippon Steel never filed bankruptcy. The 1998–99 event was a voluntary business-unit divestiture of Nippon Steel Semiconductor to UMC, not a Chapter 7/11 asset sale, and no patent conveyance is evidenced.

7. Privateering — not present (unclear, weakly). No transfer to an NPE is recorded, so there is no operating-company-to-troll arm's-length shift to evidence. The one adjacent, unrelated event is the 2011 Cree–Nippon Steel SiC cross-license (Cree received rights to Nippon Steel's SiC-related patents), which concerns silicon-carbide materials patents — not this charge-pump patent and not an NPE arrangement. I note it only to close the loop on "Nippon Steel patent licensing" searches; it does not touch US7102422.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN.

Verdict

Insufficient data — the record contains only the original assignment, which is the controlling fact.

The sole evidenced conveyance is the 1995‑04‑18 inventor→Nippon Steel Corporation assignment, and Google Patents shows Nippon Steel as the current assignee with no intervening Security Agreement, Merger, or transfer to any party through the 2023‑09‑05 expiration; no litigation naming the patent was found. Because the Assignment Center records could not be retrieved in this session, the reel/frame numbers and the correspondent of record remain unverified — this is a documentation gap, not evidence of an NPE chain, and I am deliberately not inferring "shell entity" from any naming pattern. Absent a transfer, the ordinary conclusion is that the patent simply expired in the hands of its original operating-company owner and was never asserted.

Verify: https://assignmentcenter.uspto.gov/ (search patent number 7102422) and cross-check https://patents.google.com/patent/US7102422/en (Legal Events / "Reassignment" entries).

I'll research the prior art citations for US 7,102,422. Let me search multiple sources.

Let me dig into the specific citations listed on the patent's face and the related family member.

I have a partial citation list. Let me get the complete "References Cited" list from the authoritative sources.

Preliminary notes and scope

Patent under analysis: US 7,102,422 B1 — "Semiconductor booster circuit having cascaded MOS transistors." Inventors Kikuzo Sawada and Yoshikazu Sugawara; assignee Nippon Steel Corporation. Application 08/423,089, filed 1995‑04‑18; earliest priority 1994‑04‑20 (JP 10467394 / JP 10467294), with further JP priorities 1994‑05‑31 (JP 14111394) and 1994‑08‑31 (JP 23035894); granted 2006‑09‑05; expired/anticipated expiration 2023‑09‑05.

Two scope caveats I must flag up front:

1. The claim text was not contained in the materials I was given (the supplied full text is truncated before the claims; it ends mid‑"FIG. 21" in the description). I therefore map citations to the claimed subject matter as reflected in the SUMMARY OF THE INVENTION (the four "aspects"), and I label each mapping as tentative. Anyone using this for an invalidity position must re‑run the analysis against the literal claim language from the granted patent.
2. Tool/step limits were reached before I could pull the complete IDS or the full text of every cited reference. The reference list below is the one published for US 7,102,422 (Justia "Referenced Cited," https://patents.justia.com/patent/[7102422](/patent/7102422)). I believe it is the operative examiner/IDS citation list for this number — the presence of the December‑1996 EP publication is consistent with a long‑pendency application filed in 1995 and granted in 2006 — but I could not exhaustively verify it, and I could not open each cited reference's full text. Descriptions marked [verify] are best‑effort and should be confirmed against USPTO full‑text before being relied on.

Do not confuse this with the unrelated "'242 Patent" noted in the earlier litigation summary (a game‑board case). Different patent; the number coincidence is a known false‑positive trap.

I also flag that this patent is one member of a family (US 6,603,346 B2; US 2002/0125935 A1; EP 0678970 / EP 1134879 / EP 1237266). Those are sibling/related disclosures, not prior art to US 7,102,422 (same priority), and must not be counted as § 102 art against it.

References cited on the face of US 7,102,422

A. U.S. patent documents

All six pre‑date the 1994‑04‑20 priority, so all are available as prior art (subject to the 1‑year grace/§ 102(b) rules of the pre‑AIA statute that governs this 1995 filing).

B. Foreign patent documents

C. Non‑patent literature

Bottom‑line § 102 assessment

1. No reference cited on the face of US 7,102,422 appears to be a § 102 anticipation of the independent claims. The claims (as reflected in the four SUMMARY "aspects") are built on a combination: (i) per‑stage source‑terminal‑to‑substrate connection, (ii) electrical insulation between the substrates/wells of different stages (or groups), and/or (iii) a second capacitor at each gate driven by a second clock of larger‑than‑supply amplitude. The cited art is either the conventional single‑capacitor cascaded pump (US 4,970,409; US 5,029,063; US 5,157,280; EP 0 319 063; EP 0 349 495; EP 0 485 016; JP 57‑110076), a per‑stage‑Vt‑variation scheme that the patent expressly distinguishes (JP‑A‑61‑254078), or a modeling paper (IEEE 1989). Every element of the independent claims is not disclosed in a single one of them.
2. The realistic invalidity theories are § 103, not § 102 — e.g., a conventional charge pump (e.g., US 5,029,063 / US 5,157,280 / US 4,970,409) in view of the IEEE 1989 paper's substrate‑effect teaching, optionally with JP‑A‑61‑254078 or a well‑isolation/deep‑well reference. That is the posture consistent with the patent having been granted over this list: the examiner allowed the claims, which means the art of record was not treated as anticipating.
3. EP 0 591 022 (Dec. 1996) cannot be prior art to claims entitled to the 1994‑04‑20 JP priority; treat it as a family/administrative citation, and verify its identity before any reliance.
4. The strongest single cited reference on the merits is JP‑A‑61‑254078, because the patent's own Background section names and rebuts it. Any invalidity showing should start there and supplement it with the source‑to‑substrate and well‑isolation teachings (for which the well‑isolation/deep‑N‑well prior art discussed in later charge‑pump IPRs — e.g., the multi‑well/body‑effect material in the PTAB papers surfaced in search — is more relevant than anything on the IDS list).

Verification gaps I could not close (be transparent)

• I did not obtain the complete IDS/file‑wrapper for 08/423,089; the list above is the published "Referenced Cited" for US 7,102,422 and may omit references cited only in the parent application or only in the Japanese priority applications.
• I could not open the full text of each cited reference to confirm inventor/title and precise disclosure; descriptions marked [verify] are provisional. Cited‑reference titles and subject matter should be confirmed on USPTO Patent Center / Google Patents before being quoted.
• I did not reach the granted claim set; the claim numbers I reference are the "aspect" groupings from the SUMMARY, not literal claim numbers. A § 102 mapping must be redone claim‑by‑claim once the claim text is in hand.
• The U.S. references commonly seen in charge‑pump search reports (e.g., US 5,014,779 (Meling); US 3,489,220 (Kinley); US 3,162,245 (Howard); US 3,203,483 (Vincent); US 5,224,560 (Fernandez); US 4,960,643 (Lemelson); GB 2,155,950) came up in other applications' international search reports, not on the US 7,102,422 citation list as retrieved — do not attribute them to this patent's IDS without verification.

Bottom line: The cited prior art for US 7,102,422 is a conventional charge‑pump/booster set plus one expressly‑distinguished Cockcroft booster (JP‑A‑61‑254078) and the IEEE 1989 modeling paper. None of them, singly, appears to anticipate the independent claims as summarized; they are best characterized as § 103 references, and the patent was granted over them.

I'll research the prior art references cited on this patent's page and related art before building the § 103 analysis.

Let me gather more prior-art references relevant to the well-isolation/body-bias and boosted-clock techniques.

Let me pin down the pre-1994 prior art on boosted clock amplitude and the US 4,016,476 reference details.

Obviousness Analysis — US 7,102,422 B1 (35 U.S.C. § 103)

Patent: US 7,102,422 B1, "Semiconductor booster circuit having cascaded MOS transistors"
Applicants/Inventors: Kikuzo Sawada, Yoshikazu Sugawara; assignee Nippon Steel Corp.
US filing: 1995-04-18 (Appl. 08/423,089) • Foreign priority: 1994-04-20 (JP 10467394, JP 10467294); also 1994-05-31 (JP 14111394)

1. Governing framework (read this before the analysis)

Two important consequences of the 1994 critical date — these cut against an obviousness case built on modern art:

1. The entire "triple-well charge pump" line of art post-dates this patent's priority and is not § 103 prior art. Specifically: WO 98/16010 (Macronix, filed 1996-10-10, pub. 1998-04-16 → US 6,100,557); US 6,285,240 B1 (filed PCT 1999-01-14); US 6,472,666 ("Bootstrapped charge pump," 2001); US 6,160,723 (2000). These are highly on-point for the technology generally, but any analysis that leans on them for US 7,102,422 is legally wrong. Flagged explicitly.
2. The strongest admissible art is (a) the patent's own admitted prior art and (b) the two references the specification itself cites. The solution therefore has to be built out of that foundation plus classic pre-1994 references.

2. The prior art of record

3. Claim scope and a threshold observation

From the file, the confirmed independent claims are 1, 2, and 7, with dependent claims 3–6 (per the prior summary; the full set past claim 7 was not retrievable — see § 7). Critically, the published claim wording (mirrored in the EP family member EP 1 237 266 A2) recites that the source is tied to its substrate "and when said plurality of stages are divided into at least two groups, the substrates … included in each group are electrically insulated from the substrates … included in another different group."

This is broader than "one well per stage." The claim is satisfied by any partitioning into ≥2 isolated substrate groups. That materially weakens the non-obviousness position on claim 2: the admitted FIG. 22 art already has the stages' substrates in one common group; moving to two groups is a facially minor, predictable variation. (This also aligns with the specification's "fourth aspect," where FIG. 13/14 show exactly two P-well groups.)

4. Claim-by-claim obviousness

Group A — Claim 2 (body-tied source + isolated substrate groups); Claims 3–6 dependents

Proposed combination: Witters (1989) / admitted FIG. 22 pump + US 4,016,476 + JP-A-61-254078.

• Witters / FIG. 22 supplies every structural element of claim 2 except the well-isolation/body-tie: plural cascaded MOS stages, one capacitor per drain, Vdd into the first stage, a pumped output at the last stage's source.
• JP-A-61-254078 supplies the motivation: it squarely identifies the substrate effect as the reason the output voltage fails to scale with stage count, and attempts a fix (grading Vt). A POSITA reading it is directed to "reduce the body effect in later stages."
• US 4,016,476 supplies the mechanism: connect the substrate directly to the source. The patent's own operation section describes precisely the consequence — the drain/body PN junction becomes parallel to the channel and its forward bias V_F (~0.7 V) substitutes for Vt in equations (1)/(2). That is the FIG. 6/10 device physics, and it is exactly what US 4,016,476's claim 1 describes ("source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction").
• The remaining piece — electrically insulated wells per group — is routine twin/triple-well CMOS layout, and the patent concedes it costs no extra masks ("the number of manufacturing processes is not increased at all"). Giving each source-tied body its own isolated well is the ordinary way to implement a per-stage body-tie on a common substrate; otherwise the tie short-circuits across stages.

KSR rationales: (i) Simple substitution of a known body-bias scheme (source-tied body) for the known grounded-body scheme, to achieve the known benefit of eliminating the Vbs term; (ii) predictable result — Witters' equation (2) tells the designer exactly what happens when Vbs→0; (iii) design incentive — the specification's own admitted market pressure toward single 3 V/2 V supplies where "the margin between the threshold voltage Vt and the power supply voltage Vdd is small."

Claims 3–6: claim 3 (P-channel in N-well) is the routine conductivity-type mirror of the same structure; claims 4–6 (second/gate capacitor + pass transistor gated by the first capacitor; anti-phase clocks on adjacent stages; gate of one stage tied to the next stage's capacitor) are, respectively, the known dynamic gate-prebias technique, the standard two-phase clocking already shown in the admitted FIG. 19, and a known cascade coupling. Each is separately obvious over the FIG. 22/Witters base in view of ordinary design practice.

Expected patent-owner rebuttal and its weakness: the owner will argue synergy — that the body-tie + isolated wells, combined, produce the V_F-limited operation described in FIGS. 5A–5F and the ~47 V vs. ~20 V example. But the ~47 V result is directly computable by substituting V_F for Vt in the patent's own equation (1); there is no unexpected-result story, because Witters had already published the model. That is the classic KSR "predictable results" scenario and it favors the challenger.

Group B — Claim 7 (dual-capacitor stage; gate clock amplitude > Vdd)

Proposed combination: Witters / admitted FIGS. 18–22 pump + the known bootstrap (clock-boosting) technique; with US 4,016,476 for the separate gate-drive lead.

• The base pump and the two-phase clock generation from CK via NANDs and inverters are admitted (FIG. 19), and the specification itself concedes that the clock amplitude is simply "equal to a power supply voltage Vdd" — a description of a design choice, not a hidden structure.
• The specification further concedes that the amplitude-boosting generators are conventional: "any units may be employed which operate to receive clock pulse signals CLK2 and CLK3 … and control the amplitudes thereof." An applicant's own characterization that the non-claimed generator is arbitrary is strong evidence that the only novel element is the placement of a second capacitor on the gate — a structural arrangement US 4,016,476 already shows in spirit by using a separate gate lead driven in inverted relationship to the drain lead.
• The purpose of over-supply gate drive — ensuring the pass transistor is fully on so that the Vt drop disappears — is the recognized, long-known function of bootstrap-capacitor clock boosting (used in DRAM word-line drivers and bootstrap pump stages well before 1994) and is also implied by Witters' own (Vdd − Vt) analysis: if Vt bites into the per-stage gain, drive the gate above Vdd.

KSR rationale: known technique to improve a known function; the combination of a familiar pump stage with a familiar bootstrap gate-drive yields the predictable result of eliminating the per-stage Vt loss. Weakest link: I did not locate a specific pre-April-1994 reference expressly claiming "a clock whose amplitude exceeds the supply voltage drives the charge-transfer gate." If the office/challenger cannot produce one, claim 7 (and the second aspect of claim 1) rests on level-of-skill + the applicant's own admission rather than a clean reference — this is the softest part of the case, and it should be flagged as an evidentiary gap rather than overstated.

Group C — Claim 1 (the two techniques combined)

Claim 1 = Group A elements + Group B elements (two capacitors, two clock generators, second clock amplitude > Vdd, source tied to well, wells isolated).

No single reference of record anticipates; the case is a pure combination obviousness argument:

Witters/admitted pump (base architecture, Vt-limited) + JP-A-61-254078 (express problem statement: substrate effect destroys gain) + US 4,016,476 (body-tied source; PN-junction conduction) + a known bootstrap/clock-boost generator (over-supply gate drive).

Because both sub-techniques attack the same identified problem (the per-stage voltage loss term (Vφ − Vt) in Witters' equation (1)), and because Witters' paper itself frames the figure of merit as (Vφ − Vt), a POSITA had an explicit incentive to attack both terms simultaneously — raise Vφ (boost the gate clock) and remove Vt (tie body to source). Under KSR, combining two known solutions to a single recognized deficiency in a known device is the paradigm of obviousness.

5. § 103 Rationale summary (short form)

6. Objective indicia / secondary considerations

• Long-felt need and failure of others: Supported. The specification admits that at Vdd = 2.0 V even 100 stages yield only ~12 V, and that the JP-A-61-254078 graded-Vt approach fails ("the increase of the threshold voltage Vt due to the substrate effect can not be suppressed") and adds photomask/implant cost. This cuts for non-obviousness.
• Commercial success / licensing: No evidence located (patent expired 2023-09-05; no litigation found per the prior sections). Neutral.
• Unexpected results: Weak for the patent owner — the reported improvements track directly from Witters' published equations (1)/(2) once V_F replaces Vt. Predictability of the result is the challenger's best answer to the "47 V vs. 20 V" narrative.

7. Evidentiary gaps and cautions

1. Claim set incomplete. Only claims 1, 2, and 7 (plus 3–6 as dependents) were verified. The specification's "fourth aspect" (grouped substrate regions with independently controlled potentials — positive- and negative-HV variants) implies an additional independent claim that could not be read verbatim. That claim should be analyzed separately; the Group A reasoning (FIG. 22 single substrate group → divide into ≥2 groups) applies with equal or greater force to it.
2. Do not import post-1994 art. WO 98/16010 / US 6,100,557 / US 6,285,240 / US 6,472,666 / US 6,160,723 are not prior art against a 1994 priority date. Their appeal is obvious; their admissibility is nil. If a challenger relies on them, that is a defect, not a feature.
3. Claim 7's clock-boost reference is the soft spot. The record I could assemble supports it via level-of-skill, the applicant's admission, and the known bootstrap technique, but I did not verify a specific pre-1994 printed publication that drives a charge-transfer gate with a sub-supply-exceeding clock. Stated as an uncertainty, not a finding.
4. JP-A-61-254078 is a Japanese publication; a challenger should confirm the publication date and secure a certified translation plus, ideally, its family equivalent.
5. Prior-art keyword extraction on the patent page ("stages; terminal; mos transistor; booster circuit; transistor") is algorithmic, not examiner-cited art; it is useful only as an indicator of claim breadth.

Bottom line: Claim 2 (and its dependents) is the most vulnerable — it is effectively the admitted FIG. 22 pump plus the textbook body-tie remedy (US 4,016,476) plus routine well isolation. Claim 7 is probably obvious given the applicant's own admission that the amplitude-controlled clock generator may be "any unit," though the pre-1994 documentary support is thinner. Claim 1 falls as a combination of two known fixes (raise Vφ; zero out Vt) aimed at the single (Vφ − Vt) deficiency that Witters' 1989 paper had already quantified.

Grounding URLs

• https://patents.google.com/patent/[US7102422B1](/patent/US7102422B1)/en (specification, Background, equations (1)–(2), cross-sections FIGS. 6/10/14)
• https://ieeexplore.ieee.org/document/[572617](/patent/572617) (Witters et al., IEEE JSSC 24(5):1372–1380, 1989)
• https://doi.org/10.1109/JSSC.1989.572617
• https://patentimages.storage.googleapis.com/88/60/cc/3eddda1dc0eb99/US4016476.pdf (US 4,016,476, "Booster circuits," Apr. 5, 1977)
• https://patentimages.storage.googleapis.com/2d/74/54/cd51767d3c3c0b/US20020125935A1.pdf (US 2002/0125935 A1 — same family; JP-A-61-254078 discussion)
• http://data.epo.org/publication-server/rest/v1.2/patents/EP1237266NWA2/document.xml (EP 1 237 266 A2 — published claim wording)