US 6002630

I'll search for authoritative information on this patent number.

Let me verify the patent's legal/prosecution record and litigation history.

Let me do a final targeted check for any 2026 appellate activity and confirm the official record.

US Patent 6,002,630 — "On chip voltage generation for low power integrated circuits"

Sourcing note: I retrieved the authoritative full text from Google Patents (https://patents.google.com/patent/[US6002630](/patent/US6002630)/en) and corroborated the bibliographic/prosecution data against secondary record repositories (uspto.report, everypatent, Justia Patents, Docket Alarm PTAB filings, RPX Insight, Patexia, National Law Review's PTO Litigation Center report). I was not able to directly query USPTO PatentCenter or the CAFC's own docket system; the statements below about those are based on the sources listed, and I flag the one item where I have no authoritative information. I have kept the identifier exactly as given: 6002630 (i.e., U.S. Patent No. 6,002,630).

Bibliographic data

Abstract (as published)

An on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts) includes a sense circuit on the integrated circuit which generates an output indicating a level of the supply voltage. The on chip voltage supply circuit generates the on chip voltage in response to the output of the sense circuit and the supply voltage. The sense circuit output indicates the level of the supply voltage so that the on chip voltage supply circuit is able to adapt the amount of boosting utilized to produce the on chip voltage in response. The on chip voltage supply circuit generates the word line voltage at a node coupled to word line driving circuits in the device.

Factual context / problem addressed

The specification states that as supply voltages dropped to a range of about 2.7–3.6 V, flash memory word lines still needed a read potential of 4 V or more. A fixed-boost-ratio pump sized for both extremes of the supply range would require about a 1.5 V boost and would produce ~4.2 V at the low end but ~5.1 V at the high end, wasting power and causing transient fluctuations that slow sensing. The invention senses the supply level on-chip and varies the amount of boosting accordingly. The description cites U.S. Pat. No. 5,511,026 ("BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES") as prior art. Address-transition detection is described as using the applicants' co-pending application Ser. No. 08/751,513, filed Nov. 15, 1996, titled "ADDRESS TRANSISTION DETECTION CIRCUIT" (spelling as in the patent).

Plain-language overview of the independent claims

There are three independent claims — 1, 10, and 26 (37 claims total).

Claim 1 — Integrated circuit with supply-responsive boosting (the generic claim).
An IC has a power-supply input that receives a supply voltage within a specified range, and has on-chip components that need a higher voltage than that range. Two things are added:

1. A sense circuit tied to the supply input that outputs a signal indicating the supply voltage's level; and
2. An on-chip voltage supply circuit tied to both the sense circuit and the supply input that generates the higher on-chip voltage in response to both the sense output and the supply voltage itself.
   The key limitation is that the on-chip supply circuit contains a voltage boosting circuit whose input is coupled to the supply input, and which boosts that input voltage by an amount that depends on the sense circuit's output — i.e., variable boosting based on sensed supply level, not a fixed boost ratio.

Claim 10 — Memory device with a supply-responsive word-line voltage node.
An IC memory device has: a supply input in a specified range; a memory array whose word lines are coupled to memory cells having a first threshold below the read voltage (first state) and a second threshold above the read voltage (second state); address inputs; word-line driving circuits that apply a word-line voltage to selected word lines per the addresses; a sense circuit producing an output indicating the supply voltage level within the range; and an on-chip voltage supply circuit connected to the sense circuit, the supply input, and a node that feeds the word-line drivers. That circuit generates the word-line voltage at the node in response to both the sense output and the supply voltage. (Notably, claim 10 does not itself recite the boost-amount-depends-on-sense-output limitation that appears in claim 1 and in dependent claim 15.)

Claim 26 — Floating-gate memory device with sectioned decoders and address-transition detection.
This is the most specific independent claim. It requires all of:

• A supply input within a specified range;
• An array of floating gate memory cells programmable to a first threshold below the read voltage and a second threshold above it;
• Address inputs and word-line driving circuits organized as multiple word-line decoder sections, each identified by a portion of an address, plus a selector that connects the node to the selected decoder section based on that address portion;
• Address transition detection circuits that separately detect (a) a section transition in the portion of the address identifying a decoder section and (b) a word line transition in another portion of the address identifying a word line within a section; and
• A sense circuit indicating the supply voltage level, with the on-chip voltage supply circuit generating the word-line voltage at the node in response to the sense output, the address transition detection circuits, and the supply voltage.

Selected dependent-claim themes: binary above/below-threshold sense output (claims 2, 11, 27) or multi-threshold sensing (3, 12); separate first/second boosting elements adding a smaller/greater amount (4, 5, 13, 14, 27); supply range about 2.7–3.6 V with on-chip voltage > 3.6 V (6, 16, 29) and specifically about 4.5–5.2 V (7, 17, 30); an idle pump maintaining an idle level (8, 18, 31); pumping triggered by a control-signal transition (9, 19); decoder sections plus selector (20); and the pump architecture of an idle pump + section boost pump + word line boost pump (21, 32), a section-transition signal distinguished from a word-line-only transition signal (22, 33), and an additional boost pump for section transitions (23).

Litigation and PTAB history found

• ITC Investigation No. 337-TA-909 — listed as a family litigation item for this patent (Macronix-related; Spansion was the respondent/petitioner side per the PTAB filings).
• IPR2014-01118 — Spansion Inc., Spansion LLC, Spansion (Thailand) Limited v. Macronix International Co., Ltd., reviewed U.S. Patent 6,002,630. Filed 2014-07-11; institution decision 2015-01-21; terminated-settled 2015-01-30. The challenged claims were 1–6 and 10–16 (matching the claims raised in the ITC case), with claims instituted per the PTAB record. The parties filed a Joint Motion to Terminate Proceeding Pursuant to 35 U.S.C. § 317 on 2015-01-28 asserting a settlement resolving all disputes over the patent-at-issue; the Board's judges were Justin Busch, Kalyan K. Deshpande, and Peter P. Chen. The IPR did not reach a final written decision on the merits.
• The patent also appears in the family's broader litigation set tracked by Darts-IP (family 21851721).

CAFC 2026 dockets — no authoritative information

I found no CAFC docket, appeal, or 2026 activity involving 6002630. My searches for a Federal Circuit 2026 appeal concerning this patent number returned nothing relevant, and the patent's own record shows it expired (anticipated expiration 2017-11-21) with the only PTAB proceeding having been terminated by settlement in January 2015. I also cannot rule out a docket entry that my searches did not surface — I did not have direct access to the CAFC's docket system, so this should be treated as "not found," not as a certified negative.

Uncertainties to flag

1. Claims 34–37: the retrieved full text truncated mid-claim-33, so I cannot characterize the final four claims. The claims listing states "(37)" and independent claims are 1, 10, and 26.
2. Collateral assignments: The assignments to Nintendo (2001) and back to Macronix (2013) are recorded as "COLLATERAL ASSIGNMENT" — this is a security interest, not necessarily a transfer of title. Current assignee on the record is listed as Macronix International Co., Ltd.
3. Priority lineage: Google Patents states priority claimed from PCT/US1997/021513 with a 1997-11-21 priority date; I did not independently verify the PCT filing date or whether it is a §119/§365 priority claim or a §120 continuation-type relationship with the same-day application.
4. No CAFC 2026 activity confirmed — as noted above, this is a negative search result, not a verified absence.

I'll search for litigation involving US patent 6002630 specifically, prioritizing sources like Unified Patents, PACER/CAFC, and ITC records.

Good progress. Let me dig into the ITC investigation and any district court cases.

Let me confirm the outcomes of the ITC investigation and the district court case, plus any other jurisdictions.

Litigation involving U.S. Patent No. 6,002,630

Patent identified: U.S. 6,002,630 (application 09/029,945; filed Nov. 21, 1997; granted Dec. 14, 1999), "On chip voltage generation for low power integrated circuits," inventors Weitong Chuang, Chun-Hsiung Hung, Kuen-Long Chang; original assignee Macronix International Co., Ltd. Google Patents' own "Family has litigation" flags list only two proceedings for this family: PTAB case IPR2014-01118 and U.S. ITC case 337-TA-909. My searches confirm those two, and I found no additional U.S. or foreign case in which the '630 patent itself was asserted.

Below are the proceedings identified. Where I could not verify a final outcome from the available sources, I say so explicitly rather than guess.

1. ITC Investigation No. 337-TA-909 — § 337 action (the principal enforcement vehicle for the '630 patent)

Sources: ITC Notice of Institution, 337-TA-909 (https://www.usitc.gov/secretary/fed_reg_notices/337/337_909_notice01282014sgl.pdf); ITC notice at 79 Fed. Reg. 6227–228 (Feb. 3, 2014) (https://www.govinfo.gov/content/pkg/FR-2014-02-03/pdf/2014-02092.pdf); 79 Fed. Reg. notice on Tellabs substitution (https://www.govinfo.gov/content/pkg/FR-2014-09-10/pdf/2014-21484.pdf); Lexology (https://www.lexology.com/library/detail.aspx?g=f210d879-fbe3-46c0-bcc2-d7b6c034b115).

2. IPR2014-01118 — Inter partes review of the '630 patent (PTAB)

This IPR was part of a broader Spansion multi-petition strategy announced publicly on July 21, 2014, in which Spansion challenged three Macronix patents — U.S. 6,552,360, U.S. 6,100,557, and U.S. 6,002,630 — the same patents Macronix was then asserting against Spansion in ITC Investigation 337-TA-909.

Sources: RPX Insight (https://insight.rpxcorp.com/ptab/1687-spansion-v-macronix-international-co-ltd-ipr-of-630); Patexia (https://services.patexia.com/lawsuits/Spansion-Inc-v-Macronix-International-Co-Ltd-id-63429); National Law Review PTO Litigation Center Report, July 14, 2014 (https://natlawreview.com/node/33526/printable/pdf); Spansion press release as reported by MarketScreener, July 21, 2014 (https://hk.marketscreener.com/quote/stock/SPANSION-INC-[6334162](/patent/6334162)/news/...).

Related parallel litigation — NOT directly asserting the '630 patent

The '630 patent arose out of the broader Macronix v. Spansion dispute. For completeness (and to avoid overstating the '630's footprint), the parallel proceedings below were part of the same campaign but, based on the pleadings/records surfaced, asserted different Macronix patents (e.g., the '360, '557, '052, '772, '826, '757, '267, '324 and '330 patents) rather than the '630:

• Macronix Int'l Co., Ltd. v. Spansion Inc. et al., No. 3:13-cv-00679 (E.D. Va.), filed Oct. 2, 2013 — asserted seven Macronix patents (the '052, '772, '826, '757, '267, '324, and '330 patents), not the '630. This case was subsequently transferred to the N.D. Cal. and docketed as No. 5:14-cv-01890 (BLF) (also cited as 4:14-cv-01890), Macronix Int'l Co., Ltd. v. Spansion Inc. et al., filed April 24, 2014, before Judge Beth Labson Freeman. On Dec. 12, 2014 the court granted in part the defendants' motion to stay (Docket #123), effectively staying the case pending the ITC proceedings. Note: portions of the E.D. Va. record also reference a Macronix complaint decided as Macronix Int'l Co. v. Spansion Inc., 4 F. Supp. 3d 797 (E.D. Va. 2014) (a pleading-sufficiency/Twombly–Iqbal decision), and a later N.D. Cal. action No. 5:14-cv-01946.
• Spansion LLC v. Macronix International Co., Ltd. et al., No. 3:13-cv-03566 (N.D. Cal.) — a counter-suit filed by Spansion (docket report dated Aug. 1–2, 2013), asserting Spansion patents such as U.S. 6,639,416, 6,459,625, 7,315,536, 6,900,124, and 7,018,922 against Macronix — again not the '630.
• Macronix's German action — reported July 21, 2014 (a European counterpart of the '557 patent), i.e., not the '630.

Sources: Google Patents litigation note via Darts-IP; ITC / Docket Alarm joint claim-construction filings; Spansion's N.D. Cal. docket report (https://www.docketalarm.com/... US 09/404,394 ...); UniCourt case summary for Macronix Int'l v. Spansion, No. 4:14-cv-01890 (https://unicourt.com/case/rc-db1-macronix-international-co-ltd-v-spansion-inc-et-al-[155677](/patent/155677)); CourtListener, Macronix Int'l Co. v. Spansion Inc., 4 F. Supp. 3d 797 (https://www.courtlistener.com/opinion/[7305143](/patent/7305143)/macronix-international-co-v-spansion-inc/).

Bottom line

• Two proceedings specifically involve U.S. 6,002,630:

  1. ITC Inv. No. 337-TA-909 — Macronix (complainant) v. Spansion and downstream respondents (respondents); instituted Jan. 28, 2014; '630 claims 1–6 and 10–16 asserted; target date May 4, 2015. Final disposition not verified from the sources I could retrieve.
  2. PTAB IPR2014-01118 — Spansion (petitioner) v. Macronix (patent owner); filed July 11, 2014; instituted Jan. 21, 2015; terminated by settlement (Jan. 30, 2015).

• No district-court case asserting the '630 patent was identified. The existing Macronix/Spansion district-court and counter-suit dockets that I found asserted other Macronix/Spansion patents, not the '630.

Caveats / limits

I was unable to complete confirmation of (a) the final Commission determination or termination/settlement of 337-TA-909, (b) whether the '630 was ever added to any district-court complaint in the transferred N.D. Cal. action or a later refiled action, and (c) any non-U.S. (e.g., German) case specifically asserting the '630's foreign counterparts. Those items should be verified against the ITC EDIS docket (https://edis.usitc.gov), PACER, and the PTAB End-to-End docket before being relied upon. If you want, I can run targeted follow-ups on those specific gaps.

Proceedings overview

One (1) AIA trial proceeding has ever been filed on US 6002630 — IPR2014-01118 — and it ended in a settlement-driven termination after institution but before any Final Written Decision: 0 claims canceled, 0 claims sustained on the merits, 0 institution denials, 0 active proceedings. The patent therefore carries no PTAB-based invalidity finding a defendant can borrow, but it also carries no pro-patent FWD hardening it; claims 1–6 and 10–16 were put in play and then abandoned by the petitioner, leaving them untested. Two things matter more than the PTAB record for a defendant today: (a) the '630 patent expired on 2017-11-21 and (b) no post-settlement assertion of the '630 patent appears anywhere in the public record.

Data-integrity note (flag): the structured "PTAB proceedings on file" block states the USPTO ODP API returns no AIA trials for this patent. Web research contradicts that: IPR2014-01118 is confirmed by the USPTO PTO Litigation Center report (filed 2014-07-11), by the Board's own Joint Motion to Terminate paper (2015-01-28), and by the Google Patents litigation flag on the patent page itself. Treat the ODP "none" as an ingest gap, not as evidence of no activity. Separately, the "Petitioner: Unified Patents PTAB Data" line on the Google Patents page is a CC-BY data attribution, not a party — Unified Patents never petitioned this patent.

IPR2014-01118 — Spansion Inc., Spansion LLC, Spansion (Thailand) Ltd. v. Macronix International Co., Ltd.

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2014-07-11 (Tech Center 2800)
• Status: Terminated-Settled — verbatim status from the docket: "Terminated-Settled." Plain English: the Board instituted trial on 2015-01-21, the parties settled, and the Board terminated the proceeding in its entirety on a joint § 317(a) motion before deciding the merits — so no Final Written Decision issued and no claim was canceled or confirmed.
• Judge panel: Justin Busch, Kalyan K. Deshpande, and Peter P. Chen (per RPX/Patexia docket metadata). Caution: Patexia's "Judge Writing the Final Decision: Peter P. Chen" is a field artifact — there was no FWD; Paper 18 (2015-01-28) is the operative termination paper.
• Petition grounds: Challenged claims 1–6 and 10–16 of the '630 patent. The specific prior-art references and statutory bases (§ 102 / § 103) were not retrievable from the public record in this pass — the petition PDF and institution decision were not surfaced. I will not guess at the art. What is confirmed: the challenge was filed in parallel with, and as a direct response to, Macronix's ITC assertion of the same claim set (claims 1–6 and 10–16) in Inv. No. 337-TA-909.
• Institution decision: Instituted 2015-01-21 (within the statutory 3-month window after the 2014-07-11 filing; POPR and any preliminary response not retrieved). The Board's institution reasoning is not in the record I could assemble — do not quote it as if it exists. The practical inference from the parties' own filing is that at least one ground met the § 314(a) threshold.
• Final Written Decision: None. The joint motion states: "Here, the Board has not decided the merits of the proceedings. In fact, this proceeding was only recently instituted." (Paper 18, 2015-01-28).
• Settlement / termination: Co-petitioners and Patent Owner filed a Joint Motion to Terminate Proceeding Pursuant to 35 U.S.C. § 317 on 2015-01-28 (Board authorized 2015-01-27; Board action 2015-01-30). The parties represented that the settlement agreement resolves all disputes between them involving the '630 patent and filed a true copy under § 317(b) / 37 C.F.R. § 42.74(b) with a request to treat it as business confidential information. Terms are confidential and not public. The settlement was part of a global Macronix–Spansion peace — Spansion's Form 10-K states the ITC-909, ITC-893, ITC-916 and the N.D. Cal. cases "settled effective as of January 22, 2015." ITC-909 was terminated on the ALJ's ID (2015-02-18), with the Commission declining review on 2015-03-12.
• Appeal: None. Because the proceeding terminated before a FWD, there was nothing to appeal; institution decisions are unappealable in any event (Cuozzo; Thryv). No Federal Circuit docket exists for this patent.
• Defensive value: Low-to-moderate, and indirect. Spansion's IPR produces no estoppel the current defendant can inherit and no invalidity holding to cite. Its value is evidentiary/contextual: it shows a sophisticated flash-memory competitor (Spansion, with Fish & Richardson and Ropes & Gray involved in the parallel ITC fight) believed claims 1–6 and 10–16 were worth attacking and got past institution — useful framing for a § 103 obviousness theory you would have to build yourself. It does not let you say "claim 1 is dead"; claim 1 is very much alive on the public record.

Strategic summary

Claim status of US 6002630. There is no PTAB cancellation of any claim. The complete picture: Canceled: none. Sustained on the merits: none (nothing was ever decided). Untested: all of them — and note the challenge was not claim-set-wide: only claims 1–6 and 10–16 were ever put at issue, leaving claims 7–9 and 17–37 never challenged in any AIA trial. If a demand letter or complaint cites claims 1–6 or 10–16, you cannot point to a PTAB disposition; if it cites claims 7–9 or 17–37, those claims have never even faced an AIA petition. The patent's status line is Expired – Lifetime, with anticipated expiration 2017-11-21 (20 years from the 1997-11-21 filing; priority claimed from PCT/US1997/021513).

Estoppel landscape. § 315(e)(2) estoppel never attached to anyone. Estoppel under § 315(e) is triggered only by a final written decision, and IPR2014-01118 was terminated under § 317(a) pre-FWD. So Spansion (and its successors/privies) is not estopped from re-litigating the same grounds in district court, and — importantly for you — no third party inherits any estoppel benefit either. Practically, this means every prior-art ground remains nominally available to a new petitioner or a district-court defendant, including art Spansion raised and art it didn't. Two caveats: (1) a new IPR today would be time-barred for anyone served with an infringement complaint more than one year ago (§ 315(b)) and is pointless on an expired patent; (2) the six-year damages lookback of § 286 means a patent that expired 2017-11-21 supports no recoverable damages whatsoever for suits filed after roughly 2023-11-21.

Pattern signals. The '630 patent was swept into a single, coordinated counter-attack by one petitioner group (Spansion) as part of the Macronix–Spansion flash-memory war of 2013–2015, alongside IPRs on sibling patents (Spansion's July 2014 petitions on the '557 and '360 patents; Macronix's own petitions on Spansion's '625, '416, '536 and '027 patents). The '630 IPR was not a defensive-aggregator filing — Unified Patents never petitioned this patent, despite the attribution text on the Google Patents page. Macronix never had to defend a FWD and never pursued a PTAB appeal on this patent. The patent is a 1997-priority, 1999-issued flash voltage-generation patent that expired in 2017; the last documented assertion was the ITC-909 / N.D. Cal. campaign that settled in January 2015. The absence of any IPR post-2015 is not a sign the patent is "hardened" — it is a sign nobody has needed to attack an expired patent.

Recommended next steps

1. If you are a defendant and the demand/complaint cites any claim of the '630 patent, lead with expiration, not PTAB. The patent expired 2017-11-21 (Google Patents status line: "Expired - Lifetime"; anticipated expiration 2017-11-21). There is no injunction available and no § 286 damages window if suit is filed now. That is a dispositive posture independent of the IPR record.
2. Do not cite IPR2014-01118 as an invalidity finding. You may cite it only for what it says: alleges challenged claims 1–6 and 10–16; instituted 2015-01-21; terminated-settled on the joint § 317 motion filed 2015-01-28; no FWD. Lead source: Joint Motion to Terminate (Paper 18, 2015-01-28), available at docketalarm — https://www.docketalarm.com/cases/PTAB/IPR2014-01118/Inter_Partes_Review_of_U.S._Pat._6002630/docs/01-28-2015-Patent_Owner/Motion-18-Joint_Motion_to_Terminate_Proceeding.pdf . Docket metadata: https://insight.rpxcorp.com/ptab/1687-spansion-v-macronix-international-co-ltd-ipr-of-630 . Official record: PTAB E2E / Patent Trial and Appeal Board End-to-End, https://ptacts.uspto.gov/ptacts/ (search IPR2014-01118).
3. Get the two documents I could not retrieve — they are the only claim-level substance that exists. (a) Spansion's Petition (filed 2014-07-11) to identify the § 102/§ 103 grounds and references for claims 1–6 and 10–16; (b) the Decision on Institution (2015-01-21) to see which claims/grounds were instituted and the panel's reasoning. Both should be free in PTAB E2E under IPR2014-01118. If a new IPR or district-court invalidity contention is contemplated, these are your best starting theories — institution on at least one ground is a meaningful signal, and being the first filer on this art avoids redundancy attacks.
4. No active proceedings, so no trial-stage milestones to track. If the ODP ingest is later corrected to reflect IPR2014-01118, the only milestone is closed: terminated 2015-01-30 by Board action on the joint motion. There is no institution deadline, hearing, or FWD due date outstanding. If a new petition were somehow filed, the statutory schedule would be: institution ≤6 months from filing (§ 314(b)), FWD ≤12 months from institution (§ 316(a)(11)).
5. Treat the settlement agreement as unreachable. It was filed under seal with a business-confidentiality request under § 317(b)/§ 42.74(c) — the license/royalty terms will not become public, and there is no collateral document trail to mine.
6. Correct the record internally. Note for your file that the ODP "no AIA trial proceedings" result is incomplete; the proceeding is real and the patent page itself links it (Google Patents flags "PTAB case IPR2014-01118 filed (Settlement)" and cites the ITC case 337-TA-909).

I'll research the assignment record for this patent. Let me run several targeted searches.

Let me try to locate the specific reel/frame records.

I hit my search-step limit before I could pull the reel/frame data from the Assignment Center itself, so I must flag a hard data gap up front and then report what is grounded.

Assignment & Ownership Analysis — US 6,002,630

Critical sourcing caveat (read first). I was not able to open the USPTO Patent Assignment Search (Assignment Center) record for this patent from my available tooling. Every search aimed at extracting reel/frame numbers returned either unrelated hits (a freight-carrier list, a trademark TTAB record for Nintendo of America reel 4740/0814 — a trademark, not this patent) or nothing. Consequently:

• No reel/frame numbers are reported below. I will not invent them. Where the format asks for a reel/frame I have written [not retrieved].
• No correspondent-of-record names are reported. The correspondent field is the single most probative field for this task and I could not read it. This materially weakens signal #3.
• The dates below come from Google Patents legal events (https://patents.google.com/patent/US6002630/en), which mirror the assignment record's recordation dates but do not display reel/frame or execution dates. They are therefore recordation dates unless stated otherwise.

Verification link: https://assignmentcenter.uspto.gov/ (patent number search) and https://assignment.uspto.gov/patent/index.html

Inventors

Unusual patterns: None evident. All three inventors are contemporaneous Macronix personnel on a Macronix-filed, Macronix-priority application (priority 1997-11-21; external priority from PCT/US1997/021513, family member WO1999027537A1). The 1998-03-04 record is a standard "ASSIGNMENT OF ASSIGNORS INTEREST" from all three inventors to the company — the ordinary employment/obligation assignment, not a distressed or post-departure conveyance.

Explicit uncertainty: I have no authoritative information on whether any inventor departed Macronix within 12 months of filing. I did not verify subsequent inventor affiliations, and I am not going to assert a "mass departure" pattern that I cannot support. The 12-month-departure tell requested in the brief is not present on the evidence I have — it is simply unknown.

Original assignee

Macronix International Co., Ltd. (No. 16, Li-Hsin Road, Science Park, Hsin-chu, Taiwan) — named as both applicant at filing and assignee on the 1998-03-04 record.

• Primary line of business: fabless/IDM semiconductor memory — NOR flash, NAND flash, mask ROM, and ROM-based custom silicon (famously Nintendo cartridge ROM).
• Did they ship a product embodying the claims? Effectively yes. The '630 patent covers the on-chip read-mode word-line voltage generation used in Macronix's own flash parts. Macronix's own ITC complaint (Inv. 337-TA-909) asserted a domestic industry in the United States based on products practicing the asserted Macronix patents — i.e., Macronix asserted these claims against a competitor in respect of its own shipped silicon, not a paper portfolio.
• Current status: Operating. Macronix remains an active, publicly listed memory manufacturer (Taiwan Stock Exchange). It did not dissolve, and it did not file bankruptcy. (The entity that went through Chapter 11 in this dispute is Spansion — the accused infringer, not the assignee. That distinction matters for signal #6.)

Assignment timeline

All four recordation events below are the complete set visible on Google Patents legal events for US 6,002,630. Execution dates and reel/frame are not available to me.

• Executed [not retrieved] / recorded 1997-11-21 — Reel [not retrieved]/[not retrieved]

  • Conveyance: Application filed by / priority to applicant (filing event, not a title transfer)
  • Assignor: (n/a — filing)
  • Assignee: Macronix International Co., Ltd.
  • Correspondent: [not retrieved]
  • Context: Original filing — the priority-establishing event; also claims external priority from PCT/US1997/021513 (WO1999027537A1).

• Executed [not retrieved] / recorded 1998-03-04 — Reel [not retrieved]/[not retrieved]

  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS) — i.e., Assignment
  • Assignor: Chang, Kuen-Long; Chuang, Weitong; Hung, Chun-Hsiung (the three inventors)
  • Assignee: Macronix International Co., Ltd.
  • Correspondent: [not retrieved] — firm probably visible on the face of the 1998 Hsinchu/DC filing; I could not read it. Cannot flag recurrence without it.
  • Context: Original employment/obligation assignment — inventors' rights vested in the operating company. Ordinary, not a fire-sale.

• Executed [not retrieved] / recorded 2001-07-24 — Reel [not retrieved]/[not retrieved]

  • Conveyance: COLLATERAL ASSIGNMENT
  • Assignor: Macronix International Co., Ltd.
  • Assignee: Nintendo Co., Ltd.
  • Correspondent: [not retrieved]
  • Context: Securitization / lien, not a title transfer. Macronix pledged the patent as collateral to Nintendo. The timing and the parties are consistent with the 2001-era Macronix–Nintendo–MegaChips manufacturing/supply arrangements (mask ROM and flash memory for Nintendo platforms), i.e., a performance or payment security interest taken by a major customer. I have not verified the underlying loan/supply agreement and flag that as an inference, not a finding.

• Executed [not retrieved] / recorded 2013-12-27 — Reel [not retrieved]/[not retrieved]

  • Conveyance: COLLATERAL ASSIGNMENT (per the record, transferring back) — functionally a release / reassignment of the security interest
  • Assignor: Nintendo Co., Ltd.
  • Assignee: Macronix International Co., Ltd.
  • Correspondent: [not retrieved]
  • Context: Release of security interest / ownership cleanup. Nintendo's collateral was returned to Macronix, restoring clean record title. Timing note: this recordation is dated 2013-12-27 — the same date Macronix filed its ITC §337 complaint against Spansion (per the Federal Register institution notice, complaint filed December 27, 2013). The record was cleaned up on the day the litigation began. This is a standing/ownership housekeeping step incident to assertion, not an NPE-style pre-litigation transfer to an asserter.

No post-2013 assignment exists on the record. The chain terminates at Macronix.

Timeline diagram

timeline
    title Ownership of US 6002630
    1997 : Application filed by Macronix
         : PCT priority claimed
    1998 : Inventors assign to Macronix
    1999 : Patent issued 14 Dec 1999
    2001 : Collateral assignment to Nintendo
    2013 : Nintendo collateral released to Macronix
         : ITC complaint filed vs Spansion
    2014 : Spansion files IPR challenge
    2015 : IPR terminated by settlement
    2017 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. The only entities in the chain are Macronix International Co., Ltd. and Nintendo Co., Ltd. — both large operating corporations with substantial product businesses. There is no "IP / Holdings / Licensing / Ventures" entity, no single-purpose LLC, and no registered-agent service address anywhere in the record. The patent never left operating-company hands.

2. Known asserter in the chain — NOT PRESENT. Neither Macronix nor Nintendo appears on any of the enumerated NPE/asserter lists (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, DGC, Spangenberg entities), nor in the RPX/Unified high-frequency-plaintiff directories so far as I found. To the contrary, the assertion here was complained by Macronix itself, with its own U.S. subsidiary Macronix America, Inc., at the ITC — the classic operating-company plaintiff posture, not an NPE front.

3. Repeat correspondent across the chain — UNKNOWN / INSUFFICIENT DATA. This is the field I most needed and could not obtain. I cannot state whether the same attorney or firm of record appears on the 1998, 2001 and 2013 records. Do not read the absence of a flag here as a negative finding; it is a data gap, and it is the one thing that would most change the confidence level of this analysis. (Verify at the Assignment Center record — the correspondent is displayed on the individual assignment detail page.)

4. Cascading transfers — NOT PRESENT. There are only two recorded title-affecting events across the patent's life (2001 and 2013), twelve years apart, and the 2001 event is a lien, not an ownership change. There is no chain of LLCs, no common-correspondent clustering, and nothing resembling the <24-month cascading-transfer pattern.

5. Pre-litigation transfer — NOT PRESENT (with a closely related observation). No assignment to an asserter occurred. I did find a timing correlation worth recording: the 2013-12-27 collateral release and the 2013-12-27 ITC complaint share a date. That is ownership-record hygiene immediately before suit — Macronix needed uncontested record title to plead ownership in the §337 complaint — but it is not the NPE tell (which requires the suit to be enabled by a transfer to a non-practicing party). Here the suing party is the original owner and a practicing manufacturer.

6. Bankruptcy fire-sale — NOT PRESENT. Macronix has not filed for bankruptcy and did not sell this patent in insolvency proceedings. Caution: the bankruptcy in this story belongs to Spansion (Chapter 11 in 2009), the accused infringer and IPR petitioner, which is the opposite side of the transaction from what this signal tests.

7. Privateering — NOT PRESENT. Privateering requires an operating company to funnel patents to an NPE that asserts on the operating company's behalf. Macronix asserted in its own name (with Macronix America as co-complainant) against Spansion. No NPE intermediary exists on the chain, so there was no privateer.

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified Patents or OIN. It terminates at Macronix. (Note the inversion: Unified Patents appears in this record only as the source of the PTAB dataset that documents Spansion's IPR2014-01118 against the patent — not as an assignee.)

Verdict

Operating-company assertion.

Justification: the ownership chain runs inventors → Macronix International Co., Ltd. (recorded 1998-03-04) and stays inside practicing semiconductor manufacturers for the patent's entire life — a collateral assignment (lien) to Nintendo Co., Ltd. recorded 2001-07-24, released back to Macronix recorded 2013-12-27, with no assignment to any licensing-only entity. Macronix then asserted claims 1–6 and 10–16 of the '630 patent in its own name against a direct competitor, Spansion, in ITC Inv. 337-TA-909 (instituted 2014-01-29) rather than through an NPE conduit. This is a practicing manufacturer enforcing patents covering its own flash-memory products — the definitional opposite of an NPE posture, and signals #1, #2, #4, #6, #7 and #8 all resolve in that direction.

Confidence limitation: the verdict on the posture is well supported, but signal #3 (repeat correspondent) is unresolved because I could not read the correspondent-of-record fields, and no reel/frame numbers were retrievable by me. Neither gap would plausibly flip the verdict given the named parties' identities, but a direct Assignment Center pull (search patent 6002630) should be run to close out the correspondent field and to capture reel/frame, execution dates, and any records I could not see.

I'll search for the cited prior art references on this patent.

Let me pull the front-page reference lists from primary sources.

Prior-art assessment for U.S. Patent No. 6,002,630 ("On chip voltage generation for low power integrated circuits")

Bottom line up front — a sourcing limitation I must flag

I was not able to retrieve the authoritative front-page "(56) References Cited" list for U.S. 6,002,630 in this session. The authoritative full text you supplied (fetched from Google Patents) renders the specification, claims, abstract and classifications, but it does not include the (56) U.S. Patent Documents / Foreign Patent Documents / Other Publications block. My web searches for that block (patentimages PDF, uspto.report, freepatentsonline, and targeted queries pairing 6002630 with known charge-pump art) returned only tangential documents — e.g., later patents that cite the '630 (EP 1459160 A2 lists US 6002630 A 19991214 CHUANG WEITONG [TW] et al. in its examination citations), and unrelated PTAB petitions — but not the '630's own cited prior art.

Under the standing rule ("If you do not know something with high confidence, say so explicitly rather than fabricating"), I will not invent a (56) list. A fabricated citation set would be worse than an incomplete one, because §102 mapping is date- and disclosure-specific. Below I give (A) the one reference I can confirm from the patent's own text, (B) the internal cross-reference (which is not §102 art), and (C) the fastest authoritative routes to the complete list.

A. Reference expressly identified in the patent text (confirmed)

B. Internal cross-reference — not §102 prior art

The specification also cites the applicants' own co-pending application:

• Ser. No. 08/751,513, filed Nov. 15, 1996, "ADDRESS TRANSISTION DETECTION CIRCUIT" (spelling as in the patent), used for the ATD0 / ATDX address-transition signals feeding the boost, read and auxiliary pumps.

This is a common-ownership cross-reference, not prior art. Because it is the applicants' own earlier-filed work, it is disqualified as §102(a)/(b) art by the inventors' own activity and is not §102(e) art against a common-inventor/common-owner application in the relevant timeframe. Do not map it to any claim.

C. Framework for the §102 analysis once the true (56) list is pulled

Because the effective filing/priority date is 1997-11-21 (with a PCT/US1997/021513 external-priority claim, WO1999027537A1), the date windows are:

• §102(a): art known or used by others in the U.S., or patented/published before the applicants' invention date.
• §102(b): art patented or described in a printed publication more than one year before 1997-11-21, i.e., before 1996-11-21 — the critical statutory bar for the (56) U.S. patents and any 1996-or-earlier foreign publications.
• §102(e): U.S. patents granted on applications filed before 1997-11-21 — this is where most of the (56) "U.S. Patent Documents" will fall, and where a citation dated after 1997 can still be §102(e) art.

For each (56) reference, the mapping question is the same and narrow, because the '630's claims turn on two limitations:

1. "sense circuit… generates an output indicating a level of the supply voltage" (claims 1, 10, 26), and
2. boost amount "depends on the output of the sense circuit" (claims 1, 15, 21, 24, 25, 27, 28, 31, 32).

A reference that discloses only a fixed-ratio or regulator-clamped word-line pump (the vast majority of 1990s DRAM/flash boosted-word-line art — e.g., the Toshiba EP 0 661 710 "boost potential generation circuit," the Mosaid/U.S. 6,055,201 boosted word-line charge pump, the EP 0 210 260 boosted word line, etc., all of which surfaced in my searches) will not anticipate claims 1, 10 or 26, because those references vary pump capacity with refresh cycle or load, not boost amount as a function of sensed supply level. Such references are §103 candidates at most.

D. Where the authoritative prior art actually lives for this patent

The single most useful place to find the prior art that was actually asserted against the '630 is the PTAB petition in IPR2014-01118 (Spansion v. Macronix, filed 2014-07-11, instituted on claims 1–6 and 10–16, terminated-settled 2015-01-30). A petition's Exhibit 1002–10xx set is the exhaustive, litigated prior-art record for this patent. My searches did surface PTAB petition excerpts in the same database (e.g., petitions citing Tanizawa, Ichimura/Ichimaru, and Shibata), but those belong to unrelated IPRs over a temperature-compensated constant-current patent, not to the '630, and I explicitly flag that they must not be attributed to this patent.

Recommended verification steps to close the gap

1. Google Patents → US6002630 → "References Cited" tab (the (56) block that did not render in the text you supplied).
2. USPTO PatentCenter / PatFT full-text for application 09/029,945 — front page (56) list with examiner-cited references, plus the "Other Publications" and any IDS.
3. PTAB End-to-End / IPR2014-01118 Exhibit List — the Petitioner's grounds and exhibits for the '630 itself.
4. ITC EDIS, Inv. No. 337-TA-909 — Macronix's asserted claims (1–6, 10–16) and the Respondents' invalidity contentions, which will name the art relied on.

Consistency check against the previously generated sections

No contradictions: the earlier sections correctly identified the priority date (1997-11-21), the three independent claims (1, 10, 26), the asserted-claim sets in the ITC (1–6, 10–16) and IPR2014-01118 (1–6, 10–16), and the settlement termination. The only item to reconcile is item 1 of the earlier "Uncertainties to flag" (claims 34–37 truncated) — that remains open, and it also means I cannot state a §102 mapping for claims 34–37, since their text is not in the supplied record.

If you can supply the (56) block or the IPR2014-01118 petition, I will produce the full per-reference table (citation | date | description | §102(a)/(b)/(e) category | potentially anticipated claims) directly.

I'll analyze obviousness, but first let me retrieve the prior-art references associated with this patent, since the task instructs me to use them.

Let me pull the front-page "References Cited" list and the citing/related documents for this patent.

Let me try to retrieve the patent's own front-page "References Cited" list directly.

Obviousness Analysis — U.S. Patent No. 6,002,630 under 35 U.S.C. § 103

0. Scope, sourcing, and a disclosure about the "Prior Art section"

The task asks me to use "the results from the Prior Art section of this page." I want to be transparent about what that page actually surfaced:

• The Google Patents page for US6002630 lists only prior-art keywords — voltage, word line, node, output, supply — and does not expose a complete front-page "References Cited" (U.S. Patent Documents) list in the text I retrieved.
• The specification itself cites one concrete prior-art patent: U.S. Pat. No. 5,511,026 ("BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES").
• My retrieval of neighboring art (~1993–1997, Intel/TI/flash-memory gate-supply and charge-pump patents) surfaced a cluster of directly analogous references, several of which I was able to pull text or claims from.

I could not obtain the examiner's complete cited-art list, and I have not fabricated one. The combinations below are grounded in (i) the reference the patent itself cites, (ii) references whose text/claims I actually retrieved, and (iii) the specification's own admissions about the state of the art. Where I am reconstructing rather than quoting, I say so.

Where this conflicts with the previously generated sections: it does not. The earlier "Patent summary" and "Litigation summary" are consistent with what follows. The one useful cross-reference is that Spansion's IPR2014-01118 asserted claims 1–6 and 10–16 as unpatentable and the Board instituted — i.e., a real-world petitioner assembled a colorable § 103 challenge over art of this vintage before the case settled (no final written decision). That is context, not proof.

1. Legal framework and the level of ordinary skill

Governing standard. Under Graham v. John Deere and KSR Int'l v. Teleflex, a claim is obvious if the differences between it and the prior art are such that the subject matter as a whole would have been obvious to a person having ordinary skill at the time of the invention. KSR instructs that a combination of familiar elements according to known methods is obvious when it yields no more than predictable results, and that a "design need or market pressure" to solve a known problem — or the mere existence of a finite number of identified, predictable solutions — can supply the motivation to combine. The specification's own background section supplies much of that motivation here (see §8).

Level of ordinary skill (PHOSITA). A bachelor's degree in electrical engineering (or equivalent) plus roughly 3–5 years of experience designing non-volatile-memory support circuitry — charge pumps, word-line decoders/drivers, and on-chip reference/detector circuits — for low-voltage flash applications. This was a well-populated field by the Nov. 21, 1997 priority date; the '630's own references (Intel, TI, and Macronix flash gate-supply patents from 1993–1996) confirm it.

The invention, distilled. All three independent claims reduce to the same core idea: detect the power-supply voltage level on-chip and vary the amount of charge-pump boosting accordingly, so that a word-line read voltage above the supply range is produced without wasteful over-boost. Claim 1 is the generic integration; claim 10 adds the memory-cell/word-line-driver context; claim 26 adds floating-gate cells, sectioned decoders with a selector, and separate section/word-line address-transition detection.

2. The prior-art references available for combination

3. Claim 1 — the generic claim is obvious

The limited difference over the art. Claim 1's only element not squarely met by the pumped-word-line-supply art (the '026, EP 713165, US 5,663,918) is that the boost amount depends on the sensed supply level — i.e., a supply-responsive variable boost rather than a fixed-boost or reference-tracked boost.

Proposed combination.

1. Primary: U.S. 5,511,026 (or EP 0 713 165) — a flash memory having a voltage-source input, on-chip components (word lines) using a voltage higher than the supply range, and a capacitive charge pump that boosts the supply to that higher on-chip voltage.
2. Secondary: a supply-voltage sensor as in U.S. 5,301,161 / 5,499,453 / 5,594,360 (resistor-divider comparator or equivalent) generating an output indicative of the supply level.
3. Tertiary (the "boost-amount" lever): the known charge-pump control techniques of the Intel pump family (e.g., U.S. 5,553,030 / 5,483,486 / 5,424,586) — switching stages, capacitors, or pump drive in response to a control signal — to set the amount by which the supply is boosted.

Why the POSITA would combine them (motivation, per KSR). The '026 is directed expressly at "low voltage supply memories" and "multi-density" arrays; its pumping capability scales with the supply, and pump output/power depend directly on VDD. A designer told to make the '026 work across the then-emerging 2.7–3.6 V window (the '630's own stated range) has an obvious reason to (a) know the supply level on-chip and (b) reduce delivered boost when the supply is already high — because, as the '630 background concedes, a fixed boost that is adequate at 2.7 V overshoots at 3.6 V and wastes power. Adjusting a pump's output in response to a sensed condition was a known technique applied to a known circuit, with a predictable result (higher boost at low VDD, lower boost at high VDD). That is the KSR paradigm of obviousness.

No unexpected result. The claimed benefit — reduced power and reduced on-chip voltage fluctuation at the high end of the supply range — is the ordinary and predictable consequence of "boost less when the supply is already high." Nothing in the '630 demonstrates a result beyond what the combination would predict.

4. Claim 10 — obvious for the same reasons, plus more structure supplied by the art

Claim 10 adds only the memory context: an array with word lines coupled to cells having a first threshold below the read voltage and a second threshold above it, address inputs, word-line driving circuits, the supply sensor, and an on-chip supply generating the word-line voltage at a node feeding the drivers.

The '026 supplies all of the memory-side structure: a flash array, word lines coupled to cell gates, word-line decoder/driver circuitry, and a read-mode pumped VPXG node powering those drivers. The two-state cell threshold description (erased/programmed relative to the read voltage) is conventional flash-cell description. Adding the supply sensor of §2–3 and making the pumping responsive to it renders claim 10 obvious. Note (as flagged in the earlier summary) that claim 10 does not itself recite the "boost-amount-depends-on-sense-output" limitation — its on-chip supply need only generate the word-line voltage "in response to the output of the sense circuit and to the supply voltage." That is an even lower bar than claim 1, and the combination more easily meets it.

5. Claim 26 — obvious as a combination of three known teachings

Claim 26 is the most heavily loaded and, correspondingly, the most clearly obvious as a combination, because every one of its "extra" limitations maps onto identified art:

(a) Floating-gate cells with two thresholds relative to a read voltage — conventional flash architecture; taught by the '026 (and by the '630's own description as background).

(b) Word-line decoder sections + selector keyed to a portion of the address.

• U.S. 5,511,026, claim 9 expressly recites a word-line predecoder decoding "a portion of a wordline address signal" into a multibit select signal, feeding a plurality of word-line decoder sections, each selecting a word line when selected by its respective select bit. That is claim 26's "plurality of word line decoder sections … identified by a portion of an address" and its "selector … responsive to the portion of the address to connect the node to a selected word line decoder section." The '026 further recognizes the large parasitic capacitance at each section's VPX input and charges it with the standby pump — the very problem the '630 attributes to "section transitions."

(c) Address-transition detection distinguishing section transitions from word-line transitions.

• EP 0 713 165 teaches triggering a word-line boost from an address-transition-detection pulse.
• The '630's own specification states the ATD circuits come from App. Ser. No. 08/751,513 ("or another address transistion circuit as known in the art"). Distinguishing a section-level transition from a within-section word-line transition is nothing more than decoding which address bits changed — a routine refinement of the known ATD function, and squarely the subject of the applicant's own prior application.

(d) Sense circuit + on-chip supply responsive to the sense output, the ATD circuits, and the supply — supplied by the §3 combination.

Motivation to combine (c) with (a)–(b). The '026's own scheme already treats the section-capacitance problem separately (standby pump charging unselected sections so they can help power a newly selected section). A POSITA seeking to keep the pumped node stable across both kinds of address change has a clear reason to differentiate "which kind of change happened" (section vs. word line) so that the correct-sized charge is injected — precisely the ATD-splitting recited in claim 26 and its dependent claims 21–25. The result — more charge for the larger section transition, less for the smaller word-line transition — is a predictable allocation, not an inventive insight.

6. Dependent claims — individually obvious

The dependent claims are conventional refinements that fall to the same references:

• 2, 11, 27 (binary above/below-threshold sense output): the standard output of a divider+comparator (the '630's own FIG. 3/FIG. 5 use R1:R2 = 3:5 and Vref ≈ 2 V) or of U.S. 5,301,161-class supply detectors.
• 3, 12 (plurality of thresholds): multiple comparators / window detectors — an expressly acknowledged, routine extension; the specification itself frames "more levels are sensed" as an optimization, not an invention. Also KSR-favored (finite number of predictable options).
• 4, 5, 13, 14, 27 (first element adds first amount; second adds a greater second amount): two-stage/selectable pumps — met by the Intel charge-pump family and by the '026's dual capabilities (multi-phase read pump vs. standby pump; multiple pump sections).
• 6, 16, 29 (supply ~2.7–3.6 V; on-chip voltage > 3.6 V) and 7, 17, 30 (on-chip voltage ~4.5–5.2 V): numeric ranges; the '026 is directed to low-supply flash gate voltages above VSUPP, and the "at least 4V" gate requirement for a low-supply read is taught by EP 0 713 165. These are design choices, and the ranges are not shown to be critical.
• 8, 18, 31 (idle pump): U.S. 5,511,026, claim 9 — the "low power standby pump" that maintains the pumped node when read mode is inactive is the claimed idle pump.
• 9, 19 (boost on a control-signal transition): EP 0 713 165 (ATD-pulse-triggered boost); and the applicant's own ATD application.
• 20 (decoder sections + selector): U.S. 5,511,026, claim 9.
• 21, 32 (idle pump + section boost pump + word-line boost pump): the '026's standby pump + read pump, differentiated by the two ATD classes of claim 26 — a straightforward mapping.
• 22, 33 (section-transition signal vs. word-line-only transition signal): routine ATD bit-decoding.
• 23, 25 (additional boost pump on section transitions, responsive to the sense output): the '026's recognized need to charge section parasitic capacitance, sized by the same supply-responsive control.

7. What the art does not cleanly show (candid assessment)

To avoid overstating the rejection:

• No single reference retrieved expressly teaches "sensing VDD and scaling the pump's boost magnitude to the sensed VDD." The strongest such teaching I could identify is distributed: supply detection is old (U.S. 5,301,161 et al.); pump-output control by a control signal is old (U.S. 5,553,030 / 5,483,486 family); and the problem is admitted by the '630 itself. A § 103 rejection would therefore rest on combination plus the specification's own admissions and the predictable-result rationale, not on a single anticipatory reference. An examiner or petitioner could also reach claim 1 via "obvious to try" — a finite set of known levers (stages, capacitors, oscillator frequency/drive) applied to a known pump.
• The ATD-based triggering is weak prior art for the patentee to lean on — because the patentee identifies ATD as its own prior application Ser. No. 08/751,513 (filed Nov. 15, 1996), which is at least § 102(a)/(e) art as to the Nov. 21, 1997 filing.

8. Motivation to combine — the specification's own admissions do the heavy lifting

Under KSR, the best evidence of motivation often comes from the reference itself or the patent. Here the '630's Background section is essentially a roadmap:

• It states the low-supply problem (word lines need "4 volts or more" while VDD is 2.7–3.6 V).
• It performs the arithmetic: a fixed boost sized for both extremes needs ~1.5 V and "will cause the on chip voltage to reach approximately 5.1 volts when the supply potential is high."
• It concludes: "when the supply potential is at its high range, the power consumed by the boost circuit is wasted," and that fixed-ratio boosting causes "transient fluctuations" that "decrease the reading speed."

A POSITA reading that framing — and under market pressure to extend flash devices to the new 2.7–3.6 V standard — would be led directly and predictably to sense the supply and reduce boost at the high end. The '630 claims the application of routine supply-sensing to a routine charge pump to achieve an explicitly predicted benefit. That is the definition of an obvious improvement.

9. Secondary considerations — and why they likely do not save the claims

• No unexpected results are demonstrated. The claimed power reduction and reduced transient fluctuation are the direct, expected consequences of reducing boost when VDD is high.
• No evidence of a long-felt, unmet need that others failed to solve is apparent — the field was actively producing pumped word-line supplies with detection/regulation (Intel, TI, Mitsubishi) through 1993–1997.
• Possible commercial-success argument (weak nexus). The assignment history shows a collateral assignment to Nintendo Co., Ltd. (2001) and back to Macronix (2013). A patentee could argue the technology reached Nintendo handheld products, but a mere security-interest record does not establish commercial success of the claimed subject matter, and any such showing would still need a nexus to the supply-responsive-boost limitation rather than to flash-memory read circuits generally. (And it would not revive claims already expired as of 2017.)

10. Bottom line

Confidence. High that the claims are vulnerable to a well-constructed § 103 combination of the vintage art identified above; moderate on any single-reference theory for claim 1, because the "supply-sensed, variable-boost-magnitude" element is best established by combination and by the specification's admissions rather than by one squarely anticipatory reference.

Caveats I will not paper over: I could not retrieve the complete examiner-cited "References Cited" list for US6002630, and I have not verified every teaching of the "similar documents" cluster (US 5,553,030, 5,483,486, 5,301,161, 5,499,453, 5,594,360, 5,663,918) line-by-line against their full texts — those are characterized from the retrieval snippets above. Any formal rejection should be run against the actual patent documents before being relied upon.