US 5619124

I'll search for this specific patent number and check litigation dockets.

Search results first: what I could and could not find

Confirmed record for US 5619124 — I retrieved and rely on the authoritative full text you supplied (fetched from https://patents.google.com/patent/US5619124/en, source timestamp 2026-09-30), cross-checked against Justia (https://patents.justia.com/patent/5619124) and EveryPatent (http://www.everypatent.com/comp/pat5619124.html), both of which returned the same specification text.

CAFC 2026 dockets / litigation: no results found. I ran searches for 5619124 + CAFC, for "5,619,124" + litigation, and for USPTO status. No Court of Appeals for the Federal Circuit docket, district court case, ITC investigation, or PTAB/IPR proceeding involving US 5619124 appeared in any result. This is a negative search result, not a verified absence — I did not directly query the CAFC docket system (CM/ECF) or PACER in this session, so treat "no litigation" as unsupported rather than established.

Important caveat on identifier collision: searching "5619124" returns JP 5619124 B2 (Japanese patent no. 5619124, Canon K.K., "画像処理装置、撮像装置、画像処理プログラムおよび画像処理方法," registered 2014-09-26). That is a different, unrelated patent in a different jurisdiction and is not US 5619124. Similarly, the "Samsung/Netlist IPR, CAFC Nos. 2023-2133, 2024-2304, 2025-1286…" hits that surfaced are completely unrelated patents. Do not conflate them.

US 5619124 — bibliographic summary

Abstract (verbatim substance): "A reference voltage generator for generating a reference voltage having a constant voltage level. The reference voltage generator comprises a high voltage generating circuit for generating a boost voltage boosted over the power voltage level; a clamping circuit for clamping the boost voltage below a constant voltage; a ripple preventing circuit for preventing tipple [ripple] of the boost voltage clamped through the clamping circuit; and a voltage dividing circuit for outputting a reference voltage which is below the power voltage by lowering the boost voltage outputted through the tipple preventing circuit."

Plain-language overview of the independent claims

Claim 1 — the core "four-block" generator. An on-chip reference voltage generator that takes an externally supplied power voltage (VCC) and produces a reference voltage at a constant level. It requires four cooperating elements, recited in means-plus-function style:

1. High voltage generating means — makes a boost voltage above the level of the external power supply.
2. Clamping means — clamps that boost voltage to a constant voltage.
3. Ripple preventing means — suppresses ripple in the clamped boost voltage.
4. Voltage dividing means — divides the filtered boost voltage back down to a reference voltage below the external power voltage level.

Plain-English point: instead of deriving Vref directly from VCC, the invention deliberately pumps VCC up high, pins that high level with a process/temperature-stable clamp, cleans it up, then divides it down. Specification numbers: boost ≈ 10–18 V, Vref ≈ 1–3 V, divider ratio example 9:1, so a 1 V shift in the diode breakdown yields only ~0.1 V shift in Vref.

Claim 9 — the same generator, minus the ripple-prevention element. An integrated circuit (framed as a "semiconductor integrated circuit") with only three elements: high voltage generating means, clamping means, and voltage dividing means that lowers the clamped boost voltage to output a reference voltage below the power voltage level. The ripple preventing circuit of claim 1 is absent, which is the principal structural difference between the two independent claims.

Claim 14 — claim 9 restated in structural ("non-means") language. Same three elements as claim 9 — a "voltage generator," a "clamp," and a "voltage divider" — with the same function and the same result (reference voltage below the power voltage level). The subject matter appears substantively identical to claim 9; the difference lies in the claim-drafting style, presumably to avoid means-plus-function treatment under 35 U.S.C. § 112 ¶ 6.

Dependent claim coverage (all three families parallel each other):

• 2/10/15 — high voltage generating means = charge pumping capacitor driven by a pumping clock.
• 3 — clamping means = a diode, clamped by a reverse breakdown voltage (this is the stability anchor of the whole scheme).
• 4 — ripple preventing means = a capacitor of predetermined capacitance.
• 5/12/17 — clamped boost voltage = 10 to 18 volts.
• 6/13/18 — reference voltage = 1 to 3 volts.
• 7/11/16 — voltage divider = serially connected resistive elements (claims 11 and 16 literally recite "a resistive elements connected in serial").
• 8 — resistive elements = polysilicon resistance layer or impurity-diffusion resistance layer.

Technical and legal observations

• Figures: FIG. 7 is the block diagram (blocks 45, 50, 55, 60); FIG. 8 is the detailed circuit (series charge-pump stages built from NMOS transistors 100–125 and pumping capacitors 70–95, clocks φ and its complement); FIG. 9 is the operational timing diagram showing the boost voltage damping to a constant level after time t1. FIGS. 1–6 are admitted prior art.
• The asserted advantage: the specification argues the diode reverse breakdown voltage in the clamping circuit "is low in deviation of the manufacturing process" and "there is scarcely variation when temperature changes," so dividing it down yields a reference that is far more stable than the resistor/NMOS (FIG. 1), depletion-transistor (FIG. 3), or clamped-PMOS (FIG. 5) prior-art approaches.
• Terminal disclaimer / § 286 practical point: because the patent expired 2014-11-28, any 2026 lawsuit would be limited by 35 U.S.C. § 286 to six years of pre-filing damages (i.e., roughly from April 2020) — entirely after expiration. That makes live 2026 assertion essentially unrecoverable, which is consistent with finding no 2026 CAFC docket for this number.

Explicit uncertainties

1. I have not directly queried USPTO PatentCenter/PAIR, the PTAB API, PACER, or the CAFC CM/ECF docket; my litigation finding is a web-search negative result only.
2. The authoritative text I worked from is the Google Patents rendering, not the USPTO-issued grant document. Google's bibliographic labels (e.g., "Current Assignee (The listed assignees may be inaccurate)") are its own hedges, and its "priority date is an assumption" language should be read as its disclaimer.
3. Your prompt states today is April 26, 2026, while the supplied patent text was fetched at 2026-09-30. I flag this only because it affects any "as of" framing; it does not change the bibliographic data.
4. The specification contains internal inconsistencies worth noting for accuracy: the Summary describes a "damping circuit" where the claims and Detailed Description say "clamping"; reference numeral 45 is used both for the high voltage generating circuit (FIG. 7/8) and for the PMOS transistor in the prior-art FIG. 5; and the two pumping clocks are both printed as "φ and φ" though the text says they are of opposite phase (i.e., φ and φ-bar). These are as-published defects, not my transcription.

I'll search for litigation involving US patent 5619124 across patent litigation databases.

The initial searches returned false positives (US 7,619,912 "the '912 patent" is a different patent, and JP5619124B2 is a Japanese patent). Let me search more precisely for the exact US patent number.

Findings: Litigation involving U.S. Patent No. 5,619,124

No litigation is known involving U.S. Patent No. 5,619,124.

I searched patent-litigation-focused sources and general web indexes for the specific number (in "5,619,124," "5619124," and "US5619124" formats). I found no district court case, ITC investigation, PTAB proceeding, or Federal Circuit appeal in which this patent was asserted, challenged, or otherwise at issue.

Important note on false positives (do not conflate these)

My searches surfaced several hits containing similar-looking identifiers. None of them involve U.S. 5,619,124, and they should not be mistaken for it:

I flag these because the operating rule requires literal interpretation of identifiers — "912," "124," and "561" as shorthand in other cases are not U.S. 5,619,124.

Corroborating circumstantial evidence that no litigation exists

The patent's own record (Google Patents / USPTO) is consistent with a patent that was never litigated:

• Status: Expired – Lifetime; anticipated expiration 2014-11-28 (20 years from the 1994-11-28 filing).
• Citations (prior art cited during prosecution): only 2 references — US 5,436,552 (Mitsubishi) and US 5,497,119 (Intel). These are prosecution citations, not litigation.
• Cited By: 12 later patents (e.g., Atmel, Samsung, Seiko/SII, Infineon). These are patent citations by laterapplicants — not litigation.
• No PTAB/IPR/PGR/re-exam proceeding is listed, and no "Related Litigation" or litigation-event entries appear on the patent record.
• Assignee: Samsung Electronics Co., Ltd.; inventor Young-Ho Lim. It is a portfolio/defensive patent in the analog reference-voltage space.

The only post-issuance events in the file history are routine maintenance-fee payments (4th, 8th, 12th year) — no enforcement activity.

Confidence and limitations

• High confidence that as of today (April 26, 2026) there is no known litigation on U.S. 5,619,124. The number appears only once as an assertion target in zero cases I could locate.
• Caveat: I could not query subscription databases (Lex Machina, Docket Navigator, Westlaw/Lexis) directly, and PACER's full docket text is not fully indexed by public search engines. Unified Patents' litigation caselist portal and the eDockets/PTAB portals are the sources a full litigation check would normally cover; my public-source review produced no match. If you need an exhaustive, defensible "no litigation" opinion, a paid-database search (Lex Machina Patent Litigation + Docket Navigator) on the exact number should be run to confirm.

Bottom line: Based on the sources searched, no plaintiff, defendant, jurisdiction, case number, filing date, or outcome can be provided because no case against this patent is known. If you have a specific suspected case in mind (e.g., a certain NPE, product line, or district), give me that detail and I will run a targeted search to see whether 5,619,124 was in fact the asserted patent.

I'll verify the "no PTAB activity" default against live sources before writing the report.

Let me run a few more targeted checks to confirm the negative and rule out the numeric-collision traps.

Two more checks: one for any post-grant/reexam activity, and one to confirm the Netlist "'912 patent" hits are a different patent (a real collision risk here).

Proceedings overview

Zero AIA trial proceedings on file. The structured ODP block reports no IPR, PGR, or CBM for US 5,619,124, and my own searches surfaced none — the breakdown is therefore 0 active / 0 claims invalidated / 0 claims sustained by the Board / 0 settled / 0 institution-denied. The bottom line for a defendant is not "hardened patent" — it is closer to "academic patent": 5,619,124 issued 1997-04-08 to Samsung (Lim), the Google Patents record shows legal status Expired – Lifetime with an anticipated expiration of 2014-11-28, and the file history shows no challenger ever took a shot at it. Combined with the fact that AIA trials only became available 2012-09-16 — roughly a 26-month window before this patent's term ran out — the absence of PTAB activity is unsurprising rather than exculpatory.

No proceedings to enumerate

I am deliberately not drafting per-proceeding entries, because doing so would require me to invent docket numbers. There is no IPR####-#####, no PGR, and no CBM for this patent in the ODP data or in any public source I could reach. Every apparent "hit" my searches returned was a numeric collision, and a defendant's counsel should be warned about all three:

The Netlist/'912 confusion is the dangerous one: it will surface IPR2022-00639-type dockets, PTAB institutions, and a $303M EDTX verdict, none of which concern 5,619,124. Anyone briefing this patent from raw search results should be corrected (see the Netlist court filings at CourtListener ED TX 2:22-cv-00293).

Strategic summary

Claim status of 5,619,124. All 18 claims — independent claims 1, 9, and 14, and dependents 2-8, 10-13, and 15-18 — are UNTESTED at the PTAB. None are canceled, none are Board-confirmed. "Untested" is not a compliment here; it means no adjudicative body has ever passed on validity. The only validity-relevant paper in the record is the examiner's own work: two cited references, US5436552 (Mitsubishi, clamping circuit for clamping a reference voltage at a predetermined level, 1995-07-25) and US5497119 (Intel, high-precision voltage regulation for programming multilevel flash, 1996-03-05). Both predate the 1994-11-28 filing and are § 102(b)/§ 103 candidates, but both were overcome during prosecution. The cited-by art (e.g., Samsung's own US20100001710A1 / US7990129B2, Atmel's US7808300B2) postdates the patent and is relevant to validity only as evidence of what the field was doing.

Estoppel landscape. § 315(e)(2) estoppel is completely absent — it attaches only to petitioners who obtain a final written decision, and there has never been a petitioner. This cuts both ways. In a defendant's favor: no art is foreclosed, no ground was "reasonably could have raised" away, and a defendant is free to run the full panoply of § 102/§ 103 art, including the Mitsubishi and Intel references, before any forum. Against the defendant: it also means no one has ever done the work, so you cannot lean on a prior tribunal's findings, and there is no prior claim-construction record to borrow.

Pattern signals. No repeat petitioner (none exist). No patent-owner appeal history at the Federal Circuit (see the cited-by/family records; the family is US + JP + KR only, with the KR counterpart KR0153542B1 and JP JPH07194099A). No defensive aggregator — Unified Patents and its peers target actively asserted, unexpired patents, and this one was never asserted. Samsung's maintenance-fee record in the ODP block shows payments at years 4 (2000-09-25), 8 (2004-09-08), and 12 (2008-09-22), with no later fee event and Google's "Expired – Lifetime" label keyed to the 2014-11-28 twenty-year date. Caveat, stated plainly: the ODP legal-events feed provided to me appears truncated, and I cannot confirm from it whether the ~15.5-year maintenance fee was paid or whether the patent instead lapsed earlier. A defendant relying on expiration should pull the fee history directly from USPTO Patent Center rather than trusting either the truncated feed or the "anticipated expiration" estimate.

Recommended next steps

If you are a defendant and the patent has claims invalidated: it does not — no claim of 5,619,124 has been canceled by the Board, so there is no FWD to link or quote. The correct framing is not "the troll has no case because claims died," but "there is no PTAB record at all."

If active proceedings are pending: none are. No institution-deadline, no oral-hearing date, and no statutory one-year FWD clock is running for this patent. Nothing is coming; do not plan a defense around an imminent Board ruling.

The real defense here is the calendar, not the Board. Three points worth verifying in this order:

1. Expiration / unenforceability of the term. Confirm via USPTO Patent Center whether the patent expired 2014-11-28 or lapsed earlier for non-payment of the ~15.5-year maintenance fee. Either way, look hard at § 286: damages are capped at six years before the complaint, and with no post-2014-11-28 infringement to capture, a suit asserting 5,619,124 today would appear to have no recoverable damages window. That is a Rule 12 / summary-judgment argument, and far cheaper than an IPR.
2. Priority scope. The Korean priority is KR1019930025325A (1993-11-26), i.e. pre-URAA. If a plaintiff somehow stakes a claim to any post-expiration term-adjustment or continuation coverage, the § 154(b) and pre-URAA term math (17-from-issue vs. 20-from-filing, the greater of) is the fight.
3. If a live campaign somehow emerges (e.g., a portfolio plaintiff asserting it against legacy hardware), the absence of any AIA trial is a genuine signal — well-asserted patents attract IPRs. You would be the first mover, with US5436552 and US5497119 as the natural starting art for a § 103 combination against independent claim 1, whose "high voltage generating means + clamping means + ripple preventing means + voltage dividing means" recitation is written in classic pre-Williamson means-plus-function form and is vulnerable on both § 112(b) indefiniteness and § 103 grounds. Claim 5's "10 to 18 volts" and claim 6's "1 to 3 volts" ranges are quoted verbatim from the specification and invite written-description/range-obviousness attacks.

Sources checked (all negative for PTAB proceedings on this patent): the Google Patents record for US5619124A, the cited-by and family tables therein, and targeted searches against USPTO PTAB materials and CourtListener. For a definitive negative, the authoritative check is the Board's own docket at USPTO PTAB E2E / PTACTS and the published decisions library at https://www.uspto.gov/patents/ptab/decisions — I found no entry for 5,619,124 in any indexed source, but I flag that I could not open the PTAB E2E portal directly in this session.

I'll verify the assignment record and check for any litigation or ownership activity before finalizing.

Assignment & Ownership Analysis — US 5,619,124

Patent: US 5,619,124 — Reference voltage generator in a semiconductor integrated device
Application: US 08/348,183 · Filed 1994-11-28 · Issued 1997-04-08 · Priority 1993-11-26 (KR 1019930025325)
Status: Expired — Lifetime (anticipated expiration 2014-11-28; last maintenance fee paid 2008, year 12)

Inventors

Patterns: No unusual inventor-side signals. A single inventor named on the face of the patent is routine for Samsung's Korean semiconductor R&D organization of this era, and the Korean priority application (KR 1019930025325, filed 1993-11-26) shows the invention was captured inside Samsung's domestic filing pipeline before the US case. There is no evidence of inventors departing the original assignee — the patent was never re-assigned away from Samsung, so the "inventors leave, portfolio fire-sale" precursor pattern does not apply here.

Original assignee

Samsung Electronics Co., Ltd. (Suwon, Republic of Korea) — original and only assignee on the issued patent.

• Line of business: Semiconductor memory and consumer/industrial electronics; at the 1993–1997 timeframe, a leading DRAM/SRAM/ASIC manufacturer. The claimed subject matter (charge-pump boost voltage → diode clamping → RC ripple filtering → resistive divider) is the internal high-voltage/reference-generation circuitry used in exactly that product line (low-supply-voltage DRAM and integrated circuits), consistent with the stated motivation in the specification ("especially required in the semiconductor integrated devices which operate using a low power voltage").
• Product embodying the claims: Yes — the assignee is a volume chip manufacturer; the reference voltage generator is internal support circuitry, not a standalone product.
• Current status: Operating. Publicly traded (KRX: 005930); the largest memory semiconductor manufacturer globally. No bankruptcy, no acquisition, no dissolution. Ownership never left Samsung.

Assignment timeline

The Assignment Center record for this patent contains exactly one recorded assignment — the original inventor-to-employer transfer. There are no post-issuance transfers of any kind (no security interests, no mergers, no name changes, no LLC transfers).

• 1995-01-23 (executed) / recorded 1995-01-27 — Reel 007337 / 0516
  • Conveyance: Assignment
  • Assignor: LIM, Young-Ho (individual inventor)
  • Assignee: SAMSUNG ELECTRONICS CO., LTD.
  • Correspondent: Not surfaced in the publicly indexed record. The Google Patents legal-event entry gives the reel/frame and the ASSIGNMENT OF ASSIGNORS INTEREST conveyance but does not expose the recording attorney/firm; a search of the public assignment index returned no additional correspondent data. This is a gap, not a finding — do not read an unnamed correspondent as an anonymity tell. (An unnamed correspondent is trivially explained here: the counterparty is a publicly traded operating company, not a shell.)
  • Context: Initial inventor-to-employer assignment of the US application, tied to the 1993-11-26 Korean priority filing — a standard employment/priority-capture transfer, with Samsung's in-house/outside Korean prosecution counsel handling the US formalities.

Subsequent records of ownership activity (non-assignment events per Google Patents legal events):

The 1998 "ENTITY STATUS OF PATENT OWNER: LARGE ENTITY" entry confirms the fee-paying owner remained a large corporate entity throughout — consistent with Samsung retaining the patent, not a small entity or an LLC assignee.

Finding: The chain terminates at the original assignee. No assignment activity after 1995-01-27. Samsung paid all three maintenance fees through year 12 and let the patent expire on schedule in 2014. There is no NPE chain to reconstruct here.

Timeline diagram

timeline
    title Ownership of US 5619124
    1993 : KR priority application filed
    1994 : US application filed by Samsung
    1995 : Inventor assigns to Samsung Electronics
    1997 : Patent issued
    2000 : Maintenance fee paid for year 4
    2004 : Maintenance fee paid for year 8
    2008 : Maintenance fee paid for year 12
    2014 : Patent expires - Lifetime

NPE / troll-pattern signals

Verdict

Insufficient data (no records, or only the original assignment).

The Assignment Center record for US 5,619,124 contains only the original inventor-to-employer assignment executed 1995-01-23 and recorded 1995-01-27 at reel 007337/0516, assigning Young-Ho Lim's rights to Samsung Electronics Co., Ltd.; there are no post-issuance transfers, security interests, mergers, or name changes of any kind. Because the chain never leaves the original operating-company assignee — which paid maintenance fees through 2008 (year 12) and let the patent expire in 2014 — none of the eight NPE signals is present, and there is no shell LLC, recurring correspondent, or assertion vehicle to analyze. In substance this is a clean, never-transferred, operating-company-owned patent; the "insufficient data" verdict reflects the absence of any transfer chain to evaluate, not a lack of clarity about ownership.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 5619124) — and the Google Patents legal-events tab: https://patents.google.com/patent/US5619124/en

Caveat on the correspondent field: the recording attorney/firm of record for reel 007337/0516 was not recoverable from the indexed public sources used here (Google Patents legal events, an Assignment Center index query). If you need that field for a correspondent-clustering study, it must be pulled from the faces of the assignment documents at reel 007337, frame 0516 directly (USPTO Patent Assignment Search document viewer / ODP), which I could not open from this environment.

I'll verify the patent record on USPTO and research each cited reference.

Let me pull the USPTO record and check for any additional references cited during prosecution.

Prior Art Analysis — US 5619124

Note on identifier discipline: I resolved every identifier literally. The number "5619124" also returns JP 特許第5619124号 B2 (Canon K.K., 画像処理装置、撮像装置、画像処理プログラムおよび画像処理方法; app. JP 2012-277805, filed 2012-12-20, registered 2014-09-26, issued 2014-11-05, 16 claims). Searches for the bare string "5619124" surfaced that document repeatedly. It is not US 5619124 and is excluded from this analysis.

1. Scope, sources, and a hard limitation

Therefore: the citation list below is the examiner-cited art as reported by Google Patents ("Patent Citations (2)"). If the official file history contains additional U.S. or foreign references or non-patent literature that Google did not index, I have not seen them. I state that explicitly rather than implying completeness.

2. The citations for 5619124

US 5619124 lists exactly two cited patent documents, both marked as cited by the examiner:

1. US 5,436,552 A — Mitsubishi Denki Kabushiki Kaisha
2. US 5,497,119 A — Intel Corporation

Everything else on the Google page under "Cited By" (e.g., US7808300B2, US7990129B2, US9923458B2, US10985653B1, CN109802681A/B) is forward art — publications that cite 5619124, i.e., later disclosures. Forward citations cannot be prior art to 5619124 and are excluded.

The family members KR0153542B1, KR950015750A, and JPH07194099A are the same invention in other jurisdictions (the KR application 1019930025325A is the priority application itself). They are not "another's" art under §102 and are excluded.

3. Reference 1 — US 5,436,552 A

Brief description. A clamping circuit built from a constant-current circuit (constant-current source plus current-mirror), a trimmable resistance that receives the constant current, and a clamping MOS transistor whose gate receives the voltage developed across that trimmable resistance and which regulates current through a clamping node. The stated benefits are a fast current-voltage characteristic and the ability to set an arbitrary clamping potential. Critically, the reference is set in a DRAM context and its FIG. 9 shows a memory with a VBB generating circuit 116 (substrate bias) and a Vpp generating circuit 118 that "receives the power supply voltage Vcc … to generate the boost signal Vpp" — a boost signal higher than the power supply voltage Vcc — delivered to a word driver.

§102 analysis against 5619124. This is the closest art for one element only.

• Claim 3 (clamping means = a diode, clamped by a reverse breakdown voltage): US 5,436,552's clamp is a MOS transistor clamp with a trimmable resistance — not a junction diode and not a reverse-breakdown clamp. It does not anticipate claim 3.
• Claim 1 / claim 9 / claim 14 (clamping means generally): US 5,436,552 discloses clamping a voltage in a semiconductor device to a constant voltage, and separately (FIG. 9) generating a boost voltage Vpp above Vcc in a DRAM. But it does not clamp the boost voltage, does not disclose a ripple-preventing means, and does not disclose a voltage divider that lowers the clamped boost back below Vcc to produce Vref. No anticipation of claims 1, 9, or 14.
• Date status: its US filing date (1993-09-21) precedes the 5619124 priority date (1993-11-26), so it is a proper pre-AIA §102(e) reference (and would be §102(a)(2) art under the AIA, though the AIA does not govern this 1994-filed patent). The reference is legitimately "prior art"; the problem is scope, not date.

Honest conclusion: US 5,436,552 does not anticipate any claim of US 5619124. Its value is as a §103 reference teaching that (a) constant-level clamping of an on-chip voltage and (b) on-chip generation of a boost voltage above Vcc were each known in DRAM circuitry by the 1993 priority date.

4. Reference 2 — US 5,497,119 A

Brief description. A programming-voltage regulator with a sample-and-hold circuit (a capacitor that holds a reference voltage, plus a switch and a precharge circuit), and a regulator circuit containing an operational amplifier whose positive input receives the held reference voltage and whose negative input is fed back from a programmable resistive divider. The input circuit is expressly "a first resistor coupled to the input voltage; a second resistor coupled in series with the first resistor to system ground, wherein the reference voltage is supplied at a node between the first and second resistors," and the divider is "a plurality of resistors coupled in series between the output of the operational amplifier and system ground" with a selector circuit choosing a tap point.

§102 analysis against 5619124.

• Claims 7/8 (voltage divider = two serially connected resistive elements; polysilicon or impurity-diffusion resistance layer): US 5,497,119 plainly discloses two serially connected resistors generating a divided reference voltage. But claims 7 and 8 depend from claim 1; a dependent claim is anticipated only if the reference discloses every limitation of the independent claim plus the added one. Because claim 1 is not anticipated (see below), claims 7 and 8 are not anticipated either.
• Claims 11 and 16 ("a resistive elements connected in serial"): same reasoning — these depend from claims 9 and 14 (via 9→11 and 14→16). No anticipation unless the parent is anticipated.
• Claim 4 (ripple preventing means = capacitor): the sample-and-hold capacitor C1 holds a reference voltage, but its disclosed function is sampling/holding, not suppressing ripple from a pumping clock. This is not the claimed element. No anticipation.
• Claims 1, 9, 14: US 5,497,119 contains no charge pump or boost stage producing a voltage above the power supply, and no clamping stage clamping such a boost to a constant voltage. Both critical elements are absent. No anticipation of any independent claim.

A date problem worth flagging. US 5,497,119's only possible §102 date is its US filing date of 1994-06-01 (it issued 1996-03-05, after the 1994-11-28 filing, so §102(a)/(b) are unavailable, and WO95/33232 published 1995-12-07, also after). Under pre-AIA §102(e), a US patent is prior art as of the US filing date of its application — not its foreign priority date (In re Hilmer). Here 1994-06-01 is after the 5619124 priority date of 1993-11-26, so the applicant could have antedated it by relying on the Korean priority under 35 U.S.C. §119. On that reading US 5,497,119 is arguably not applicable prior art against 5619124 at all. I could not verify from the official file history whether an antedating statement was made or whether the examiner relied on this reference in a rejection. I flag this as an unresolved legal question rather than asserting a conclusion.

5. Admitted prior art (no document number available)

US 5619124's own specification admits three "conventional art" arrangements, labeled FIGS. 1–2, 3–4, and 5–6:

1. FIGS. 1–2: a resistance 5 from VCC to node N1 and a diode-connected NMOS 10 from N1 to VSS — the classic resistor/MOS Vref generator the invention criticizes for tracking VCC.
2. FIGS. 3–4: two N-channel depletion transistors 15, 20 with gates tied to VSS — criticized for temperature/process sensitivity.
3. FIGS. 5–6: resistors 25, 30, NMOS 35, 40, and PMOS 45 forming a clamped reference — criticized because deviation "results from the variations of threshold voltages and resistance elements."

These are admissions, usable as prior art under §102(a)/(b) if they were publicly known before the critical date — but there is no citable document for them, and their status as public knowledge more than one year before filing is not established on this record. Treat them as an inventor admission of the general state of the art, not as §102 references.

6. Claim-by-claim §102 table

Bottom line: on the record available to me, neither examiner-cited reference anticipates any of claims 1–18 of US 5619124 under 35 U.S.C. §102. Each maps to at most one of the four recited blocks. The strongest available theory is not anticipation but §103: US 5,436,552 (constant-level on-chip clamping; DRAM boost-voltage generator in its FIG. 9) in view of US 5,497,119 (serially connected resistive divider producing a reference voltage) in further view of the admitted charge-pump art, directed at claims 9 and 14. Even that combination does not reach claim 1's ripple preventing means or claim 3's diode/reverse-breakdown limitation, which no cited reference supplies.

7. Explicit uncertainties

1. Official USPTO citations unverified. I did not reach PatentCenter/PAIR. The "two cited references" list comes from Google Patents' rendering. Additional references of record (especially any non-U.S. patent documents or non-patent literature, and any art cited in the JP/KR counterparts) may exist and would change the analysis.
2. No prosecution history. I have no record of which claims were rejected, on what statutory basis, or whether the cited art was applied in a §102 or §103 rejection. Everything in Sections 3–6 is my own mapping of reference disclosure to issued claim language.
3. The US 5,497,119 date question in Section 4 is a genuine legal issue, not a settled point. I have stated the Hilmer / §119 analysis as I understand it and flagged that I could not confirm the file history.
4. Inventor of US 5,436,552 not confirmed in my sources; I have therefore not named one rather than guess. The assignee (Mitsubishi Denki K.K.) and all dates are confirmed.
5. The prior summary's date inconsistency — that section notes the prompt states April 26, 2026 while the supplied patent text was fetched 2026-09-30 — persists and does not affect the bibliographic or prior-art data above.

Obviousness Analysis — U.S. Patent No. 5,619,124 under 35 U.S.C. § 103

0. Scope, sources, and flagged contradictions

This analysis builds on the prior two sections (bibliographic summary; claim overview; litigation negative result) and does not repeat them. Per instruction, I anchor the art on the Prior Art section of the US5619124 Google Patents page as supplied:

• Prior-art keywords (the page's own indexing): voltage, boost, reference voltage, integrated circuit, level.
• Patent Citations (2) — US 5,436,552 (Mitsubishi Denki) and US 5,497,119 (Intel Corp.).
• Similar Documents (23 listed) — usable only after a date screen; most are later than the critical date and are therefore not § 102 art (see § 2.3).
• Cited By (12) — forward citations. These are not prior art and I do not use them (same caution as the earlier section's false-positive warning: Google's layout puts Cited By and Prior Art on the same page).

Contradictions flagged, not silently resolved:

1. Your current task states today is April 26, 2026; the supplied patent text was fetched 2026-09-30. This does not affect the art dates below, but any "as of" framing is inconsistent across the record.
2. The earlier section noted the specification's internal defects ("damping" vs. "clamping"; numeral 45 used twice; "φ and φ" for two opposite-phase clocks). Those are as-published and are relevant here because claim 1's preamble and the Summary use inconsistent wording for the same block.
3. Preamble content differs: the task now says the patent is "US patent 5619124" and the prior sections used "5,619,124." I read these as the same literal document (US5619124A / App. 08/348,183). I flag it only because the operating rule requires literal reading.

1. Governing law and the correct § 103 framework

• The application was filed 1994-11-28 with a 1993-11-26 KR priority. It is therefore governed by pre-AIA § 103 (AIA § 3(n)(1) applies only to applications filed on or after 2013-03-16). That matters for § 102(e) and for the Hilmer doctrine below.
• Framework: Graham v. John Deere Co., 383 U.S. 1 (1966) (scope/content of art; differences; PHOSITA level; secondary considerations), applied per KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) (predictable solutions, known-technique improvement, "obvious to try," market/design demand rather than an explicit TSM).
• Because the art is used to attack means-plus-function elements (claim 1's "high voltage generating means," "clamping means," "ripple preventing means," "voltage dividing means"), the § 112 ¶ 6 structure is what the specification discloses: a charge-pumping circuit (col.-level description of blocks 130/140/145), a junction diode, a capacitor of predetermined capacitance, and polysilicon/diffused resistors R1/R2. For § 103 the art need only supply structure performing the recited function; I note this because it materially narrows the gap the art must fill (MPEP 2181).

2. Art qualification and the priority-date analysis (this is where this case is decided)

2.1 US 5,436,552 (Tsugita; Mitsubishi Denki) — robustly prior art

Its US filing date (1993-09-21) precedes both the 1993-11-26 KR priority date and the 1994-11-28 US filing date. No § 119/Hilmer complication. It is available under pre-AIA § 102(e) as of 1993-09-21, and its JP priority date is available for the foreign publication. The JPH06104672A record returned in search confirms the 08/123,964 → US5436552A link.

2.2 US 5,497,119 (Intel) — temporally marginal; flag this

Its filing/priority (mid-1994) is after the '124 patent's 1993-11-26 priority date but before its 1994-11-28 US filing date. Under pre-AIA § 102(e) as applied with Hilmer v. Riesenfeld, a foreign (§ 119) priority date cannot be used to antedate a § 102(e) reference. So the '124 patentee could only remove '119 by proving prior US invention (conception + diligence/RTP) before mid-1994 — plausible given the KR filing, but an evidentiary question, not a legal certainty. Practical consequence: build the § 103 case so it does not stand or fall on '119 alone.

2.3 "Similar Documents" — do not use indiscriminately

Many of the page's Similar Documents postdate the critical date and are not § 102 art (e.g., US5898335A 1999; US6888399B2 2005; CA2216891C 2001; KR100285184B1 2001; US6559709B2 2003; US7102423B2 2006; US7728652B2 2010). Candidates appearing before the critical date, which I did not verify in this session, include US4115710A (1978, substrate bias for MOS IC), US4275437A (1981, semiconductor circuit for voltage conversion), EP0068611B1 (1986, substrate-bias voltage generator), JPS61222318A (1986), JPS63308794A (1988), KR900005792B1 (1990), and US5262989A (1993-11-16 — only ten days before the KR date). I use these only as evidence that on-chip high-voltage generation/clamping was a crowded, mature field by 1993, which supports the KSR "finite number of predictable solutions" rationale. Anyone relying on them should verify their § 102 dates first.

3. Level of ordinary skill (PHOSITA), as of November 1993

A person with a B.S.E.E. (or M.S.) and roughly 3–5 years in analog/mixed-signal MOS integrated-circuit design, specifically memory periphery: internal voltage generators (Vpp/VBB), charge pumps, and reference/clamp circuits, with working familiarity with internal voltage clamping against supply, temperature, and process variation. The '124 patent's own admitted prior art (FIGS. 1, 3, 5 and their descriptions) establishes that this artisan knew the three conventional reference approaches the patent criticizes — a resistor + diode-connected NMOS (FIG. 1), N-channel depletion devices (FIG. 3), and a resistor divider with a clamped PMOS (FIG. 5). Those six figures are applicant admissions and are § 103 art in their own right (MPEP 2129).

Note on the Dickson charge pump: the page's prior-art list does not include it, but the art's state is uncontested — J. F. Dickson, "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique," IEEE J. Solid-State Circuits, vol. SC-11, no. 3, pp. 374–378 (June 1976) (one search result mis-cited it as "vol. 1, no. 1"; the SC-11 citation is the consistent one). The '124 patent's own classification, H02M3/073 (Schenkel-type charge pumps), presupposes this. Also directly on point and inside the record: the '552 patent itself states that the boosted word-line voltage "is generated on-chip from the power supply voltage Vcc by using a boosting circuit using a capacitive coupling by bootstrap capacitance, a boosting circuit using a charge pump operation, or the like."

4. Element-by-element mapping

4.1 Independent claim 1

4.2 Independent claims 9 and 14

Same as above minus the ripple-preventing means. Claims 9 and 14 are therefore broader than claim 1 and, as the earlier section observed, substantively identical to each other (a drafting-style difference for § 112 ¶ 6). Claims 9 and 14 are the easiest targets.

4.3 Dependents

5. Grounds of rejection

Ground 1 — Claims 1–18 obvious over US 5,436,552 in view of US 5,497,119

• Same field of endeavor, same problem. Both are semiconductor-memory internal-voltage/reference circuits. The '124 preamble states the goal: a reference "so that an interior of a chip is not influenced according to the variation of an external power voltage." The '119 patent states as an object "voltage regulation circuitry that supplies a high precision output voltage that is independent of variations of an external input power supply." The '552 patent is the DRAM-side counterpart: an internally generated, above-Vcc rail that must be held at a predetermined level.
• Rationale for the combination (known-technique / predictable-result, KSR). The '552 patent supplies the two hard elements: an on-chip pumped high voltage and a clamp that pins it at a predetermined level. The reference-stabilization problem for a divider is precisely that its output tracks its input; the ordinary artisan, given a stable, clamped, process-insensitive rail, would use it as the input to the known series-resistor divider of '119 (or of the '124 patent's own FIG. 5) in order to obtain Vref that does not track Vcc. This is the paradigm of using a known technique (resistive division of a regulated node) to improve a similar device in the same way, with a predictable result.
• Reasonable expectation of success. Purely arithmetic: a fixed ratio applied to a clamped voltage yields a proportional, stable output. The patentee's own specification supplies the proof and, in doing so, undercuts nonobviousness: a 1 V change in diode breakdown with a 9:1 divider "the reference voltage Vref is changed by 0.1 volt." Attenuation of an input deviation by the divider ratio is a predictable result, not an unexpected one.

Ground 2 — Claims 1–18 obvious over US 5,436,552 in view of the applicant's admitted prior art (FIGS. 1, 3 and 5 and their descriptions)

This ground does not depend on US 5,497,119 and therefore survives the Hilmer/§ 102(e) problem in § 2.2 above. The '124 patent's own FIG. 5 showing resistors 25 and 30 dividing VCC to nodes N3/N4, with clamping transistors — combined with '552's pumped-and-clamped Vpp as the divider input, and with the '124 patent's admitted recognition that reference accuracy is degraded by "variations of the power voltage externally inputted… and temperature deviation" — states the entire case without Intel.

Ground 3 — Claims 2, 10, 15 obvious over US 5,436,552 (alone or with Dickson 1976)

The '552 patent already discloses, in its own words, on-chip charge-pump boosting of Vcc to Vpp. No secondary reference is required for the charge-pump limitation; Dickson is offered only for the two-clock/coupling-capacitor detail.

Ground 4 — Claims 5/6/12/13/17/18 obvious as range optimization

10–18 V and 1–3 V are ranges the artisan would arrive at by (i) selecting the pumped-clamp level already used in memory devices of the era and (ii) selecting a divider ratio giving a logic-level reference. In re Aller/In re Boesch; MPEP 2144.05. The '124 specification does not allege any criticality of these endpoints.

6. The strongest nonobviousness arguments, and the answers

1. "The '119 patent teaches deriving the reference from the external input voltage, not from an internally pumped voltage." This is the best argument, and it has real support: '119 claim 3 recites "a first resistor coupled to the input voltage; a second resistor coupled in series… reference voltage supplied at a node between the first and second resistors," and claim 7 says "the input voltage is equivalent to the supply voltage." Answer: an express teaching of sampling/regulating a raw supply reference is directed to that circuit's problem (multilevel flash programming precision), and is not a teaching away from using a regulated internal node; '119's stated object of independence from external-input variation points the same direction as the '124 preamble. Under KSR and In re Merck, the motivation may come from the knowledge and common sense of the artisan, not from the references alone. This argument is strongest for claims that require '119 for the divider; it collapses for Ground 2 (admitted FIG. 5) and for Ground 3 ('552 alone on the pump).
2. "The art does not suggest dividing a 10–18 V pumped rail down to 1–3 V." Answer: the '124 claim 1 merely requires "below said power voltage level"; scale-down division of an available internal rail is routine (resistors, and in '119 the amplifier-fed programmable divider of claim 8). The patent's own arithmetic shows the result is the expected one, which cuts against this argument.
3. "Unexpected stability of the junction-diode breakdown voltage." This is the patent's only substantive technical argument. Answer: it is a property of the reference element, not of the claimed combination, and the specification itself characterizes the benefit as arithmetic attenuation. That is the antithesis of an unexpected result.
4. Secondary considerations: nothing in the record — no unexpected results evidence, no commercial-success nexus, no copying, no long-felt need evidenced in the specification beyond the generic statement of the problem. Note the earlier section's finding of only routine maintenance-fee events post-grant and no enforcement activity.

7. Honest limits of this analysis

• I did not retrieve the full text or claims of US 5,436,552 in this session. The mapping of element (b) rests on its title, its VBB/Vpp DRAM context, and the Google Patents snippet quoted above; the family documents that did return (US 5,500,617; JP 2814039 B2; JP 2000-357949 A) are different clamping circuits by the same or another inventor and are not substitutes for '552's own disclosure. A definitive § 103 opinion requires the printed '552 text and its drawing.
• I did not retrieve the file wrapper / PatentCenter prosecution history. I therefore cannot state which claims the examiner rejected, whether US 5,436,552 was applied under § 102(e) or § 103, or whether US 5,497,119 was cited as § 102(e) art (which would confirm the Hilmer analysis in § 2.2). I also cannot confirm that the KR certified copy was filed to perfect the 1993-11-26 priority.
• US 5,497,119's exact § 102 date is unresolved on the record I have: the page shows "prior art date 1994-06-01," while the CN family data showed a US application 08/252,585 with priority 1994-05-31 (i.e., 1994-06-01) and the Unified Patents page showed "1994-05-31." Both are after the KR date, so the Hilmer point stands either way.
• The "Similar Documents" dates in § 2.3 are from the page's labels only, unverified; do not cite them as prior art without checking.
• Do not reuse the page's Cited By list as prior art (infringement/obviousness confusion), and do not confuse JP 5619124 B2 (Canon) with US 5619124 — carried forward from the earlier section.

8. Bottom line

There is a strong prima facie § 103 case against all 18 claims, and the case is strongest where the claimed subject matter is broadest. Claims 9 and 14 (three elements, ripple-prevention omitted, mutually duplicative in substance) are very likely obvious over US 5,436,552 in view of either US 5,497,119 or the applicant's own admitted prior art of FIGS. 1/3/5. Claim 1 adds only the ripple-preventing capacitor, which US 5,497,119's capacitor C1 supplies. Claims 2–8 and 10–18 fall to the same combination plus routine design choices (diode clamp, on-chip polysilicon/diffused resistors) and obvious range selection. The single defensible obstacle for a defendant is the § 102(e)/Hilmer qualification of US 5,497,119 — which is why the record should be built around US 5,436,552 plus the specification's own admissions, an approach that requires no Intel reference at all.