US 9477219

I'll search for authoritative information on this patent number, including any 2026 litigation activity.

US 9,477,219 B2 — Search Results and Summary

1. Docket / litigation search result (most important finding)

I found no 2026 CAFC docket activity, no district court litigation, and no PTAB (IPR/PGR/reexam) proceeding involving US 9,477,219. My searches surfaced only patent-profile pages, the patent document itself, and unrelated 2025–2026 semiconductor litigation. Specifically:

• The active 2025–2026 semiconductor fabrication litigation I retrieved (IPValue subsidiaries Longitude Licensing and Marlin Semiconductor v. TSMC, Apple, Broadcom, Qualcomm, Lenovo, OnePlus; E.D. Tex. 2:25-cv-00171 and W.D. Tex. 1:25-cv-00215; ITC 337-TA-3809) asserts U.S. 7,745,847; 9,093,473; 9,147,747; 9,184,292; and 9,953,880 — all former UMC patents. None of these is 9,477,219, and 9,477,219 is a TSMC patent, not a UMC one, so I did not attribute those results to it.
• The PTAB documents retrieved (e.g., IPR2025-00682/00683/00828–00832 against '686, '425, '227, '764, '180, '076, '779 — all TSMC-vs-UMC disputes) also do not include 9,477,219. Note the near-miss trap: several results reference patents numbered 9,477,2xx–adjacent strings; I excluded them per your instruction not to return similar numbers.

Caveat on confidence: I could not directly query USPTO Patent Center / PTAB API or the Federal Circuit's 2026 docket feed as primary sources; these conclusions rest on web-indexed results, which are strong for absence of high-profile litigation but are not a certified "no proceedings exist" finding. Treat the negative result as no evidence found, not as a verified negative.

2. Bibliographic summary (from the authoritative patent text)

Abstract (as issued): A method of semiconductor fabrication includes providing a model for a device parameter of a wafer as a function of first and second process parameters, the first and second process parameters corresponding to different wafer characteristics, respectively; deriving target values of the first and second process parameters based on a specified target value of the device parameter; performing a first fabrication process in response to the target value of the first process parameter; measuring an actual value of the first process parameter thereafter; updating the model using the actual value of the first process parameter; deriving a revised target value of the second process parameter using the updated model; and performing a second fabrication process in response to the revised target value of the second process parameter.

3. Plain-language overview of the three independent claims

Claim 1 (method). Build a model that predicts an electrical wafer device parameter (e.g., saturation drain current I_dsat) from two physical process parameters (e.g., active-region critical dimension OD_CD and shallow-trench-isolation step height STI_SH). From a target device value, work backwards to target values for both process parameters. Run the first process step using the first parameter's target. Then measure what the first step actually produced, feed that measured actual value back into the model, and recompute a new target for the second process parameter before running the second step — on the same wafer. Afterwards measure the actual device parameter. The update-and-recompute must be done so the final measured device parameter substantially hits the original target.

Claim 9 (method of fabricating a semiconductor device). A three-parameter version framed in terms of tools rather than a model: determine a target for parameter 1 from a target for parameter 2; run a first fabrication tool on a wafer at that target; measure the actual parameter 1; then determine a target for parameter 3 based on the target of parameter 2 and the measured actual of parameter 1; run a second tool on the same wafer at that revised target; then measure the actual parameter 2. Parameter 2 is defined functionally as a function of parameters 1 and 3; parameters 1 and 3 are physical wafer characteristics and parameter 2 is an electrical characteristic.

Claim 14 (system). An apparatus claim implementing the same idea: a modeling module that holds the device-parameter model (electrical device parameter as a function of physical process parameters) and derives target values from a device-parameter target; a first process tool driven by the first parameter's target; a metrology tool that measures the actual first parameter and feeds it back to the modeling module; a second process tool driven by a revised second-parameter target that the modeling module recomputed from that measurement; and a wafer acceptance test (WAT) tool that measures the actual device parameter after both process steps.

4. Practical takeaways

• Narrowness: the independent claims are tied to a feedback-into-the-next-step control loop on the same wafer, with the measurement of the first process parameter (not merely the device parameter) driving recomputation of the second target. The specification's "mini-loop"/"full-loop" distinction and the optional APC optimizer modules (110/111/112) are described in the description but are only partially captured in the independent claims (optimizer features appear in dependent claims 7, 8, 19, 20).
• File-history note for validity work: the issued claims recite "obtained as a result of the … process" language for the measured actual values and "the same wafer" limitations — these appear to be amendments made during prosecution (allowance notice 2016-05-19, grant 2016-10-25), so any invalidity/scope analysis should pull the file wrapper from USPTO Patent Center for the pre-AIA §102/§103 record.
• Opposability today: the patent lapsed for non-payment of maintenance fees effective 2024-10-25, so it is unavailable for assertion and cannot be the subject of a live 2026 IPR (IPR requires an unexpired patent). That said, my "no live proceedings" conclusion is based on indexed sources only.

Uncertainty flags: (a) I did not open USPTO Patent Center or the Federal Circuit's docket system directly, so the absence of 2026 CAFC activity is an inference from search results, not a certified docket check; (b) the Google Patents text renders the general model equation oddly ("DP = a₁P + a₂P₂ + a₃P₃ + … + a₁P_n + b"), which I read as an OCR/formatting artifact of the intended DP = a₁P₁ + a₂P₂ + … + a_n P_n + b; claim 2 confirms the two-variable form DP = a₁P₁ + a₂P₂ + b; (c) the drawing description in the fetched text inconsistently labels FIG. 2 as both "part of a semiconductor fabrication process flow" and a "flowchart," with the reference to "the embodiment illustrated in FIG. 2" where FIG. 1 was presumably meant — these are transcription inconsistencies, not necessarily patent-text errors.

I'll search for litigation involving US patent 9477219 across patent litigation databases.

Initial searches returned irrelevant results. Let me search specific litigation databases.

The searches so far haven't surfaced any litigation. Let me try more targeted queries on patent litigation databases and court records.

Summary of Findings

Based on my searches, I found no evidence of any litigation involving U.S. Patent No. 9,477,219.

Search methodology and constraints

I searched web-accessible litigation and patent sources, including queries directed at:

• The patent number "9477219" combined with litigation terms (lawsuit, plaintiff, defendant, complaint, infringement)
• The Unified Patents litigation portal (portal.unifiedpatents.com/litigation)
• CourtListener/recap records
• The patent title and assignee (TSMC) in a litigation context

Important caveats on my search:

• My search tools could not directly query the Unified Patents litigation case-list API or PACER; I could only run general web searches, and the Unified Patents portal pages that surfaced did not return this patent.
• Several results returned different patent numbers (e.g., U.S. 9,517,219 — the Almirall dapsone patent; various reexamination control numbers). Per the strict rule, I did not treat these as the patent at issue. None of them is US 9,477,219, and I have excluded them.

Positive (non-litigation) evidence from the record

The authoritative patent text provided in the prompt indicates the patent's prosecution and post-grant history, which contains no mention of any litigation:

• Patent: US 9,477,219 B2, "Dynamic compensation in advanced process control"
• Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
• Application: US 12/731,348; filed 2010-03-25; granted 2016-10-25
• Legal status: Expired – Fee Related; lapsed for failure to pay maintenance fees effective 2024-10-25 (lapse recorded 2024-12-02)
• The Google Patents "Families Citing/Cited" tables list only other patents and publications (US 8,295,965; US 2013/0110477; CN 106292814; CN 107104095, etc.) — these are citations, not litigation.
• No "Litigation" or "Reexamination" entries appear in the record. There is a related Chinese family member (CN 102201323 B), but that is a patent family member, not a lawsuit.

Conclusion

No known litigation involving US 9,477,219 was identified. This is consistent with its profile: it is a defendant-side (TSMC) process-control patent that was never held by an NPE, and it has expired for non-payment of maintenance fees. I recommend confirming this directly against the Unified Patents litigation case list and PACER/LEXIS docket searches if a definitive negative is required, since my web-search tooling could not query those databases exhaustively. I state this explicitly rather than asserting a definitive negative with certainty.

I'll verify the structured data against live sources before reporting.

Let me run targeted confirmation searches, including possible reexamination and the family.

Confirming there's no district court assertion or ex parte reexamination tied to this patent number.

Proceedings overview

Total AIA trial proceedings on file for US 9,477,219: 0. There are no IPRs, no PGRs, and no CBMs — the structured PTAB block reports the USPTO ODP API returns no AIA trial proceedings for this patent, and my independent web searches across PTAB/docket aggregators (Docket Alarm, Patexia, PTAB decisions, CourtListener) surfaced nothing naming this patent as the subject of a trial. The breakdown by status is therefore: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0 — all 20 claims (1–20) are UNTESTED in an AIA trial.

The defensive posture this gives a defendant is unusual, and it is not "the patent has survived IPRs and is hardened." It is: the patent was never challenged at the PTAB, and it is now dead for a different reason — the patentee stopped paying maintenance fees. Per the patent's own legal-events record, the fee lapse was docketed 2024-12-02 with the entry "PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)" / "PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362," effective date 2024-10-25. Any demand letter citing live claims of this patent is on very weak footing for ongoing conduct.

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No proceedings to report

There is no {PROCEEDING_NUMBER} to populate. I do not invent proceeding numbers, so this section records the negative finding and — because a defendant searching this number will hit confusing near-matches — the disambiguation.

Lookalike numbers that are NOT this patent. Each of these appeared in searches for "9,477,219" and must not be conflated with it:

I also note the non-patent citations on this patent's face (Chinese Patent Office Office Action dated 2012-03-19 in App. No. 201010192832.X; unpublished U.S. Appl. No. 13/286,337, filed 2011-11-01, "Multi-Factor Advanced Process Control Method and System for Integrated Circuit Fabrication") — these are prosecution/family documents, not PTAB filings, and neither is a proceeding against this patent.

What I could not verify. The structured block covers AIA trials only. I ran web searches for reexamination-type activity against this patent and found none, but I did not have a dedicated reexamination-register query channel, so I cannot state with high confidence that no ex parte reexamination request was ever filed. Treat that as unconfirmed rather than as a clean negative.

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Strategic summary

Claim status: nothing canceled, nothing sustained — everything is untested, and the whole patent has lapsed. US 9,477,219 issued 2016-10-25 with 20 claims (claim 1 method; claim 9 method of fabricating a semiconductor device; claim 14 system). No AIA tribunal has ever construed a term, ruled on a ground, or canceled a claim. All 20 claims remain exactly as issued — but the patent's enforceable life ended 2024-10-25 by operation of the maintenance-fee lapse, with the adjusted-expiration date of 2035-02-17 rendered moot. Assertion exposure therefore concentrates in the six-year § 286 damages window before lapse, not in the future.

Estoppel landscape: § 315(e)(2) estoppel is not in play. Because no petitioner has ever filed an IPR, PGR, or CBM against this patent, no party is estopped, and no ground is foreclosed. There is no "the petitioner already burned that reference" problem. A defendant today has the full universe of §§ 101/102/103/112 defenses available: the six references cited on the face of the patent (US 6,625,512 B1; US 7,797,073 B1; US 2004/0040001 A1; US 2004/0059456 A1; US 2006/0007453 A1; US 7,271,480 B2) plus any art the examiner never saw, and the patent's own family file history. The one thing estoppel would have given a defendant — a settled record of invalidity — does not exist.

Pattern signals: the absence of activity is the signal. This is a TSMC portfolio patent (inventors Chih-Wei Hsu, Jin-Ning Sung, Shin-Rung Lu, Jong-I Mou; sole family member CN102201323B, granted 2014-10-22). It was never asserted in the litigation I could locate, never drew an IPR petition, never drew a defensive-aggregator (Unified Patents or similar) filing, and never produced a Federal Circuit appeal. TSMC is an extraordinarily frequent IPR petitioner but rarely a PTAB respondent, and this patent shows the classic profile of a prosecution/defensive-asset patent that was allowed to lapse rather than a revenue patent that gets asserted. There is no litigation-driven IPR chain to reconstruct.

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Recommended next steps

• If you are being asserted against, the threshold question is whether there is anything left to assert. Verify the maintenance-fee lapse directly in USPTO PatentCenter (https://patents.google.com/patent/US9477219/en and the PatentCenter record for App. No. 12/731,348). The event record reads: 2024-06-17 fee reminder mailed; 2024-12-02 lapse for failure to pay maintenance fees; 2024-12-02 "patent expired due to nonpayment of maintenance fees under 37 CFR 1.362"; effective date 2024-10-25. Demand letters that ignore this are a strong bad-faith / Rule 11 signal.
• Scope the past-infringement exposure, not future exposure. A lapsed patent cannot be infringed by post-lapse conduct. Accused conduct occurring on or before 2024-10-25, and within the six-year lookback of 35 U.S.C. § 286 from any complaint date, is where a live damages theory could theoretically sit — which in 2026 means roughly late-2020 forward at the earliest as a practical matter.
• Watch for revival. Under 37 C.F.R. 1.378 a patentee may petition to revive an expired patent for unintentional delay in paying maintenance fees, with statutory limits that I am not going to state from memory with confidence. A defendant should (a) monitor the PatentCenter record for a revival petition, (b) preserve intervening-rights arguments for conduct during the lapse, and (c) if revival occurs, immediately reassess the invalidity record — because at that point the patent would be live and entirely unchallenged, with no estoppel and no PTAB record, making an IPR or an early § 101/§ 112 summary judgment motion the natural defensive path.
• If no PTAB activity exists, say so plainly — done. No proceeding number, no FWD, no judge panel, no appeal, and no settlement exist to report for US 9,477,219. I have not manufactured any. The correct defense file entry today is "no AIA trial history; patent expired for non-payment of maintenance fees effective 2024-10-25; confirm no revival."

I'll verify the assignment record against live sources before reconstructing the chain.

Let me verify the specific reel/frame and check for any post-issuance transfers.

Let me check the TSMC patent-divestiture angle and inventor mobility, since TSMC did transfer patents to Mosaid in 2022.

Assignment Reconstruction — US 9,477,219 B2

Verification note on methodology. Google Patents' legal-events feed for this patent is the authoritative record I could retrieve. It exposes exactly one recorded assignment and no post-issuance reassignment, security, license, merger, change-of-name, or release event. I could not open the USPTO Assignment Center record view directly (my tooling returned search results, not the Assignment Center record detail page), and the Assignment Center's per-patent record detail — including the correspondent field — was not surfaced in any indexed source. Where a field below is unavailable, I say so rather than guess.

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Inventors

Employment determination. All four are recorded as assignors conveying to Taiwan Semiconductor Manufacturing Company, Ltd. on the single assignment of record, and all four are listed as TSMC inventors on third-party inventor indices (Patent Leaderboard). That is consistent with — but not proof of — all four being TSMC employees at the time of filing. The recorded assignment instrument itself does not state an employer relationship; it states inventor residency addresses in Taiwan (Hsin-Chu / Tainan area for similarly-timed TSMC filings, though I do not have the individual addresses for these four specifically).

Unusual-departure pattern: Unclear / not determinable. I found no evidence of any of the four inventors departing TSMC within 12 months of the 2010-03-25 filing, and no assignment record consistent with a departing-inventor portfolio transfer. My targeted search on inventor mobility hit the tool-call limit before returning results, so I cannot affirmatively rule it out. No fire-sale precursor is present in the record.

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Original assignee

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) — named as both original and current assignee on the issued patent. Principal office: No. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu 300-78, Taiwan.

• Line of business: the world's largest dedicated (pure-play) semiconductor foundry. Founded 1987-02-21; registration no. 22099131; ~65,000 employees (2025 credit report). Publicly traded (NYSE: TSM; TWSE: 2330).
• Does TSMC ship/use a product embodying the claims? Yes — the claimed subject matter is an Advanced Process Control (APC) loop (modeling module + metrology feedback + WAT tool) for its fabs. TSMC's own annual report describes deploying intelligent manufacturing systems from front-end to back-end fabs and applying AI to process control across its GIGAFAB facilities. The claims read on foundry process control, i.e., TSMC's core service.
• Current status: operating — healthy, no bankruptcy, no acquisition, no dissolution.

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Assignment timeline

One recorded assignment only.

• Executed 2010-03-18 to 2010-03-25 (latest signature date) / recorded 2010-03-25 — Reel 024135/0913 (USPTO reel/frame per Google Patents legal events; REEL/FRAME 024135/0913)
  • Conveyance: Assignment (Assignment of Assignors' Interest) — original inventor-to-company assignment
  • Assignor: Chih-Wei Hsu; Jin-Ning Sung; Shin-Rung Lu; Jong-I Mou (four individual inventors, jointly)
  • Assignee: Taiwan Semiconductor Manufacturing Company, Ltd., No. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu, Taiwan
  • Correspondent: Not available. The correspondent of record for reel 024135/0913 was not exposed by any source I could retrieve. Inference flagged as inference: overlapping-vintage TSMC US assignments were recorded through several different firms — Haynes and Boone, LLP (e.g., reels 022946/0815 and 036728/0682), WPAT, PC (e.g., reel 060242/0852), and Eschweiler & Potashnik, LLC (e.g., reel 050453/0142). Because TSMC used multiple outside firms in this era, and because no NPE recurrence is in play here, no correspondent signal can be attributed to this patent on the present record. Do not treat the Haynes and Boone reference as this patent's correspondent.
  • Context: Standard employee/inventor assignment bundled with filing of application 12/731,348 on the same day as the filing date. Not an acquisition, not a fire-sale, not a securitization, not a transfer to an asserter.

Post-issuance record: none. Google Patents lists no reassignment after grant (2016-10-25). The only subsequent legal events are administrative: notice of allowance (2016-05-19), patent grant (2016-10-05/2016-10-25), 4th-year maintenance fee paid (2020-04-14), maintenance-fee reminder (2024-06-17), lapse for failure to pay maintenance fees effective 2024-10-25 (recorded 2024-12-02), and final lapse entry (2024-12-24).

Near-miss to exclude explicitly. TSMC did divest patents to a known monetization entity: MOSAID Technologies Inc. acquired five US patents (US 9,349,655; 7,842,577; 8,338,909; 8,952,547; 9,564,433) from TSMC under an assignment executed 2022-04-28 and recorded 2022-05-26 at Reel 060024/0288, correspondent Conversant IP Management Corp / Julie McLeod, docket "TSMC TO MOSAID." US 9,477,219 is not among them. Mosaid later asserted ten other former-TSMC patents against Intel in W.D. Tex. (1:25-cv-00677, filed 2025). This transaction is a real "privateering" datapoint about TSMC generally, but it does not touch this patent and must not be attributed to it.

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Timeline diagram

timeline
    title Ownership of US 9477219
    2010 : Filed by TSMC inventors
         : Assigned to TSMC reel 024135 frame 0913
    2011 : Pre-grant publication 2011 0238197
    2016 : Patent issued
    2024 : Lapsed for unpaid maintenance fee

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NPE / troll-pattern signals

1. Shell-entity transfer — not present. No transfer out of TSMC appears anywhere in the record; the sole assignment (reel 024135/0913, 2010-03-25) runs inbound to the operating company, not to a licensing LLC. No "IP/Holdings/Ventures"-suffixed assignee exists in this chain.

2. Known asserter in the chain — not present. Current assignee is TSMC (operating foundry). No Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Round Rock, or Spangenberg entity appears at any point. The Mosaid/Conversant acquisition of sister TSMC patents (reel 060024/0288) does not include this patent.

3. Repeat correspondent across the chain — unclear / not applicable. The chain has one link, so recurrence is structurally impossible. The correspondent field for reel 024135/0913 is not retrievable from my sources; this is an open gap requiring a direct USPTO Assignment Center lookup. No adverse correspondent inference can be drawn.

4. Cascading transfers — not present. Zero post-issuance assignments; no <24-month chained LLC hops; no common-principal pattern.

5. Pre-litigation transfer — not present. No infringement suit naming US 9,477,219 was found (consistent with the earlier section's finding: no 2026 CAFC, district court, or PTAB activity on this patent). There is therefore no transfer within 6 months of any suit — the patent has never been asserted.

6. Bankruptcy fire-sale — not present. TSMC has not filed Chapter 7/11; no IP-sale-in-bankruptcy event.

7. Privateering — not present as to this patent. TSMC's 2022 transfer of other patents to Mosaid (reel 060024/0288, 2022-04-28/2022-05-26) is a genuine TSMC→NPE divestiture, but this patent was not included; TSMC retained it. Do not conflate the two.

8. Defensive aggregator (anti-NPE) — not present. Chain terminates at an operating company, not at RPX, AST, LOT, Unified Patents, or OIN.

Additional fact bearing on any assertion analysis: the patent lapsed for non-payment of maintenance fees, effective 2024-10-25 (recorded 2024-12-02). It cannot be asserted and cannot be the subject of a live IPR/PGR (which requires an unexpired patent). The previously listed adjusted expiration of 2035-02-17 is moot.

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Verdict

Insufficient data (with an affirmative ownership finding).

Justified because the entire recorded ownership chain for US 9,477,219 consists of one instrument — the original inventor-to-company assignment recorded 2010-03-25 at Reel 024135/0913 — with no post-issuance records of any kind in Google Patents' legal events (grant 2016-10-25 is followed only by maintenance-fee administration and a 2024-10-25 lapse). That matches the rubric's "only the original assignment" trigger, and it means there is no downstream NPE chain to score. Every NPE/troll signal above is "not present," and the one real TSMC→NPE divestiture in the same portfolio (Mosaid, Reel 060024/0288, 2022-04-28) excluded this patent, so no adverse inference is available. Ownership is nonetheless clear and unbroken: TSMC remains the sole assignee; the patent is now expired and unassertable.

Open verification gap: the correspondent of record for Reel 024135/0913 could not be retrieved and should be confirmed directly at the USPTO Assignment Center.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 9477219) or https://assignment.uspto.gov/patent/index.html, and cross-check the patent page at https://patents.google.com/patent/US9477219/en.

I'll research each cited prior-art reference for US 9,477,219. Let me run parallel searches.

Let me research the remaining cited references and confirm the primary patent record.

Prior-Art Analysis for US 9,477,219 B2 ("Dynamic compensation in advanced process control")

Scope note / search limitation. I reached my tool-call budget before I could open the USPTO Patent Center record for 9,477,219 or fetch the specification of the last cited reference (US 7,271,480 B2). Everything below is grounded in (a) the authoritative Google Patents full text you already supplied and (b) indexed documents retrieved in this session. Where I could not verify a reference's content, I say so explicitly rather than inferring. I did not query USPTO Patent Center directly, so treat the "cited-by-examiner" attributions as Google-Patents-derived, not certified.

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A. The complete citations list for 9,477,219 (built on the prior section, not repeating it)

The front page lists 6 U.S. patent citations and 2 non-patent citations. One subtlety worth flagging that the earlier summary did not: five of the six carry the Google Patents asterisk (* = cited by examiner), while US 7,271,480 B2 carries no asterisk in the "Citations (6)" table — i.e., on the face of the record it appears not to have been an examiner citation. That materially changes how much weight to give it.

Non-patent citations: (i) Chinese Patent Office Office Action dated 2012-03-19, Appl. No. 201010192832.X; (ii) unpublished U.S. Appl. No. 13/286,337 (filed 2011-11-01, "Multi-Factor Advanced Process Control Method and System for Integrated Circuit Fabrication").

Because the application's effective filing date is 2010-03-25 (pre-March-16-2013), the pre-AIA § 102 framework governs. Every reference above qualifies as prior art — the publications under § 102(b) (all published more than one year before 2010-03-25), and US 7,797,073 B1 under § 102(e) (U.S. patent granted on an application filed 2002-05-28, before the '219 invention date).

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B. Reference-by-reference analysis

1. US 6,625,512 B1 — "Method and apparatus for performing final critical dimension control"

• Assignee/inventor: Advanced Micro Devices, Inc.; Greg Goodwin.
• Dates: filed 2000-07-25 (priority US 09/625,140); granted 2003-09-23. Also in family: TW 525254 B (Chinese-language counterpart).
• § 102 basis: § 102(b) (printed publication/patent > 1 yr before 2010-03-25).
• Brief description (retrieved): An APC loop for final critical-dimension (CD) control. A manufacturing run is processed; metrology data is acquired from the processed wafers; a "final critical dimension control adjustment process" is performed on that metrology data; and a feedback/feed-forward modification process is performed in response. The system includes a metal-deposition tool, a photolithography tool, an etch tool, machine interfaces sending control input parameters to each, and at least one metrology tool coupled with each of the process tools, plus a "final critical dimension control algorithm unit." It uses a manufacturing model 140 to generate control inputs.
• § 102 mapping to '219:
  • Overlap: model-driven control (element of claim 1's "providing a model"); metrology coupled to each process tool (claim 14's metrology tool); feedback/feed-forward adjustment.
  • Anticipation assessment: Weak for claim 1. Goodwin's loop measures the feature dimension and applies feed-forward/feedback to reach a target critical dimension — a physical process parameter is the controlled endpoint. Claim 1 requires the model to output a device parameter corresponding to an electrical wafer characteristic (claim 1) and requires the measured quantity to be the first process parameter driving recomputation of the second process parameter's target on the same wafer. Goodwin does not teach a device-parameter (electrical) target that generates process-parameter targets, nor the specific "measure P1 → re-derive target of P2 → run same wafer" sequencing. Relevant far more for § 103 (secondary-evidence/combination) than for § 102.

2. US 2004/0040001 A1 — "Method and apparatus for predicting device electrical parameters during fabrication"

• Applicant/inventors: Advanced Micro Devices, Inc.; Michael L. Miller and Christopher A. Bode. Granted as US 8,185,230 B2 (grant 2012-05-22; app. 10/225,638; adjusted expiration 2030-04-02). Family: EP 1,532,675 A1; TW I310971 B; WO 2004/019401 A1.
• Dates: filed 2002-08-22; published 2004-02-26.
• § 102 basis: § 102(b).
• Brief description (retrieved, verified against the granted US 8,185,230 text): This is the closest reference on the "update the model with the actual measured value" concept. The method "provides a set of initial characteristic values associated with the semiconductor device" (line width, spacer width, contact size, layer thicknesses, implant dose, implant energy); performs a first fabrication process; collects fabrication data associated with that first process; "replace[s] at least one of the initial characteristic values with the fabrication data collected for the first fabrication process to generate a first modified set of characteristic values"; and predicts a first value for at least one electrical characteristic of the device based on the modified set. The system has a first process tool, a first data-collection unit, and a prediction unit; the model may be linear/non-linear, including equation-based, neural-network, PCA, or PLS.
• § 102 mapping to '219:
  • This reference discloses the "replace initial value with measured actual value → recompute" mechanism, and it distinguishes physical characteristics (line width, spacer width, layer thickness, implant dose) from the electrical characteristic it predicts — exactly the physical/electrical split recited in claim 1, claim 9, and claim 14.
  • Anticipation assessment: Still not a clean § 102 hit for claim 1 or claim 9, but it is the strongest single reference. Its output is a prediction of the electrical characteristic, not a "revised target value of the second process parameter" that is then fed to a second fabrication tool that processes the same wafer in a later step (the '219 claim 1 ordering: first process → measure P1 → update model → revised P2 target → second process on same wafer). Miller computes the predicted device parameter; the '219 computes a new process-parameter setpoint. Also, Miller's update uses fabrication data generally, and its principal thrust is predictive modeling/early grading. Best characterized as § 103 primary art for claim 1 (combined with a feed-forward APC reference such as US 7,797,073 or US 6,810,296), not § 102.

3. US 2004/0059456 A1 — "Correlating an inline parameter to a device operation parameter"

• Inventor/applicant: Christopher A. Bode; Advanced Micro Devices, Inc. Granted as US 6,810,296 B2 (the granted text is retrieved and confirms the "dynamic targeting" method).
• Dates: filed 2002-09-25; published 2004-03-25.
• § 102 basis: § 102(b).
• Brief description (retrieved, verified against US 6,810,296): A method/apparatus for "dynamic targeting" in which inline parameter data relating to a processed workpiece is received; a determination is made whether the inline parameter would result in a value of a device operation parameter within a predetermined range; and at least one process operation performed upon the workpiece is adjusted when the inline parameter would not result in the device operation parameter being in range. Inline-parameter examples include shallow-isolation-trench CD, tunnel oxidation parameter, source/drain CD, film-stack measurement, post-etch CD, and WET parameter; the device operation parameter exemplified is erase time of a memory device. The flow (per the granted figure) is: analyze metrology data → analyze device operation based on current inline parameters → perform adjustment based on inline-parameter error → determine adjustments to specific process → apply feedback adjustments for subsequent wafers. System = a processing tool + process controller.
• § 102 mapping to '219:
  • Overlap: This is a strong conceptual match for the "inline (physical) parameter → device (electrical/operational) parameter" correlation (claim 1's model premise) and for adjusting a subsequent process based on a measured inline parameter.
  • Anticipation assessment: No anticipation, but potent § 103 art. Critically, Bode's adjustment is directed at subsequent wafers ("feedback adjustments to correct error in subsequent wafers in batch/lot") — exactly the limitation that the '219 claims deliberately exclude by reciting "the same wafer" in claims 1, 3, 9, and 14. And Bode adjusts a process operation based on whether a range is satisfied; it does not derive a revised numeric target for a second, different process parameter by back-substitution through a device-parameter model. So Bode teaches the correlation and the corrective-adjustment idea but not the same-wafer, cross-parameter re-derivation that distinguishes the '219 independent claims — a classic § 103 combination candidate.

4. US 2006/0007453 A1 — "Feature dimension deviation correction system, method and program product"

• Assignee: International Business Machines Corporation. Granted as US 7,289,864 B2 (grant 2007-10-30; app. 10/710,447; divisional/continuation US 7,502,660 B2). Listed generically in the '219 front page as IBM.
• Dates: filed 2004-07-12; published 2006-01-12.
• § 102 basis: § 102(b).
• Brief description (retrieved, verified against US 7,289,864): Corrects deviation of a feature dimension (e.g., CD) from a target. Method: first-measure the feature before processing to obtain an incoming dimension; conduct the process based on a process model; second-measure after processing for an outgoing dimension; determine an origin of any deviation (processing vs. metrology) using process reference wafers and measurement reference wafers; and adjust the measuring means and/or processing tool accordingly. Adjustments for upstream process variation are fed forward, and process/integrated-metrology adjustments are fed back during wafer processing (W2W and L2L control).
• § 102 mapping to '219:
  • Overlap: pre-measurement → process (based on a process model) → post-measurement → model adjustment → feed-forward to a subsequent operation, including at wafer-to-wafer granularity. This is closely related to the "update the model using the actual value" step of claim 1.
  • Anticipation assessment: No anticipation. IBM's controlled variable is a single feature dimension (physical); its target is a target structure dimension, not an electrical device parameter. Its "origin of deviation" logic and its reference-wafer diagnostics are directed at diagnosing whether the tool or the metrology caused the error — a different problem than back-propagating a measured physical parameter through a device-parameter model to recompute a different physical parameter's target. Relevant under § 103 (and possibly § 102 as to claim-dependent details like feed-forward adjustment of a later process), but it cannot anticipate the lock-step physical→electrical→physical chain of claim 1.

5. US 7,271,480 B2 — "Constraint stiffener design"

• Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) — same assignee as the '219 patent.
• Dates: filed 2005-09-29; granted 2007-09-18.
• § 102 basis: § 102(b) (if it is in fact relied on).
• Brief description: Per the front-page listing it is a TSMC patent directed to a "constraint stiffener design" — a structural/fabrication topic, not an APC/process-control method.
• ⚠️ Explicit uncertainty flag: I was unable to retrieve the specification of US 7,271,480 B2 before exhausting my search budget, so I cannot characterize its disclosure at the level needed for a claim-element-by-element § 102 mapping. Two further cautionary points: (i) it is the only one of the six without the "cited by examiner" asterisk, suggesting it entered the record other than through examiner citation; and (ii) its title and subject matter (stiffener/constraint structures) do not map onto any limitation of claims 1, 9, or 14 on their face. I would treat it as at most background/common-ownership art with low § 102 relevance unless its full text shows otherwise. This must be verified against the actual document.

6. US 7,797,073 B1 — "Controlling processing of semiconductor wafers based upon end of line parameters"

• Applicant/inventor: Advanced Micro Devices, Inc.; Christopher A. Bode (listed assignee; inventors incl. Alexander J. Pasadyn). Note: later subject to a GlobalFoundries assignment chain and a 2020 TSMC assignment per the retrieved legal events.
• Dates: priority 2002-05-28; granted 2010-09-14.
• § 102 basis: § 102(e) (granted on an application filed before the '219 invention; pre-AIA). It is not § 102(b) because it published/granted after 2010-03-25.
• Brief description (retrieved, verified against US 7,797,073): Models end-of-line (EOL) parameters (yield, reliability, performance) and correlates them with inline parameters (CD, film thickness, overlay accuracy, resistivity, deposition duration) via an "inline-parameter-to-target-EOL-parameter model" 330. That model produces target inline parameters which, if achieved, yield the targeted EOL parameters. A feedback correction unit 340 corrects subsequently processed wafers in a lot, and a feed-forward compensation unit 350 makes compensation adjustments to subsequent processes to compensate for errors from previous processes "to more closely approach target inline parameters." A sorted, weighted objective function weights EOL parameters. System includes processing tool 510, process controller 310 (an APC framework), and metrology tool 550.
• § 102 mapping to '219:
  • Overlap: This is the closest reference to the "derive target process-parameter values from a target device/end-of-line parameter, then adjust subsequent processing" architecture at the heart of claims 1 and 14. It explicitly generates target inline parameters from a target EOL parameter and feed-forward compensates a subsequent process for a prior process's error — matching significant portions of claim 1's "derive target values of first and second process parameters based on a specified target value of the device parameter" and "feed-forward" concepts, and claim 14's modeling-module/process-tool/metrology-tool structure.
  • Anticipation assessment: Closest of all six, but still not full § 102 anticipation of the independent claims as issued. Differences that defeat anticipation: (a) US 7,797,073's feedback correction is expressly directed to "subsequently processed semiconductor wafers" and its compensation to "subsequent processes" — it does not recite measuring the actual first process parameter and then re-running the model to produce a revised target for the second process parameter on the same wafer; (b) it does not recite the '219's final step of measuring the actual device parameter after both processes with the model-update loop conditioned on the measured device parameter "substantially approaching" the target (claim 1's wherein-clause). It is, however, very strong § 103 art when combined with Miller (US 2004/0040001) and/or Bode (US 2004/0059456).

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C. Bottom-line conclusions

1. No single cited reference appears to anticipate independent claim 1, 9, or 14. The references each disclose part of the chain — (i) inline→device-parameter correlation (Bode US 2004/0059456 / US 6,810,296), (ii) replacing an assumed value with a measured actual value in a model (Miller US 2004/0040001 / US 8,185,230), (iii) feed-forward compensation of a subsequent process from a prior process's results (IBM US 2006/0007453 / US 7,289,864; AMD US 7,797,073) — but none discloses the full lock-step, same-wafer sequence of claim 1 (measure actual first process parameter → update model → derive revised target of the second process parameter → run second step on the same wafer → then measure the actual device parameter).

2. The strongest § 103 combination is US 7,797,073 B1 (primary) + US 2004/0001 A1 (Miller), optionally + US 2004/0059456 A1 (Bode). Miller supplies the electrical-characteristic-prediction-with-measured-value-substitution mechanism; Bode supplies the inline→device-parameter correlation and corrective adjustment; US 7,797,073 supplies the model-generated target inline parameters plus feed-forward compensation. The '219's "same wafer" and "revised target value of the second process parameter" limitations would be the non-obviousness battleground.

3. The "same wafer" limitation is the strategic crux. Bode (US 2004/0059456) and US 7,797,073 both visibly operate on subsequent wafers/lots in their express feedback paths, which is precisely what the '219 independent claims amended away from (consistent with the prior section's file-history note that "obtained as a result of" and "same wafer" language appears to be prosecution amendments). Any invalidity theory must therefore supply the same-wafer, cross-parameter re-derivation from some combination, not from any single cited reference.

4. Practical relevance today is limited. As flagged in the prior section, 9,477,219 lapsed for non-payment of maintenance fees effective 2024-10-25 (lapse recorded 2024-12-02). An expired patent cannot be asserted and cannot be the subject of a new IPR. This § 102 analysis is therefore chiefly useful for (a) scope/validity context of the CN 102201323 B family member, (b) defensive/portfolio analysis, and (c) understanding the pre-AIA record.

Uncertainties I am explicitly flagging:

• US 7,271,480 B2's disclosure is unverified in this session (tool budget exhausted); I cannot responsibly state what it anticipates. Its title/subject matter and the absence of the examiner-citation asterisk suggest low relevance, but this must be confirmed against the document.
• The "cited by examiner" attribution derives from Google Patents' asterisk convention, not from a direct USPTO Patent Center / examiner-citation (PTO-892) check.
• The exact sub-issue date relationships for pre-AIA § 102(e) as to US 7,797,073 B1 should be confirmed against its application filing date (its listed priority 2002-05-28 implies an earlier parent; the granted application's actual filing date governs the § 102(e) date).

I'll research the cited prior art references so I can do a grounded element-by-element §103 analysis.

Let me pull deeper detail on the two closest references and the TSMC "constraint stiffener" reference to confirm their relevance.

Obviousness Analysis of U.S. 9,477,219 B2 under 35 U.S.C. § 103

0. Scope, sources, and standard applied

Governing law. U.S. 12/731,348 was filed 2010-03-25, so pre-AIA § 103(a) applies, with the Graham v. John Deere framework (scope/content of the prior art; differences; level of ordinary skill; secondary considerations) and the KSR Int'l v. Teleflex supplementation on motivation to combine (predictable results, finite identified solutions, design incentives, common sense).

Prior art relied on. Per the "Prior Art"/Citations section of the patent page, I use only the six U.S. references cited on the face of the patent plus the family-cited references. I flag at the end which listed items are not usable prior art (the "Prior Art Keywords"/citation tables contain one item I recommend excluding).

Confidence caveat (stated up front). The element-by-element mappings below rest on the abstracts, claim text, and specification excerpts I retrieved for each reference (emphasized Google Patents excerpts and the granted counterparts US 8,185,230 and US 6,810,296). I did not retrieve full page/line cites for every reference, and I could not confirm Miller's disclosure of an explicit feed-forward adjustment of the next step's target. Any invalidity contention would need the full reference PDFs and the '219 file wrapper.

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1. Level of ordinary skill (PHOSITA)

At the 2010 priority date: a bachelor's degree in electrical engineering, materials science, physics, or chemical engineering, plus roughly 2–5 years of experience in semiconductor process integration or APC, or equivalent. That person is familiar with: APC frameworks and process controllers; multivariate/linear modeling of physical process parameters to electrical device parameters; inline metrology (CD-SEM, scatterometry, film thickness); and end-of-line/wafer-acceptance electrical test. All six references are squarely within this skill set — indeed, five of the six are AMD process-control patents/applications in exactly this art unit (G05B 19/418 / G06F 19/00).

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2. Claim-construction touchpoints that drive the § 103 analysis

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3. The cited prior art, and its relevance

Two notes on the citation table. (i) In the "Citations (6)" table, US 7,271,480 is the only entry without the examiner-citation asterisk — consistent with it being a procedural/assignee-own reference rather than substantive prior art, and it is not analogous to the control claims. (ii) The non-patent citation US Appl. 13/286,337 ("Multi-Factor Advanced Process Control…", filed 2011-11-01) post-dates the 2010-03-25 priority and is therefore not prior art to '219; it appears merely to be a related co-pending TSMC filing. Do not use it in a § 103 ground.

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4. Dispositive element chart for independent claim 1

Reading: Miller supplies limitations (a), (c), (d), (e) — including the exact "substitute the measured actual for the modeled value, then re-compute" step that is the heart of claim 1. Bode '073 supplies (b), (f), (g), (i) — deriving downstream targets from an electrical/EOL target and feed-forwarding a prior step's error into the next step's target. The overlap is near-total.

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5. Grounds of rejection

Ground A — Miller '001 in view of Bode '073 (primary ground; anticipates-or-obvious for claims 1–8, 17–18)

• Miller = model + first process + measure + substitute actual into the model + re-compute the electrical device parameter (US 8,185,230, FIG. 3 blocks 300–340; "replace at least one of the initial characteristic values with the fabrication data collected for the first fabrication process to generate a first modified set of characteristic values… predict a first value for at least one electrical characteristic").
• Bode '073 = electrical EOL target → physical inline targets, and adjust the target inline parameter of a downstream step, using feed-forward compensation "to compensate for errors resulting from previous processes" (feedback correction unit 340; feed-forward compensation unit 350).
• Motivation: identical field (APC), identical problem (stage-to-stage drift accumulating into a final electrical miss), and the references are commonly assigned with overlapping inventorship (Bode is an inventor on '456 and '073 and a co-inventor on Miller '001). Under KSR, the substitution of a measured actual for a modeled target value in a linear model is a predictable mathematical substitution, and combining it with a known feed-forward-to-next-step controller does no more than yield the expected result.

Ground B — Bode '456 in view of Miller '001 and '073 (claims 1, 4, 9, 14, 16)

Bode '456 discloses a physical inline parameter (STI CD, post-etch CD, wafer electrical test parameter) correlated to an electrical device-operation parameter (erase time), with "at least one of a feedback adjustment and a feed-forward adjustment upon a process performed upon said workpiece" (US 6,810,296 claim 10). It supplies the electrical-characteristic-as-function-of-physical-parameter model and the adjust-the-current-workpiece step. Miller supplies the measured-actual model update; '073 supplies EOL→inline target derivation. This ground is especially clean for claim 4, whose parameter lists are essentially recited verbatim in '456 (STI CD, post-etch CD) and '073 (CD, film thickness, overlay).

Ground C — US 6,625,512 in view of Miller '001 (claims 1, 3, 5–8, 19–20)

'512 discloses the multi-tool, model-based architecture (manufacturing model 140 → control inputs to tools 110, 112) with a final-CD-control algorithm unit 160 that drives a "feedback/feed-forward modification process" to subsequent processes. Combined with Miller's substitution of measured actuals, this renders the multi-stage compensation loop of claims 1 and 3 obvious. '512 also directly maps onto the "optimizing module" of claims 7/19 (the final-CD-control algorithm unit that modifies control input parameters) and claim 20.

Ground D — IBM '453 in view of '073 or Miller (claims 1, 3, 9, 11)

IBM '453 discloses measuring an incoming dimension before a process and an outgoing dimension after the model-based process, determining the deviation, and adjusting the process/measurement, including "adjustments for wafer processing variation of previous process tools [that] can be fed forward" and "adjustments for the process and/or integrated metrology tools… fed back." This is the same pre-step-measure → next-step-correct architecture on the same wafer/feature, and it is a strong secondary reference against the "same wafer" and "feed-forward of the first parameter's actual" limitations (element (g)).

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6. Claim-by-claim conclusions

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7. Motivation to combine (why a PHOSITA would have done this)

1. Same field and same problem. Every reference attacks APC drift: '073 states the objective of "achiev[ing] end-of-line results that are acceptably close to the targeted end-of-line parameters"; Miller targets early prediction/control of electrical parameters; '512 targets final-CD error. The '219 background paragraph (drift accumulating across stages) is the problem these references already identify.
2. Overlapping authorship and assignee. Bode is a named inventor on '456 and '073 and a co-inventor on Miller '001 — all AMD. This is strong evidence that the combination was within the ordinary artisan's working knowledge, not an unpredictable leap.
3. Predictable, mechanical result. Replacing a modeled target value with the measured actual value, then re-solving a linear model, is a mathematical substitution yielding a predictable result — the paradigm KSR case. No new physical principle is invoked.
4. Finite, identified solutions. Given the drift problem, the artisan has a small menu: (i) feedback to the next step vs. next wafer; (ii) which measured parameter to substitute. The claims select one of these known options — KSR "obvious to try."
5. Design incentive / enabling system exists. '073 and '512 already provide the APC framework, controllers, and inter-tool data buses needed to implement the loop; the '219 system claim merely arranges known APC components.

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8. Secondary considerations (and why they likely fail)

• No unexpected results in the record. The asserted advantage (better yield/hitting the device target) is precisely the expected result of feeding a measured first-step value forward into the second-step target. That is not evidence of non-obviousness.
• No long-felt-need nexus. The AMD references predate '219 by 5–8 years and describe the same solution, which cuts against a long-felt-need argument.
• Commercial/enforcement weight is low. The patent lapsed for non-payment of maintenance fees effective 2024-10-25 (consistent with the previously-prepared sections), which undercuts any "industry praise/commercial success nexus" argument.
• No known litigation has ever been brought on this patent (consistent with the earlier litigation section), so there is no adjudicated record of secondary considerations.

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9. Where the patent could survive (§ 103 weaknesses in the grounds, and candidate rebuttals)

1. "On the same wafer." The strongest non-obviousness argument is that the primary references' feedback is wafer-to-wafer/next-lot ('073's feedback correction unit 340) while '219 recites a second process on the same wafer. Rebuttal: '073's feed-forward compensation unit 350 explicitly compensates "errors resulting from previous processes… within a particular lot," and IBM '453 measures incoming/outgoing dimensions around the same process step and "feed[s] forward" prior-tool variation. Together they reach within-wafer feed-forward.
2. "Deriving a revised target value of the second process parameter." Miller predicts the device parameter rather than a revised process-parameter target. Rebuttal: '073's "adjusting a target inline parameter" and '456's adjust-the-process step supply that limitation; the combination is the whole point of a feedback-loop APC.
3. "wherein the updating … and the deriving … are performed so that the measured actual value … substantially approaches the specified target" — a result-oriented "wherein" clause. Rebuttal: '073 uses the identical functional language ("acceptably close to the targeted end-of-line parameters"), so this clause reads on the prior art rather than distinguishing it.
4. Prosecution-history estoppel. Because "obtained as a result of the … process" and "the same wafer" appear to have been added during prosecution (allowance 2016-05-19; grant 2016-10-25), the applicant may have argued these limitations distinguish the art. This is the single most important thing to verify — pull the file wrapper from USPTO Patent Center before finalizing any contention.

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10. Bottom line

On the cited record, claims 1–20 are, more likely than not, obvious under pre-AIA § 103, and the strongest ground is:

US 2004/0040001 A1 (Miller) in view of US 7,797,073 B1 (Bode), optionally further in view of US 2004/0059456 A1 (Bode) and/or IBM US 2006/0007453 A1.

Miller supplies the model, the first process step, the measured actual, and the substitution of that measured value into the model; Bode '073 supplies electrical-target-to-physical-target derivation and feed-forward correction of the next step; Bode '456 supplies the physical-inline-to-electrical-device-parameter correlation and the feedback/feed-forward process adjustment; IBM '453 supplies same-wafer pre/post measurement and prior-tool feed-forward. Every independent claim (1, 9, 14) is covered by this combination, and the dependent claims add only routine design choices (linear model form, conventional parameter lists, wafer-to-wafer reuse, and separate metrology vs. WAT measurement).

The only plausible non-obviousness foothold is the "second fabrication process on the same wafer" + "deriving a revised target of the second process parameter" coupling, and even that is arguably met by the feed-forward teachings of '073 and '453. Any challenge should confirm, from the full reference texts and the '219 file wrapper, (i) whether Miller discloses an adjust-the-next-step action rather than prediction only, and (ii) precisely what applicant argued to distinguish "same wafer."

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Explicit uncertainty flags for this § 103 section:

• Element mappings rely on the abstracts/spec excerpts returned by web search, not verified page-and-line cites for each reference. Full PDFs are needed before filing.
• I could not retrieve Miller's full specification to confirm whether it expressly feeds the predicted electrical characteristic forward to adjust a subsequent process target; if it does, claim 1 may be anticipated (not merely obvious) by Miller alone.
• The "Prior Art Keywords" list on the page (parameter / target value / wafer / tool / actual value) is an auto-generated keyword table, not a reference list; I did not treat it as prior art.
• US 7,271,480 (TSMC) is listed in the citation table but is non-analogous (device/layout, not process control) and should be excluded from any § 103 ground; the non-patent citation US Appl. 13/286,337 post-dates the priority date and is likewise not prior art.