US 9093473

Here is a concise summary of US patent 9093473:

Patent Number: US9093473B2
Title: Method for fabricating metal-oxide semiconductor transistor
Current Assignee: Marlin Semiconductor Ltd
Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
Filing Date: 2014-07-15
Issue Date: 2015-07-28
Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a method for manufacturing a Metal-Oxide Semiconductor (MOS) transistor. The core idea is to first create a gate pattern on a semiconductor substrate and then form an epitaxial layer next to this gate pattern. Crucially, after the epitaxial layer is formed, a second photo-etching step is performed on the gate pattern to create a slot within it, effectively dividing the original gate pattern into two separate gates.

Litigation Status (as of April 26, 2026):

The patent family has ongoing litigation. A PTAB case, IPR2025-00879, was filed but not instituted due to procedural reasons. Additionally, US cases related to this patent have been filed in the Texas Western District Court (case 1:25-cv-00215), the Texas Eastern District Court (case 2:25-cv-00171), and the International Trade Commission (cases 337-TA-3809 and 337-TA-1443). There is no specific mention of US9093473 in the CAFC May 2026 scheduled cases, and the CAFC case information provided general resources rather than specific dockets for this patent number.

Known litigation involving US patent 9093473 includes the following cases:

1. PTAB Case: IPR2025-00879

• Plaintiff(s) (Petitioner): TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, APPLE, INC., BROADCOM, INC., AND QUALCOMM, INC. [cite: Patents Google US9093473B2 Legal Events 2025-06-10]
• Defendant(s) (Patent Owner): Marlin Semiconductor Limited. [cite: Patents Google US9093473B2 Legal Events 2025-06-10]
• Jurisdiction: Patent Trial and Appeal Board (PTAB). [cite: Patents Google US9093473B2 Legal Status PTAB case IPR2025-00879]
• Case Number: IPR2025-00879. [cite: Patents Google US9093473B2 Legal Status PTAB case IPR2025-00879]
• Filing Date: April 17, 2025. [cite: Patents Google US9093473B2 Legal Events 2025-06-10]
• Outcome or Current Status: Not Instituted - Procedural. [cite: Patents Google US9093473B2 Legal Status PTAB case IPR2025-00879]

2. US District Court Case: Texas Western District Court

• Plaintiff(s): Longitude Licensing Ltd. and Marlin Semiconductor Limited.
• Defendant(s): [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), Broadcom Inc., Qualcomm Inc., Taiwan Semiconductor Manufacturing Company Limited (TSMC), Lenovo Group Limited, Motorola Mobile Communication Technology Ltd., Motorola (Wuhan) Mobility Technologies Communication Company Limited, and OnePlus Technology (Shenzhen) Co., LTD.
• Jurisdiction: U.S. District Court for the Western District of Texas. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Western District Court]
• Case Number: 1:25-cv-00215. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Western District Court]
• Filing Date: March 21, 2025.
• Outcome or Current Status: Stayed. The case was stayed pending the final disposition of ITC Investigation No. 337-TA-1443.

3. US District Court Case: Texas Eastern District Court

• Plaintiff(s): Longitude Licensing Ltd. and Marlin Semiconductor Limited.
• Defendant(s): Lenovo Group Limited, Motorola Mobile Communication Technology Ltd., Motorola (Wuhan) Mobility Technologies Communication Company Limited, OnePlus Technology (Shenzhen) Co., Ltd., and Taiwan Semiconductor Manufacturing Corporation Limited.
• Jurisdiction: U.S. District Court for the Eastern District of Texas. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Eastern District Court]
• Case Number: 2:25-cv-00171. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Eastern District Court]
• Filing Date: February 13, 2025.
• Outcome or Current Status: Stayed. The case was stayed pending the final disposition of ITC Investigation No. 337-TA-1443, with the motion to stay granted on April 23, 2025.

4. US International Trade Commission (ITC) Investigation: 337-TA-1443

• Plaintiff(s) (Complainant): Longitude Licensing Ltd. and Marlin Semiconductor Limited.
• Defendant(s) (Respondent): Apple Inc., Broadcom Inc., Lenovo Group Limited, Motorola Mobile Communication Technology Ltd., Motorola (Wuhan) Mobility Technologies Communication Company Limited, OnePlus Technology (Shenzhen) Co., LTD., Taiwan Semiconductor Manufacturing Company Limited, and Qualcomm Inc.
• Jurisdiction: U.S. International Trade Commission (ITC). [cite: Patents Google US9093473B2 Legal Status US case filed in International Trade Commission (337-TA-1443)]
• Case Number: 337-TA-1443. [cite: Patents Google US9093473B2 Legal Status US case filed in International Trade Commission (337-TA-1443)]
• Filing Date: February 18, 2025.
• Outcome or Current Status: Active. The investigation was instituted on March 21, 2025, and an evidentiary hearing is scheduled for February 2, 2026.

The Google Patents page for US9093473 also lists a "US case filed in International Trade Commission" with case number "337-TA-3809". However, further research indicates that "3809" appears as an internal identifier associated with ITC Investigation 337-TA-1443 rather than a separate, distinct ITC investigation. Therefore, separate details for 337-TA-3809 as an independent litigation case are not provided.

Proceedings overview

One AIA trial proceeding has been filed against US patent 9093473. This proceeding resulted in a discretionary denial of institution, meaning no claims were invalidated. This gives the patent owner a hardened defensive posture, as the patent has withstood a challenge at the PTAB's institution stage.

IPR2025-00879 — Taiwan Semiconductor Manufacturing Company Ltd. and [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

• Type: Inter Partes Review
• Filed: 2025-04-17
• Status: Not Instituted - Procedural. The institution was discretionarily denied by the USPTO Director.
• Judge panel: Coke Morgan Stewart, Acting Under Secretary of Commerce for Intellectual Property and Acting Director of the United States Patent and Trademark Office.
• Petition grounds: The petition challenged the patent, with the petitioner arguing that there was a "material error by the Office" related to "certain teachings in Chien770 that appear to disclose the claimed features that the patent examiner indicated were not taught by the prior art of record, including Chien770." This suggests grounds under 35 U.S.C. § 102 and/or § 103, although the specific claims challenged are not detailed in the available information.
• Institution decision: Denied (discretionary denial) on 2025-09-03. The Director found discretionary denial appropriate because a final written decision was unlikely to issue before a parallel U.S. International Trade Commission ("ITC") investigation hearing (scheduled for February 2, 2026), which would result in significant duplication of effort, additional expense, and a risk of inconsistent decisions. Additionally, the patent had been in force for ten years, creating strong settled expectations for the patent owner, and the petitioner did not provide persuasive reasoning for the IPR being an appropriate use of Board resources.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: No information regarding an appeal to the Federal Circuit is publicly available as of this date.
• Defensive value: The patent owner successfully defended against this IPR petition, as institution was denied. This means the challenged claims of US9093473 remain intact and have not been invalidated by this PTAB proceeding. For a defendant, this indicates that an IPR-based defense on the grounds raised in this petition would be more challenging, as the Director has already found reasons to deny institution.

Strategic summary

Currently, all claims of US9093473 are sustained and remain untested by PTAB proceedings on the merits. One Inter Partes Review (IPR2025-00879) was filed by Taiwan Semiconductor Manufacturing Company Ltd. and Apple Inc. but was discretionarily denied institution by the USPTO Director on September 3, 2025. The denial was based on factors such as the timing relative to a parallel ITC investigation and the patent's age contributing to "settled expectations," rather than a ruling on the merits of the prior art.

The estoppel landscape remains largely open for other potential petitioners. Since institution was denied on procedural grounds rather than a final written decision on the merits, the strict estoppel provisions of 35 U.S.C. § 315(e)(2) might not fully apply to prevent future challenges on the same or reasonably could have raised grounds by different parties. However, a future petitioner might face similar discretionary denial arguments if parallel litigation circumstances exist. The involvement of Unified Patents in other IPRs suggests an active landscape of defensive challenges in the semiconductor space, although Unified Patents was not explicitly named as the petitioner for IPR2025-00879 (TSMC and Apple Inc. were).

Recommended next steps

• As a defendant, be aware that while IPR2025-00879 did not invalidate any claims of US9093473, the patent owner prevailed at the institution stage due to discretionary denial. This means the specific prior art grounds raised by TSMC and Apple Inc. against the patent were not adjudicated on the merits by the PTAB.
• The absence of an institution on the merits means that the core patentability arguments have not been thoroughly vetted in an AIA trial. If facing assertion, consider a thorough prior art search to identify new grounds or different arguments based on the prior art previously cited in IPR2025-00879, taking into account the Director's reasons for discretionary denial.
• Given the Director's emphasis on "settled expectations" and parallel litigation in the denial of institution for IPR2025-00879, any future PTAB challenge would need to carefully address these discretionary factors, perhaps by demonstrating a material error by the examiner during prosecution or by filing early in relation to any parallel litigation.
• For specific details on the Director's decision for IPR2025-00879, refer to the document titled "Director_Discretionary_Decision@uspto.gov Paper 11" dated September 3, 2025, by searching the PTAB-TACTS system (USPTO's Patent Trial and Appeal Case Tracking System) for IPR2025-00879.

Inventors

• Ming-Te Wei (United Microelectronics Corp)
• Wen-Chen Wu (United Microelectronics Corp)
• Lung-En Kuo (United Microelectronics Corp)
• Po-Chao Tsao (United Microelectronics Corp)

There are no unusual patterns indicating inventors departing within 12 months of filing.

Original assignee

The original assignee named on the issued patent US9093473B2 is United Microelectronics Corp (UMC). UMC is a major semiconductor foundry, providing manufacturing services for integrated circuits. They ship a wide variety of semiconductor products embodying many different claims. UMC is currently an operating company.

Assignment timeline

• 2010-07-08 (executed) / recorded 2014-07-15 — Reel 033309/0116
  • Conveyance: Assignment
  • Assignor: KUO, LUNG-EN, TSAO, PO-CHAO, WEI, MING-TE, WU, WEN-CHEN (all inventors)
  • Assignee: UNITED MICROELECTRONICS CORP., TAIWAN
  • Correspondent: N/A (Not listed on record)
  • Context: Original assignment from inventors to employer.
• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292
  • Conveyance: Assignment
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED, IRELAND
  • Correspondent: LEE & HAYES, P.C., 601 W RIVERSIDE AVE SUITE 1400, SPOKANE, WA 99201
  • Context: Transfer-to-asserter.

Timeline diagram

timeline
    title Ownership of US 9093473
    2010 : Inventors to United Microelectronics
    2014 : Application filed
    2015 : Patent granted
    2021 : Assigned to Marlin Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — present. On 2021-07-26 (recorded), the patent was assigned from United Microelectronics Corporation, an operating company, to Marlin Semiconductor Limited, a company incorporated in Ireland. The name "Marlin Semiconductor Limited" suggests a licensing-focused entity, and its incorporation in Ireland (often associated with favorable tax structures for intellectual property) further supports this. Without product information for Marlin Semiconductor Limited, it is highly indicative of a shell entity for patent monetization.
2. Known asserter in the chain — unclear. While Marlin Semiconductor Limited is the current assignee, it is not immediately recognizable as a widely known NPE from standard public lists like Acacia Research Corp, Marathon Patent Group, or Intellectual Ventures without further investigation. However, its characteristics align with typical NPE behavior.
3. Repeat correspondent across the chain — not present. The correspondent for the 2021-07-26 assignment to Marlin Semiconductor Limited is LEE & HAYES, P.C. This correspondent does not appear in earlier records for this patent. Without a broader dataset of other tracked patents, it's not possible to definitively flag this as a repeat correspondent for NPE activity.
4. Cascading transfers — not present. There are only two recorded assignments, and they are spaced several years apart (2010 to 2021), not indicating cascading transfers within a short period.
5. Pre-litigation transfer — unclear. The current patent information shows litigation events starting in 2025 (IPR filed 2025-06-10, US cases filed in 2025). The assignment to Marlin Semiconductor Limited occurred on 2021-07-26. This is more than 6 months before the first known litigation filing, so it is not a "pre-litigation transfer" as strictly defined for this signal.
6. Bankruptcy fire-sale — not present. The original assignee, United Microelectronics Corp, is still an active operating company.
7. Privateering — unclear. There is no public information or SEC filing data available in the patent record to suggest a privateering arrangement between United Microelectronics Corp and Marlin Semiconductor Limited.
8. Defensive aggregator (anti-NPE) — not present. The chain ends with Marlin Semiconductor Limited, which does not appear to be a defensive aggregator.

Verdict

NPE — high confidence

The transfer from United Microelectronics Corp, a prominent operating semiconductor foundry, to Marlin Semiconductor Limited, an entity incorporated in Ireland, is a strong signal of a shell-entity transfer for patent assertion. This, coupled with the lack of apparent product lines for the assignee and the subsequent filing of litigation in 2025 (as shown in the legal status section of the patent), indicates a high likelihood of NPE activity.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

As a technical patent analyst, I have reviewed US patent 9093473B2, titled "Method for fabricating metal-oxide semiconductor transistor." The core innovation of this patent, particularly articulated in Claim 1, is a method that includes forming an epitaxial layer adjacent to two sides of a gate pattern, and then, after forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot, thereby separating the gate pattern into two gates. This sequence is presented as a solution to issues encountered in conventional approaches where the slot is formed before the epitaxial layer.

To identify the most relevant prior art and assess potential anticipation under 35 U.S.C. § 102, I have examined the patent citations listed in US9093473B2. Due to the limitations of this tool in accessing and performing detailed technical analysis of the full claims and specifications for all cited patents, the brief descriptions are primarily derived from the patent titles, and the potential anticipation assessment is based on a high-level comparison to the key distinguishing features of US9093473's Claim 1. A definitive anticipation ruling would require a full claim-by-claim comparison against the complete text of each prior art reference.

Below are selected patent citations, prioritizing those marked as "Cited by examiner" and those whose titles suggest direct relevance to MOS transistor fabrication, gate structures, or epitaxial layers:

Most Relevant Prior Art for US9093473B2

1. US20120012904A1

   • Full Citation: US20120012904A1, "Metal-oxide semiconductor transistor and method for fabricating the same" by Ming-Te Wei et al.
   • Publication Date: 2012-01-19 (Filing Date: 2010-07-15)
   • Brief Description: This publication describes a metal-oxide semiconductor transistor and its fabrication method. Notably, this application shares at least one inventor with US9093473B2 and has the same priority date, indicating it is a related application, likely a parent or sibling. Such a related application, if disclosing the same invention, would be prior art under certain conditions (e.g., if it published earlier than the effective filing date of the asserted claims in US9093473B2, or if it's a parent application from which priority is claimed). The fact that this is by the same inventor(s) and has a similar title suggests a high degree of technical overlap.
   • Potential Anticipation: Highly likely to potentially anticipate Claim 1 and its dependent claims of US9093473B2, as it is a related application from the same inventive entity with a similar subject matter and an earlier publication date than US9093473B2. A detailed comparison of the claims would be necessary, but given the relationship, it might disclose the specific sequence of forming the epitaxial layer before the polysilicon slot.

2. US20090186475A1

   • Full Citation: US20090186475A1, "Method of manufacturing a MOS transistor" by Shyh-Fann Ting.
   • Publication Date: 2009-07-23 (Filing Date: 2008-01-21)
   • Brief Description: This patent application describes methods for manufacturing MOS transistors, a broad area directly relevant to US9093473B2. To determine specific anticipation, its disclosure regarding gate patterning, epitaxial layer formation, and any subsequent slot creation would be critical.
   • Potential Anticipation: This reference could potentially anticipate aspects of Claim 1, particularly the general steps of forming a MOS transistor, gate pattern, and epitaxial layer. The key question for anticipation of Claim 1 of US9093473B2 would be whether it explicitly teaches forming the polysilicon slot after the epitaxial layer.

3. US20100081245A1

   • Full Citation: US20100081245A1, "Methods for fabricating mos devices having highly stressed channels" by Advanced Micro Devices, Inc.
   • Publication Date: 2010-04-01 (Filing Date: 2008-09-29)
   • Brief Description: This patent application focuses on fabricating MOS devices with "highly stressed channels," which often involves the use of epitaxial layers (e.g., SiGe for compressive strain or SiC for tensile strain) to enhance carrier mobility. This directly relates to the context of epitaxial layer formation in US9093473B2 (e.g., lines-).
   • Potential Anticipation: While it focuses on stressed channels and epitaxial layers, it would only anticipate Claim 1 of US9093473B2 if it also teaches the specific sequence of forming the gate pattern, then the epitaxial layer, and subsequently forming a slot in the gate pattern using a second photo-etching process. Without seeing its full claims and description, direct anticipation of the specific timing of the slot formation cannot be confirmed.

4. US7745847B2

   • Full Citation: US7745847B2, "Metal oxide semiconductor transistor" by United Microelectronics Corp.
   • Publication Date: 2010-06-29 (Filing Date: 2007-08-09)
   • Assignee: United Microelectronics Corp., which is the original assignee of US9093473B2. This makes it a highly relevant piece of prior art from the same entity.
   • Brief Description: The title indicates a focus on the MOS transistor structure itself. Being from the same assignee, it likely covers related semiconductor manufacturing techniques and could potentially disclose aspects of gate formation and epitaxial layers.
   • Potential Anticipation: Given the common assignee, this patent could disclose a manufacturing method that includes elements of US9093473B2. The critical aspect for anticipation of Claim 1 would be whether it teaches the specific sequence of forming the epitaxial layer before the polysilicon slot in the gate pattern.

5. US7312129B2

   • Full Citation: US7312129B2, "Method for producing two gates controlling the same channel" by Freescale Semiconductor, Inc.
   • Publication Date: 2007-12-25 (Filing Date: 2006-01-25)
   • Brief Description: This patent explicitly mentions "producing two gates controlling the same channel," which directly relates to the concept of separating a single gate pattern into two gates as described in US9093473B2 (Claim 1: "separating the gate pattern into two gates"). This makes it highly relevant for potentially anticipating the outcome of the second photo-etching process.
   • Potential Anticipation: This patent is highly relevant to the "forming a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates" step of Claim 1. Detailed examination of its claims and description is needed to see if it also teaches the step of forming an epitaxial layer before this gate separation, which is the distinguishing feature of US9093473B2.

6. US6143606A

   • Full Citation: US6143606A, "Method for manufacturing split-gate flash memory cell" by Worldwide Semiconductor Manufacturing Corp.
   • Publication Date: 2000-11-07 (Filing Date: 1997-12-26)
   • Brief Description: The title specifically mentions "split-gate" and "manufacturing," making it relevant to the gate separation aspect of US9093473B2. Split-gate structures inherently involve a separation of a gate element.
   • Potential Anticipation: This patent could potentially anticipate the "forming a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates" element of Claim 1. The key for anticipation of Claim 1 of US9093473B2 would be whether this patent teaches the formation of an epitaxial layer before the split-gate formation.

General Statement Regarding Anticipation:

For each of the cited patents, and particularly for Claim 1 of US9093473B2, a thorough anticipation analysis under 35 U.S.C. § 102 would require a detailed, side-by-side comparison of every element of Claim 1 (and its dependent claims) against the complete disclosure (including all claims, specification, and drawings) of each prior art reference. The critical differentiating element in US9093473B2's Claim 1 is the sequence where the second photo-etching process for forming the gate slot occurs after the epitaxial layer is formed. Any prior art that explicitly teaches all the elements of Claim 1 in this specific order would anticipate it. Without full access to the detailed text and figures of each cited patent, it is not possible to provide a definitive claim-by-claim anticipation statement for all 49 references.

To analyze the obviousness of US patent 9093473 under 35 U.S.C. § 103, we will examine the independent claims and consider combinations of prior art references along with the motivation for a person having ordinary skill in the art (PHOSITA) to combine them. The key distinguishing feature of US9093473, as highlighted in its abstract and detailed description, is the sequence of steps, specifically forming the epitaxial layer before performing the second photo-etching process to create a slot in the gate pattern.

Independent Claim 1 of US9093473B2

Independent Claim 1 describes a method for fabricating a metal-oxide semiconductor (MOS) transistor, comprising:

1. Providing a semiconductor substrate.
2. Forming a silicon layer on the semiconductor substrate.
3. Performing a first photo-etching process on the silicon layer for forming a gate pattern.
4. Forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern.
5. After forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Prior Art Combination and Obviousness Analysis

The core of the obviousness argument rests on whether a PHOSITA, at the time of the invention (priority date 2010-07-15), would have been motivated to combine existing prior art elements in the claimed sequence, particularly regarding the timing of epitaxial layer formation and gate slot creation. The patent itself provides significant insight into the "conventional approach" and the problems it seeks to solve.

Primary Reference 1: US20050112817A1 (Taiwan Semiconductor Manufacturing Company, Ltd.)

• Disclosure: This patent describes a "Semiconductor device having high drive current and method of manufacture thereof," which involves forming strained source/drain regions using epitaxial layers.
• Specifically, it teaches:
  • Providing a semiconductor substrate.
  • Forming a gate structure on the semiconductor substrate (which typically includes a silicon layer, e.g., polysilicon). (See paragraph discussing "a gate structure 104 is formed on the semiconductor substrate 100").
  • Forming an epitaxial layer (e.g., SiGe or SiC) in the semiconductor substrate adjacent to two sides of the gate structure to function as source/drain regions. (See paragraph "Source/drain regions are then formed next to the gate structure 104. In this embodiment, the source/drain regions are formed by an epitaxial process... For example, the epitaxial layers may be SiGe layers or SiC layers.")
• Contribution to Claim 1: US20050112817A1 discloses steps (1), (2), (3) (forming the gate pattern), and (4) (forming the epitaxial layer adjacent to the gate pattern) of Claim 1. It does not, however, disclose the step of forming a slot in the gate pattern to separate it into two gates.

Secondary Reference 2: US20080090360A1 (Krivokapic)

• Disclosure: This patent, titled "Methods for fabricating multiple finger transistors," teaches how to split a single gate electrode into multiple gate electrodes (fingers) by forming a slot.
• Specifically, it teaches:
  • Forming a gate stack (e.g., a polysilicon gate stack) on a semiconductor substrate and defining a first gate electrode within it. (See paragraph).
  • Forming source/drain regions in the semiconductor substrate. (See paragraph).
  • Subsequently, a "second gate electrode" is formed in the gate stack, which involves splitting the initial gate electrode by creating a slot (as illustrated in Figure 4, showing slot 110 splitting gate electrode 104 into 104a and 104b).
• Key Timing: Krivokapic explicitly describes forming the source/drain regions before forming the second gate electrode (i.e., splitting the gate via a slot). (See paragraph "Thereafter, source/drain regions are formed in the semiconductor substrate and a second gate electrode is formed in the gate stack.").
• Contribution to Claim 1: US20080090360A1 discloses steps (1), (2), (3) (forming the gate pattern), and (5) (performing a second photo-etching process on the gate pattern to form a slot and separate it into two gates). Crucially, its sequence of performing the gate splitting after source/drain formation aligns with the "after forming the epitaxial layer" aspect of Claim 1, assuming the source/drain regions are epitaxial.

Motivation to Combine US20050112817A1 and US20080090360A1, driven by US9093473's own Background:

A PHOSITA would be motivated to combine the teachings of US20050112817A1 and US20080090360A1 for the following reasons:

1. Synergistic Performance Enhancement: Both references address transistor performance. US20050112817A1 aims to increase drive current through strained epitaxial source/drain regions, a known technique for high-performance MOS devices. US20080090360A1 teaches fabricating multiple-finger transistors, a common approach to further enhance current drive, reduce resistance, or improve device matching. A PHOSITA seeking to maximize MOS transistor performance would naturally combine these complementary techniques.
2. Addressing Known Problems in the Prior Art (as disclosed in US9093473 itself): The "Description of the Prior Art" section of US9093473 explicitly details the problems associated with the "conventional approach" of forming the polysilicon slot before the epitaxial layer. These problems include:
   • "Polysilicon residue and line end bridge" if the etching ratio for the slot formation is too low.
   • "Consumption of the hard mask" and "consumption of the spacer" if the etching ratio is too high, leading to "a portion of the gate is exposed and un-wanted epitaxial layer would be formed on the exposed portion of the gate."
     A PHOSITA, confronted with these well-articulated problems arising from the conventional sequence, would be strongly motivated to find a solution. The sequencing taught by Krivokapic (forming source/drain regions before splitting the gate), when applied to epitaxial source/drain regions (as taught by US20050112817A1), directly addresses the identified issues. By ensuring the epitaxial layer is formed before the potentially damaging slot-etching step, the gate structure is protected, preventing unwanted epitaxial growth on exposed gate portions. This represents a clear problem-solution motivation for adopting the sequence claimed in US9093473.

Therefore, a PHOSITA, having reviewed these prior art documents and being aware of the explicit problems associated with the "conventional approach" of slot formation before epitaxial layer growth (as detailed in the background of US9093473), would have been motivated to combine the features of US20050112817A1 and US20080090360A1 to arrive at the method claimed in US9093473, particularly the critical step of forming the epitaxial layer before the second photo-etching process that forms the slot. This combination, driven by clear motivations, renders Independent Claim 1 obvious under 35 U.S.C. § 103.

Dependent Claims

Dependent claims 2-10 elaborate on the process with additional steps such as forming hard masks, first and second spacers, lightly doped drains, and specific dielectric layers. Many of these steps are standard techniques in MOS transistor fabrication and are disclosed in various general semiconductor manufacturing patents (e.g., US6593197B2 for spacers, US7812399B2 for multi-layer gate structures and spacers). If the independent claim is found obvious, adding these conventional and well-known fabrication steps, especially when motivated by common design choices or known process improvements (like using protective dielectric layers to avoid rework issues as discussed in US9093473 itself), would also be considered obvious to a PHOSITA.