US 7923764

US Patent 7923764: Semiconductor Device and Method for Fabricating the Same

Title: Semiconductor device and method for fabricating the same

Current Assignee: Advanced Integrated Circuit Process LLC
Original Assignee: Panasonic Corp
Inventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
Filing Date: July 20, 2009
Issue Date: April 12, 2011

Abstract:
The patent describes a semiconductor device that includes a high dielectric constant gate insulating film formed on an active region within a substrate, a gate electrode on this insulating film, and an insulating sidewall on each side of the gate electrode. A key feature is that the high dielectric constant gate insulating film extends continuously from under the gate electrode to under the insulating sidewall. Furthermore, the portion of this insulating film under the sidewall is thinner than the portion under the gate electrode.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Semiconductor Device):
  This claim describes a semiconductor device featuring a gate insulating film made of a high dielectric constant material. This film is located on an active area of a semiconductor substrate, with a gate electrode positioned on top of it. Insulating sidewalls are present on the sides of the gate electrode. The crucial aspect is that the high dielectric constant gate insulating film is continuous, extending from directly beneath the gate electrode to beneath these sidewalls. Additionally, the part of the insulating film under the sidewalls is designed to be thinner than the part under the main gate electrode.

• Independent Claim 8 (Method for Fabricating a Semiconductor Device):
  This claim outlines a method for manufacturing the semiconductor device. It involves four main steps:
  a) Creating a high dielectric constant gate insulating film on an active region of a substrate.
  b) Forming a gate electrode on this high dielectric constant gate insulating film.
  c) After forming the gate electrode, etching the part of the high dielectric constant gate insulating film that is outside the gate electrode to reduce its thickness.
  d) After the etching step, forming an insulating sidewall on each side surface of the gate electrode.

USPTO and CAFC 2026 Dockets:
The patent US7923764 is currently active, with an anticipated expiration date of July 24, 2026.
According to the latest information available (fetched May 14, 2026), there are several ongoing litigation cases related to this patent:

• Two US cases were filed in the Texas Eastern District Court (case numbers 2:24-cv-00623 and 2:24-cv-00730).
• Two PTAB (Patent Trial and Appeal Board) cases, IPR2025-01079 and IPR2025-00829, were filed but not instituted due to procedural reasons.
• Additionally, the patent family has experienced its first worldwide litigation.

As of April 26, 2026, and based on the provided and searched information (up to May 14, 2026), no specific dockets for US7923764 in the U.S. Court of Appeals for the Federal Circuit (CAFC) for the year 2026 have been found. While district court cases or PTAB decisions could potentially lead to CAFC appeals, none are currently listed as active in the CAFC dockets for 2026.

Here is a list of known litigation involving US patent 7923764:

District Court Cases

1. Case Number: 2:24-cv-00623

   • Plaintiff(s): Advanced Integrated Circuit Process LLC
   • Defendant(s): United Microelectronics Corporation (UMC)
   • Jurisdiction: U.S. District Court, Eastern District of Texas
   • Filing Date: August 1, 2024
   • Outcome/Current Status: Ongoing. This case has been consolidated with case 2:24-cv-00730. A motion to transfer was pending as of April 28, 2025. The Markman hearing was scheduled for December 18, 2025. Fact discovery was set to close on January 29, 2026, and expert discovery by March 12, 2026. Dispositive motions were due by March 17, 2026, with a trial date set for June 22, 2026.

2. Case Number: 2:24-cv-00730

   • Plaintiff(s): Advanced Integrated Circuit Process LLC
   • Defendant(s): United Microelectronics Corporation (UMC) and Taiwan Semiconductor Manufacturing Company Limited (TSMC)
   • Jurisdiction: U.S. District Court, Eastern District of Texas
   • Filing Date: September 6, 2024
   • Outcome/Current Status: Ongoing. This is the lead case, consolidated with case 2:24-cv-00623 on December 6, 2024. TSMC filed a motion to dismiss for lack of personal jurisdiction or, alternatively, to transfer, on November 29, 2024. The court granted AICP's motion for leave to conduct jurisdictional discovery on January 2, 2025. TSMC filed a motion to stay litigation pending the conclusion of inter partes reviews (IPRs) on April 28, 2025. The Markman hearing was scheduled for December 18, 2025. Fact discovery was set to close on January 29, 2026, and expert discovery by March 12, 2026. Dispositive motions were due by March 17, 2026, with a trial date set for June 22, 2026.

PTAB Cases

1. Case Number: IPR2025-01079

   • Petitioner(s): United Microelectronics Corporation, and UMC Group (USA)
   • Patent Owner(s): Advanced Integrated Circuit Process LLC
   • Filing Date: June 2, 2025
   • Outcome/Current Status: Not Instituted - Procedural. (Status as of 2026-05-16, from the provided patent text).

2. Case Number: IPR2025-00829

   • Petitioner(s): Taiwan Semiconductor Manufacturing Company Limited (TSMC)
   • Patent Owner(s): Advanced Integrated Circuit Process LLC
   • Filing Date: March 26, 2025 (TSMC filed its first IPR petition on this date, challenging asserted patents)
   • Outcome/Current Status: Not Instituted - Procedural. (Status as of 2026-05-16, from the provided patent text).

Proceedings overview

One AIA trial proceeding has been filed against US Patent 7,923,764. The petition for IPR2025-01079 was discretionarily denied, meaning no claims were invalidated or sustained as part of this proceeding. For a defendant, this indicates that the patent has not been successfully challenged through this IPR.

IPR2025-01079 — United Microelectronics Corporation et al. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-06-02
• Status: Discretionary Denial — the petition was not instituted by the PTAB.
• Judge panel: Not publicly available from the provided search results.
• Petition grounds: The petition challenged claims of US7923764 under statutory basis § 103 (obviousness) using various prior art references. Specific claims and prior art are not available in the provided snippets.
• Institution decision: Denied on 2025-11-26. The PTAB issued a discretionary denial based on the factors outlined in Fintiv (e.g., in view of parallel district court litigation).
• Final Written Decision: Not applicable as the petition was denied institution.
• Settlement / termination: Not applicable as the petition was denied institution.
• Appeal: Not publicly available from the provided search results whether the denial was appealed to the Federal Circuit.
• Defensive value: The discretionary denial means the patent owner successfully fended off this IPR challenge without any claims being addressed on the merits. This particular IPR does not offer a defendant any direct claim invalidation leverage, and it indicates the patent owner is capable of leveraging procedural defenses at the PTAB.

Strategic summary

Currently, no claims of US7923764 have been canceled or found unpatentable through AIA trial proceedings. The single IPR filed, IPR2025-01079, was discretionarily denied at the institution stage, meaning the PTAB did not proceed to a full review of the challenged claims. As a result, all claims of US7923764 remain officially UNTESTED on their merits by the PTAB.

Regarding estoppel, since IPR2025-01079 was denied institution based on a discretionary denial (likely related to Fintiv factors as per the Unified Patents data), statutory estoppel under 35 U.S.C. § 315(e)(2) for the petitioner (United Microelectronics Corporation et al.) may or may not apply depending on the specific grounds and the court's interpretation. However, other parties not in privity with the petitioner are not estopped from raising the same or similar prior art grounds against the patent in future proceedings or litigation. The denial of institution does not typically create broad estoppel against other potential challengers.

A notable pattern signal is that the petitioner was "United Microelectronics Corporation et al.", suggesting a direct industry player challenged the patent. The discretionary denial on Fintiv grounds also highlights the patent owner's strategy to manage parallel litigation with PTAB proceedings. Advanced Integrated Circuit Process LLC is listed as the current assignee, which is a common characteristic of entities engaged in patent assertion. Unified Patents also filed two IPRs (IPR2025-00829 and IPR2025-01079) against this patent, though the latter is listed with the inventor. The information provided in the initial prompt regarding IPR2025-01079 listing United Microelectronics Corporation et al. as the petitioner, and Google Patents showing Unified Patents filing IPR2025-01079 as well as IPR2025-00829, suggests Unified Patents may have been involved in orchestrating or funding the challenge by United Microelectronics Corporation, or there may be an overlap in the data sources.

Recommended next steps

For a defendant currently facing assertion of US7923764, it is important to understand that while IPR2025-01079 was filed, it did not result in any claims being invalidated. The discretionary denial means the claims themselves have not been substantively reviewed and confirmed patentable. The primary impact of IPR2025-01079 is a procedural hurdle that the petitioner encountered due to parallel district court litigation.

Defendants should conduct a thorough prior art search to identify potential grounds for a new IPR petition if they are considering a PTAB challenge. The Fintiv factors (and any subsequent changes in PTAB discretionary denial policy) would need to be carefully considered when filing a new petition, especially if there is ongoing district court litigation.

The information from Unified Patents indicates the discretionary denial for IPR2025-01079 (and IPR2025-00829) was "Procedural". This means the denial was not based on the merits of the prior art argument but rather on case management considerations, such as a parallel district court case. Therefore, the door is still open for other parties to challenge the claims on their merits.

The full details of the denial for IPR2025-01079, including the specific Fintiv analysis, would be found in the PTAB's Institution Decision, which can be accessed through the USPTO PTAB E2E system by searching for IPR2025-01079.

The patent has an anticipated expiration date of 2026-07-24. This means the patent has a limited remaining lifespan, which will influence the strategy for any potential defendant.

Further investigation into the details of the district court cases (e.g., 2:24-cv-00623, 2:24-cv-00730 in Texas Eastern District Court) associated with this patent would be crucial to understand the context of the PTAB's discretionary denial and to assess litigation risk and strategy.

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Citations:
https://portal.unifiedpatents.com/ptab/case/IPR2025-01079
https://portal.unifiedpatents.com/ptab/case/IPR2025-00829
https://patents.google.com/patent/[US7923764B2](/patent/US7923764B2)/en
https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00623
https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00730

Inventors

• Junji Hirase
• Akio Sebe
• Naoki Kotani
• Gen Okazaki
• Kazuhiko Aida
• Shinji Takeoka

Their employer at the time of filing was Panasonic Corp.

Original assignee

The original assignee on the issued patent US7923764B2 was Panasonic Corp. Panasonic Corporation is a multinational electronics company known for manufacturing a wide range of electronic products, including semiconductors. As of today, Panasonic Corporation is an operating company.

Assignment timeline

• 2020-05-27 (executed) / recorded 2020-06-03 — Reel 048999/0430
  • Conveyance: Assignment
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: Panasonic Corporation, 1000 Continental Boulevard, Multistop 1G-10, King of Prussia, PA 19406, United States.
  • Context: Internal reorg
• 2024-06-12 (executed) / recorded 2024-06-14 — Reel 060596/0064
  • Conveyance: Change of Name
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: Nuvoton Technology Corporation Japan, 2-10-1 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa, 222-8502, Japan.
  • Context: Change of name
• 2024-07-30 (executed) / recorded 2024-08-01 — Reel 060907/0313
  • Conveyance: Assignment
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
  • Correspondent: The Gray Law Firm, PC, 12221 Merit Drive, Suite 1000, Dallas, TX 75251, United States. This correspondent has appeared on other tracked patents on this site.
  • Context: Transfer to asserter

Timeline diagram

timeline
    title Ownership of US 7923764
    2009 : Filed by Panasonic Corp
    2011 : Issued
    2020 : Assigned to Panasonic Semiconductor
    2024 : Name changed to Nuvoton
    2024 : Assigned to Advanced Integrated Circuit Process LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent was assigned to ADVANCED INTEGRATED CIRCUIT PROCESS LLC in 2024-07-30 (Reel 060907/0313). This entity's name suggests a licensing-only function, and it is a known asserter.
2. Known asserter in the chain — present. ADVANCED INTEGRATED CIRCUIT PROCESS LLC is the current assignee, and Unified Patents has identified them as a high-frequency plaintiff.
3. Repeat correspondent across the chain — present. The Gray Law Firm, PC, with attorney name and address 12221 Merit Drive, Suite 1000, Dallas, TX 75251, United States, appears as the correspondent for the 2024-07-30 assignment to ADVANCED INTEGRATED CIRCUIT PROCESS LLC (Reel 060907/0313). This firm has been flagged as a repeat correspondent in other NPE assertion chains.
4. Cascading transfers — not present. There are only two assignments, with a name change in between, over four years.
5. Pre-litigation transfer — unclear. While the assignment to ADVANCED INTEGRATED CIRCUIT PROCESS LLC occurred on 2024-07-30, and there are currently two district court cases filed in 2024, the exact dates of the first infringement suits need to be verified against the specific filing dates in PACER to definitively establish a "pre-litigation transfer" within 6 months.
6. Bankruptcy fire-sale — not present. The initial transfers were internal reorgs and name changes, not bankruptcy proceedings.
7. Privateering — unclear. While the patent moved from an operating company chain to an NPE, there is no explicit evidence from SEC filings or other public coverage to indicate a specific privateering arrangement where Panasonic/Nuvoton is sponsoring the assertion against competitors.
8. Defensive aggregator (anti-NPE) — not present. The chain terminates with a known asserter, not a defensive aggregator.

Verdict

NPE — high confidence

This verdict is based on the transfer of the patent from NUVOTON TECHNOLOGY CORPORATION JAPAN to ADVANCED INTEGRATED CIRCUIT PROCESS LLC on 2024-07-30 (Reel 060907/0313), which is a known high-frequency plaintiff (asserter) per Unified Patents. Additionally, the correspondent for this transfer, The Gray Law Firm, PC, is identified as a repeat correspondent associated with NPE activity.

USPTO Assignment Center search page for verification: https://assignmentcenter.uspto.gov/

The most relevant prior art for US patent 7923764, based on a review of its cited patents, is identified as US6677209B2. This assessment is based on the patent's abstract describing a key structural feature that closely aligns with the independent claims of US7923764.

Most Relevant Prior Art: US6677209B2

• Full Citation: US6677209B2, "Transistor and manufacturing method thereof", issued January 13, 2004, to Hongo et al., and assigned to Matsushita Electric Industrial Co., Ltd.

• Publication/Filing Date: Issued January 13, 2004. The filing date for this patent (from Google Patents) is August 19, 2002 (U.S. Application No. 10/222,940).

• Brief Description: This patent describes a transistor structure featuring a gate insulating film that includes a high-k dielectric film. A notable characteristic of this gate insulating film is that the portion located under the gate electrode is thicker than the portion located under the sidewall spacers. The patent also details a manufacturing method for this transistor, which involves forming the gate insulating film and gate electrode, and then performing an etching process to thin a portion of the gate insulating film. This design aims to achieve high driving performance and reliability by addressing issues such as breakdown voltage reduction, parasitic capacitance, and short channel effects.

• Claims Potentially Anticipated under 35 U.S.C. § 102:

  • Claim 1 (Device Claim): US6677209B2 directly describes a structure where a high dielectric constant gate insulating film is present under both the gate electrode and the sidewall spacers, and the portion under the gate electrode is thicker than the portion under the sidewall spacers. This explicitly anticipates the core features of Claim 1 of US7923764, which states that the high dielectric constant gate insulating film "is continuously formed so as to extend from under the gate electrode to under the insulating sidewall, and at least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode."

  • Claim 61 (Method Claim): US6677209B2's abstract mentions a "manufacturing method thereof" and specifically notes that the described structure "is formed by using a method... in which a gate insulating film and a gate electrode are formed on a semiconductor substrate, and then an etching process is performed to thin a portion of the gate insulating film". This aligns with the key steps of Claim 61 of US7923764, particularly the step of "etching... part of the high dielectric constant gate insulating film located in an external side to the gate electrode to reduce a thickness of the part". Therefore, US6677209B2 appears to anticipate Claim 61.

  • Other Claims (Dependent Claims): While US6677209B2 broadly anticipates the fundamental device structure (Claim 1) and method (Claim 61) of US7923764, its abstract does not provide specific details that would directly anticipate the nuanced features of the dependent claims, such as:

    • The specific configurations of double sidewalls (Claims 2-6).
    • The presence of a "notch at a side end portion" of the high-k film (Claims 7-12).
    • The explicit inclusion of a "buffer insulating film between the substrate and the high dielectric constant gate insulating film" (Claims 13-24), although a multi-layer gate insulating film is generally contemplated.
    • The use of a "fully silicided gate electrode" (Claims 37-60).
    • Specific processing steps for double sidewalls, wet etching, or full silicidation described in dependent method claims (Claims 62-77).

  However, the existence of US6677209B2 could render many of these dependent claims obvious under 35 U.S.C. § 103, especially if the additional features were known in the art or simple optimizations.

Obviousness Analysis of US Patent 7,923,764 Under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 7,923,764 ("the '764 patent") by considering combinations of prior art references and the motivations a person having ordinary skill in the art (POSITA) would have had to combine them, with a reasonable expectation of success. The '764 patent claims semiconductor devices (specifically MISFETs) and methods for fabricating them, focusing on the gate insulating film structure.

Summary of the '764 Patent's Key Claimed Features

The core inventive concepts of the '764 patent, as described in the "SUMMARY OF THE INVENTION" and detailed embodiments, relate to a high dielectric constant (high-k) gate insulating film in a MISFET structure. The key features include:

1. Continuity of High-K Film Under Sidewall(s): The high-k gate insulating film is continuously formed to extend from under the gate electrode to under the insulating sidewall(s). This aims to prevent the side end portions of the high-k film from being in direct contact with the sidewalls, thereby suppressing degradation of its dielectric constant and insulation property.
2. Reduced Thickness Under Sidewall(s): At least part of the high-k gate insulating film located under the insulating sidewall(s) has a smaller thickness than the part under the gate electrode. This "convex shape" (or "double convex shape" for multiple sidewalls) aims to suppress increased capacitance between the gate and drain and adverse effects on circuit speed, while also facilitating ion implantation for extension/LDD regions.

The patent also describes variations such as:

• A double sidewall structure (offset sidewall and outer sidewall).
• The high-k film existing only under the first (offset) sidewall or under both, with different thickness profiles.
• A notch at the side end portion of the high-k film.
• A buffer insulating film (e.g., silicon oxide or oxynitride) between the substrate and the high-k gate insulating film.
• A fully silicided (FUSI) gate electrode.

Identified Prior Art

The '764 patent explicitly acknowledges the following prior art:

• FIGS. 16A and 16B (Ken Watanabe, "HfSiON - CMOS technology for achieving high performance and high reliability," Semi. Forum Japan, 2005): These figures illustrate structures of known MISFETs using a high dielectric constant gate insulating film.

  • FIG. 16A shows a single sidewall structure with a gate electrode (105) on a high-k gate insulating film (104), and an insulating sidewall (107) on its sides. Extension regions (110) are under the sidewall.
  • FIG. 16B shows a double sidewall structure, adding an insulating offset sidewall (106) between the gate electrode (105) and the outer sidewall (107).
  • The '764 patent states that in these known structures, "side end portions of the high dielectric constant gate insulating film are in direct contact with sidewalls," leading to degradation of the high-k film.

• H. Sayama et al., "IEDM Tech. Dig., 2000, p. 239": This reference is cited as disclosing a "double sidewall type MISFET in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner."

Obviousness Arguments

A POSITA in semiconductor device fabrication, at the time of the invention (priority date 2005-08-05), would have been motivated to combine features from the cited prior art and general knowledge in the field to arrive at the claimed invention, with a reasonable expectation of success.

Combination 1: Watanabe (FIGS. 16A/16B) + Motivation to Address Known High-K/Sidewall Degradation + Motivation to Control Parasitic Capacitance and Ion Implantation Depth

Rationale:
The '764 patent clearly identifies two significant problems with the existing high-k MISFET structures, such as those shown in Watanabe (FIGS. 16A and 16B):

1. Degradation of High-K Film: The direct contact between the side end portions of the high-k gate insulating film and the sidewalls leads to a "reduction in the dielectric constant and insulation property," deteriorating device characteristics and reliability. This was a recognized issue in the art of integrating high-k dielectrics. A POSITA would be motivated to protect the sensitive high-k material from degradation during subsequent processing, such as sidewall formation. Extending the high-k film to continuously cover the area under the sidewall, as taught by the '764 patent, would be an obvious modification to prevent its exposed edge from direct interaction with the sidewall material, thereby maintaining its integrity. The inventors themselves "have devised a MISFET structure in which a high dielectric constant gate insulating film is kept remaining under sidewalls to prevent end portions of the high dielectric constant gate insulating film from being in contact with the sidewalls, and a method for forming the MISFET structure."

2. Increased Parasitic Capacitance and Ion Implantation Issues: If the high-k film is simply extended under the sidewalls with uniform thickness, it leads to "a capacitance between gate/drain regions is increased, thus resulting in adverse effects on circuit speed." Furthermore, performing extension or LDD implantation through a thick high-k film is problematic due to the heavy metal content and small projection range (Rp) of implanted ions, necessitating increased acceleration energy and resulting in deeper junctions than desired.

   • Faced with the problem of increased capacitance and implantation issues after addressing high-k film degradation by extending it under the sidewalls, a POSITA would be strongly motivated to reduce the thickness of the high-k film in these peripheral regions. This is a common design trade-off: maintaining a thicker high-k film under the gate for strong gate control, while thinning it in the extension regions to minimize parasitic capacitance and enable shallower, more precise dopant profiles for improved short-channel effects. The patent explicitly states this motivation: "To cope with this problem, the inventors have devised a MISFET structure in which a high dielectric constant gate insulating film is kept remaining under sidewalls and part of the high dielectric constant gate insulating film located under the sidewalls is made to have a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under a gate electrode, and a method for forming the MISFET structure."

Therefore, combining the basic MISFET structures of Watanabe (FIGS. 16A or 16B) with the known problems in high-k integration and the conventional approaches to manage parasitic capacitance and ion implantation would lead a POSITA to the claimed structure where the high-k film is continuous under the sidewall(s) but with a reduced thickness in those regions. The manufacturing methods for achieving such stepped or reduced thickness profiles (e.g., selective etching) were also known in the art.

Combination 2: Watanabe (FIGS. 16A/16B) + Known Techniques for Interface Improvement (Buffer Layers)

Rationale:
The '764 patent describes an embodiment (Fourth Embodiment, FIG. 9) where a buffer insulating film (e.g., silicon oxide or oxynitride film 25) is provided between the substrate (1) and the high-k gate insulating film (4A). The patent states this improves the interface between the substrate and the gate insulating film, suppressing deterioration.

• The use of buffer layers, such as SiO2 or SiON, between a silicon substrate and a high-k dielectric film was a well-established technique in semiconductor manufacturing by 2005 to improve interface quality, reduce interface trap densities, and enhance carrier mobility. This was common knowledge for a POSITA working with high-k gate dielectrics.
• Therefore, integrating a known buffer layer between the substrate and the high-k gate insulating film of a Watanabe-type MISFET, regardless of whether the high-k film itself has a continuous and stepped profile, would be an obvious design choice for a POSITA seeking to improve device reliability and performance. The '764 patent acknowledges this, stating that applying a buffer layer to the first, second, or third embodiments would achieve the "same effects."

Combination 3: Watanabe (FIGS. 16A/16B) + Motivation for Performance Optimization (Notches, FUSI Gates)

Rationale:
The '764 patent introduces additional features like notches (e.g., FIG. 6, 7, 8, 10) in the side end portions of the high-k film and fully silicided (FUSI) gate electrodes.

• Notches: The patent states that the notch (20) further suppresses adverse effects on circuit speed due to increased capacitance. If the primary solution of a thinned high-k under the sidewall still presented some parasitic capacitance issues, further removal of the high-k material at the very edge (creating a notch) would be an obvious refinement for a POSITA aiming to minimize parasitic capacitance, as described in the modified example of the first embodiment.
• FUSI Gates: The eighth embodiment describes a FUSI gate electrode (16) to replace a conventional polysilicon gate. FUSI technology was known to offer advantages such as lower gate resistance, improved work function control, and better compatibility with high-k dielectrics. Applying FUSI technology to the gate electrode of a MISFET structure (like those of Watanabe, or the improved structures of the earlier embodiments of '764) would be an obvious design choice for a POSITA seeking to enhance gate performance and reduce overall device resistance.

Conclusion

The primary claims of US7923764, relating to the continuous, yet thickness-reduced, high-k gate insulating film under the sidewall(s), address known problems in high-k MISFET technology that a POSITA would have been motivated to solve. The identified problems (high-k degradation at sidewall interface, increased parasitic capacitance, and ion implantation challenges) and the proposed solutions (continuous, thinned high-k film, buffer layers, notches, FUSI gates) are presented by the patent itself as logical responses to these known issues. Therefore, the combination of basic MISFET structures (Watanabe, Sayama) with common knowledge regarding high-k material integrity, parasitic capacitance management, ion implantation control, interface engineering, and gate electrode optimization would render the claimed invention obvious under 35 U.S.C. § 103.

For US patent 7923764, the following details have been identified:

Projected Expiration Date:
The anticipated expiration date for US7923764 is July 24, 2026.

Patent Term Adjustments (PTA) & Patent Term Extensions (PTE):
The provided information indicates that the patent's anticipated expiration date (July 24, 2026) aligns with the nominal 20-year term from the filing date of its parent application, U.S. patent application No. 11/491,260 (filed July 24, 2006). This suggests that there were likely no Patent Term Adjustments (PTA) that significantly extended the patent term, or any adjustments were offset by applicant delay, resulting in the term ending on the statutory 20-year mark from the earliest U.S. filing date. Patent Term Extensions (PTE) are typically granted for delays in regulatory review for certain products (e.g., pharmaceuticals, medical devices). There is no information in the patent text or search results to suggest that US7923764 is eligible for or has received a Patent Term Extension under 35 U.S.C. § 156.

Continuation and Divisional Applications; Related Family Members:

• Parent Application (Divisional): US7923764 (Application No. US12/505,799) is a divisional application of U.S. patent application No. 11/491,260, which was filed on July 24, 2006, and later issued as U.S. Pat. No. 7,579,227.
• Original Priority Application: The earliest priority claim for this patent family traces back to Japanese Patent Application No. 2005-227457, filed on August 5, 2005.
• Published Application: US20090278210A1 is the published application corresponding to US12/505,799, the application that matured into US7923764B2.
• Child Applications (claiming priority from US7923764):
  • U.S. patent application No. 13/037,831, filed on March 1, 2011, which later issued as US8253180B2.
  • U.S. patent application No. 13/547,913, filed on July 12, 2012, which later issued as US8587076B2.

Defensive Disclosure: US Patent 7923764 Derivative Works

This document presents a series of derivative works and technical disclosures aimed at establishing prior art around US Patent 7923764, titled "Semiconductor device and method for fabricating the same." The objective is to illustrate numerous obvious variations and applications of the claimed inventions, thereby reducing the patentability of future incremental improvements by competitors.

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Derivatives of Independent Claim 1 (Semiconductor Device)

Independent Claim 1: A semiconductor device comprising: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode, wherein the high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall, and at least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

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1. Material & Component Substitution

Derivative 1.1: Alternative High-k Dielectric and Metal Gate Material

• Enabling Description: The high dielectric constant gate insulating film is fabricated using zirconium dioxide (ZrO2) or hafnium oxide (HfO2), with a thickness under the gate electrode between 3-5 nm and a reduced thickness under the insulating sidewall between 1-2 nm. The gate electrode is formed from a titanium nitride (TiN) or tantalum nitride (TaN) layer, offering improved work function tuning and reduced gate depletion effects compared to polysilicon. The insulating sidewalls are composed of silicon nitride (SiN). This configuration allows for lower equivalent oxide thickness (EOT) and better gate control.

graph TD
    A[Substrate (e.g., Silicon)] --> B{Active Region};
    B --> C[ZrO2 or HfO2 Gate Insulator];
    C -- Thinner under sidewall --> D[Insulating Sidewall (SiN)];
    C -- Thicker under gate --> E[TiN or TaN Gate Electrode];
    E -- on --> C;
    D -- flanking --> E;

Derivative 1.2: Organic High-k Dielectric with Carbon Nanotube Gate Electrode

• Enabling Description: The high dielectric constant gate insulating film is formed from an organic high-k polymer (e.g., polyimide-based or PVDF-TrFE copolymer) with a dielectric constant greater than 10. The thickness under the gate electrode is between 5-10 nm, reduced to 2-4 nm under the sidewalls. The gate electrode is comprised of a network of carbon nanotubes (CNTs), providing high conductivity and flexibility. The insulating sidewalls are formed from a low-k parylene material, deposited conformally. This structure is particularly suited for flexible electronic applications where mechanical resilience and organic compatibility are crucial.

graph TD
    A[Flexible Substrate] --> B{Active Region};
    B --> C[Organic High-k Polymer Film];
    C -- Thinner under sidewall --> D[Parylene Sidewall];
    C -- Thicker under gate --> E[Carbon Nanotube Gate Electrode];
    E -- on --> C;
    D -- flanking --> E;

Derivative 1.3: Ferroelectric Dielectric with Platinum Gate

• Enabling Description: The high dielectric constant gate insulating film utilizes a ferroelectric material such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT). This film exhibits a high dielectric constant and provides non-volatile memory capabilities or enhanced switching characteristics. The film has a thickness of 20-30 nm under the gate, reduced to 10-15 nm under the sidewalls. The gate electrode consists of a platinum (Pt) layer, known for its excellent work function and chemical inertness with ferroelectric materials. The insulating sidewalls are aluminum oxide (Al2O3).

graph TD
    A[Substrate] --> B{Active Region};
    B --> C[Ferroelectric (SBT/PZT) Film];
    C -- Thinner under sidewall --> D[Al2O3 Sidewall];
    C -- Thicker under gate --> E[Platinum Gate Electrode];
    E -- on --> C;
    D -- flanking --> E;

Derivative 1.4: Air-Gap Sidewall with Stacked High-k Dielectric

• Enabling Description: The high dielectric constant gate insulating film is a stacked dielectric consisting of an initial layer of silicon oxynitride (SiON) followed by a hafnium silicon oxynitride (HfSiON) layer, providing enhanced interface quality and high-k properties. The combined thickness under the gate is 4 nm, thinning to 1.5 nm under the sidewall. Instead of a solid insulating sidewall, an air-gap is intentionally created adjacent to the gate electrode, acting as an ultra-low-k dielectric spacer. This air gap is formed using a selective etching process and capped with a thin silicon nitride film to maintain structural integrity.

graph TD
    A[Substrate] --> B{Active Region};
    B --> C[SiON/HfSiON Stack];
    C -- Thinner under air gap --> D[Air Gap Sidewall (Low-k)];
    C -- Thicker under gate --> E[Gate Electrode (e.g., Polysilicon)];
    E -- on --> C;
    D -- flanking --> E;
    D_cap[SiN Cap Layer] -- over --> D;

---

2. Operational Parameter Expansion

Derivative 1.5: Cryogenic Operation with Ultra-Thin Dielectric Profile

• Enabling Description: A semiconductor device designed for cryogenic operation (e<50K). The high dielectric constant gate insulating film is a highly crystalline HfO2 layer, with a precisely controlled thickness of 2.5 nm under the gate electrode, and reduced to an ultra-thin 0.8 nm under the insulating sidewall. The gate electrode is composed of a superconducting alloy (e.g., NbTi) to minimize resistance at low temperatures. The insulating sidewalls are made of silicon dioxide (SiO2), engineered for minimal thermal contraction mismatch. This extreme thinning under the sidewall minimizes parasitic capacitance even at very low temperatures where quantum effects become significant.

stateDiagram
    direction LR
    CryoState : Operating at <50K
    GateControl : Ultra-thin HfO2 (0.8nm) under sidewall
    GateControl : Superconducting Gate (NbTi)
    Substrate : Silicon substrate

    CryoState --> GateControl
    GateControl --> Substrate

Derivative 1.6: High-Power RF Switch with Tunable Dielectric Zones

• Enabling Description: A MISFET for high-frequency ( > 100 GHz) RF switching applications requiring high power handling. The high dielectric constant gate insulating film is patterned to have a stepped thickness profile: 10 nm under the main gate region for high breakdown voltage, tapering down to 4 nm under an inner offset sidewall, and further reducing to 2 nm under an outer insulating sidewall. The dielectric material is tantalum pentoxide (Ta2O5), known for its high breakdown field. The gate electrode is tungsten (W) for robustness, and the sidewalls are silicon nitride/silicon dioxide (SiN/SiO2) composite. This multi-level thickness allows for optimized impedance matching and reduced Miller capacitance at high frequencies while maintaining high power integrity.

graph TD
    A[Substrate] --> B{Active Region};
    B --> C1[Ta2O5 Gate Insulator (10nm)];
    C1 -- under --> E[Tungsten Gate Electrode];
    E -- flanked by --> S1[Inner Offset Sidewall (SiN)];
    C1 -- continues thinner (4nm) under --> S1;
    S1 -- flanked by --> S2[Outer Insulating Sidewall (SiO2)];
    C1 -- continues even thinner (2nm) under --> S2;
    S2 -- External to --> C1;

Derivative 1.7: Radiation-Hardened FET with Varied Dielectric Thickness for Charge Trapping Management

• Enabling Description: A field-effect transistor designed for radiation-hardened applications (e.g., space electronics). The high dielectric constant gate insulating film is aluminum oxide (Al2O3), with a thickness of 8 nm under the gate electrode to maximize radiation tolerance by offering more charge trapping sites. This thickness is gradually reduced to 3 nm under the insulating sidewall. This thinner region under the sidewall helps to quickly dissipate trapped charges at the edges of the gate, preventing significant shifts in threshold voltage and maintaining device functionality in a high-radiation environment. The gate electrode is polysilicon and the sidewalls are silicon dioxide.

stateDiagram
    direction LR
    RH_FET : Radiation-Hardened FET
    Al2O3_Gate_Dielectric : Al2O3 (8nm) under Gate
    Al2O3_Sidewall_Dielectric : Al2O3 (3nm) under Sidewall
    Charge_Trapping : Manages charge trapping at edges
    Threshold_Stability : Maintains Vth stability

    RH_FET --> Al2O3_Gate_Dielectric
    RH_Gate_Dielectric --> Al2O3_Sidewall_Dielectric
    Al2O3_Sidewall_Dielectric --> Charge_Trapping
    Charge_Trapping --> Threshold_Stability

---

3. Cross-Domain Application

Derivative 1.8: Bio-FET for Real-time Metabolite Sensing

• Enabling Description: A bio-FET for real-time metabolite sensing in biological fluids. The high dielectric constant gate insulating film is a hafnium zirconium oxide (HfZrO) layer, which exhibits excellent biocompatibility and high sensitivity to changes in surface charge. The film thickness is 5 nm under the active sensing gate region, reducing to 1.5 nm under the insulating sidewalls. The gate electrode is functionalized with a receptor molecule (e.g., enzyme, antibody) for specific metabolite binding. The thinner dielectric under the sidewalls minimizes stray capacitance from non-sensing regions, enhancing the signal-to-noise ratio of the bio-detection event.

graph TD
    A[Substrate (e.g., Silicon)] --> B{Active Region};
    B --> C[HfZrO Gate Insulator (Biocompatible)];
    C -- Thinner under sidewall (1.5nm) --> D[Insulating Sidewall];
    C -- Thicker under sensing gate (5nm) --> E[Functionalized Gate Electrode (Receptor)];
    E -- on --> C;
    D -- flanking --> E;
    Fluid[Biological Fluid] -- interfaces with --> E;

Derivative 1.9: Photo-detecting Pixel with Integrated Gate Control

• Enabling Description: This device is integrated into a photo-detecting pixel array for advanced imaging systems. The high dielectric constant gate insulating film is tantalum pentoxide (Ta2O5), configured over a photodiode active region. The film has a primary thickness of 6 nm under a control gate for charge collection efficiency, and a reduced thickness of 2 nm under adjacent insulating sidewalls. This allows for localized depletion region control and minimizes capacitive crosstalk between neighboring pixels, enhancing pixel isolation and signal integrity. The gate electrode is a transparent conducting oxide (TCO) such as Indium Tin Oxide (ITO).

graph TD
    A[Substrate] --> B{Photodiode Active Region};
    B --> C[Ta2O5 Gate Insulator];
    C -- Thinner under sidewall --> D[Insulating Sidewall];
    C -- Thicker under control gate --> E[Transparent ITO Gate Electrode];
    E -- on --> C;
    D -- flanking --> E;
    Light[Incident Light] --> E;

Derivative 1.10: High-Temperature Pressure Sensor FET

• Enabling Description: A FET-based pressure sensor designed for high-temperature (up to 300°C) industrial process monitoring. The high dielectric constant gate insulating film is a silicon carbide (SiC)-based dielectric (e.g., SiC-HfO2 composite), providing stability at elevated temperatures. The film has a thickness of 15 nm under a flexible gate electrode (which deflects under pressure), reducing to 5 nm under rigid insulating sidewalls. The thicker gate dielectric ensures mechanical robustness and thermal stability, while the thinner sidewall dielectric helps to accurately define the sensing area and reduce edge effects in the pressure transducer. The gate electrode is a platinum-iridium alloy.

graph TD
    A[High-Temp Substrate (e.g., SiC)] --> B{Active Region};
    B --> C[SiC-HfO2 Dielectric];
    C -- Thinner under sidewall (5nm) --> D[Rigid Insulating Sidewall];
    C -- Thicker under flexible gate (15nm) --> E[Flexible Pt-Ir Gate Electrode];
    E -- on --> C;
    D -- flanking --> E;
    Pressure[Applied Pressure] -- deflects --> E;

---

4. Integration with Emerging Technologies

Derivative 1.11: AI-Optimized Gate Dielectric Profile for Neuromorphic Computing

• Enabling Description: A neuromorphic MISFET where the variable thickness profile of the high dielectric constant gate insulating film is dynamically optimized by an AI algorithm during an in-situ annealing or etching step. The gate insulating film is HfO2, with an initial uniform thickness. An AI agent, fed with real-time electrical feedback, directs a focused ion beam (FIB) or an atomic layer etching (ALE) process to sculpt the HfO2, creating a complex, non-uniform thickness profile (e.g., 2-5 nm under the gate, 0.8-2 nm under the sidewalls) that mimics synaptic weight adjustments for specific neural network functions. This allows for bespoke dielectric shaping for enhanced memristive or synaptic behavior.

sequenceDiagram
    participant AI as AI Algorithm
    participant Sensor as In-situ Electrical Sensor
    participant FIB_ALE as FIB/ALE Tool
    participant MISFET as MISFET Device

    AI->Sensor: Request electrical feedback
    Sensor->AI: Provide real-time I-V characteristics
    AI->AI: Analyze and determine optimal HfO2 profile
    AI->FIB_ALE: Command specific etch/deposition profile parameters
    FIB_ALE->MISFET: Apply focused etching/deposition
    MISFET->Sensor: Electrical change
    Sensor->AI: Provide updated feedback (loop until optimized)

Derivative 1.12: IoT-Enabled MISFET with Real-time Degradation Monitoring

• Enabling Description: A MISFET for IoT edge devices, featuring an integrated nanoscale impedance sensor within the sidewall structure. The high dielectric constant gate insulating film is Al2O3, with a nominal thickness of 4 nm under the gate and 1.5 nm under the sidewall. The integrated IoT sensor continuously monitors the impedance and breakdown characteristics of the thinner dielectric region under the sidewall. This real-time data is transmitted wirelessly to a central hub, allowing for predictive maintenance and early detection of device degradation or potential failure modes in harsh IoT environments.

classDiagram
    class IoT_MISFET {
        +Substrate
        +ActiveRegion
        +Al2O3_Gate_Insulator
        +GateElectrode
        +InsulatingSidewall
        +NanoImpedanceSensor
    }
    class NanoImpedanceSensor {
        +MonitorImpedance()
        +DetectDegradation()
        +TransmitData()
    }
    class WirelessModule {
        +ConnectToHub()
        +TransmitSensorData()
    }
    class CloudPlatform {
        +ReceiveData()
        +AnalyzeData(AI)
        +AlertMaintenance()
    }

    IoT_MISFET "1" -- "1" NanoImpedanceSensor : contains
    NanoImpedanceSensor "1" -- "1" WirelessModule : transmits via
    WirelessModule "1" -- "1" CloudPlatform : sends to

Derivative 1.13: Blockchain-Verified Manufacturing for High-Reliability MISFETs

• Enabling Description: A high-reliability MISFET where critical fabrication parameters of the high dielectric constant gate insulating film are recorded on a blockchain ledger. The HDK film is a HfSiON film, with a thickness of 3 nm under the gate and 1 nm under the sidewall. Each step of its formation, including precursor batch numbers, deposition temperatures, etching times, and thickness measurements (including the differentiated gate vs. sidewall thickness), is cryptographically hashed and appended to a distributed ledger. This provides an immutable and verifiable supply chain and manufacturing history, ensuring authenticity and compliance for critical applications where counterfeiting or substandard materials are a concern (e.g., aerospace, medical implants).

graph TD
    A[Material Precursors] --> B{HDK Film Deposition};
    B --> C{Gate Electrode Formation};
    C --> D{Selective Etching of HDK Film};
    D --> E{Sidewall Formation};
    E --> F{Thickness Measurement};
    F --> G[Blockchain Ledger (Immutable Record)];

    subgraph "Fabrication Steps"
        B -- Parameters --> G;
        C -- Parameters --> G;
        D -- Parameters --> G;
        E -- Parameters --> G;
        F -- Results --> G;
    end

---

5. The "Inverse" or Failure Mode

Derivative 1.14: Self-Protecting MISFET with Sacrificial Thinner Dielectric

• Enabling Description: A MISFET designed with a sacrificial, thinned high dielectric constant gate insulating film under the sidewall to act as a localized fuse or preferential degradation point. The gate insulating film is HfO2, 4 nm thick under the gate, and precisely etched to a highly vulnerable 0.5 nm under the sidewall. In the event of an overvoltage surge or ESD event, this ultra-thin region is designed to fail first in a controlled manner, isolating the more critical gate-channel interface and protecting the main device functionality. The failure generates a detectable impedance change, signaling an event without catastrophic device destruction.

stateDiagram
    direction LR
NormalOperation --> OvervoltageEvent: Overvoltage/ESD
OvervoltageEvent --> ThinDielectricFailure: Thinner Dielectric (0.5nm) Fails
ThinDielectricFailure --> GateProtection: Main Gate Insulator Protected
ThinDielectricFailure --> SignalImpedanceChange: Impedance Change Detected
GateProtection --> LimitedFunctionality: Continue Limited Operation

Derivative 1.15: Low-Power MISFET with Tunable Leakage Control

• Enabling Description: A MISFET optimized for ultra-low-power standby applications, where a controlled amount of gate leakage is acceptable or even desirable for certain operational states. The high dielectric constant gate insulating film is a HfSiON layer, 3 nm thick under the gate, and thinned to 1.2 nm under the sidewall. This thinner region is specifically engineered with controllable defect density (e.g., through localized annealing) to provide a regulated leakage path. In a "sleep" or "low-power" mode, the slight increase in leakage through the thinned sidewall region is balanced against reduced dynamic power consumption, facilitating faster wake-up times compared to a fully switched-off state.

graph TD
    A[Substrate] --> B{Active Region};
    B --> C[HfSiON Gate Insulator];
    C -- 3nm under gate --> E[Gate Electrode];
    C -- 1.2nm under sidewall, Controlled Leakage --> D[Insulating Sidewall];
    E -- on --> C;
    D -- flanking --> E;
    E -- activates --> Channel[Channel Region];
    C -- regulates --> Leakage[Controlled Leakage Path];

    subgraph Power Modes
        Normal --> Channel;
        Sleep --> Leakage;
    end

Derivative 1.16: Redundant Gate Insulator for Graceful Degradation

• Enabling Description: A MISFET incorporating a redundant high dielectric constant gate insulating film layer under the sidewall to enable graceful degradation upon primary dielectric failure. The primary gate insulating film is ZrO2, 3 nm under the gate, thinning to 1 nm under the sidewall. Directly beneath this thinned sidewall region, a secondary, slightly thicker (e.g., 2 nm) Al2O3 layer is formed as a backup dielectric. If the primary 1 nm ZrO2 region under the sidewall experiences breakdown, the device can continue to operate with slightly degraded performance, relying on the underlying Al2O3 layer, thereby preventing immediate catastrophic failure and extending operational lifetime.

graph TD
    A[Substrate] --> B{Active Region};
    B --> C1[Primary ZrO2 Film];
    C1 -- 3nm under gate --> E[Gate Electrode];
    C1 -- 1nm under sidewall --> D1[Inner Sidewall];
    B --> C2[Secondary Al2O3 Film (Backup)];
    C2 -- 2nm under sidewall --> D2[Outer Sidewall];
    E -- on --> C1;
    D1 -- flanking --> E;
    D2 -- flanking --> D1;

    subgraph Failure Logic
        D1_Active[Primary Sidewall Active];
        D1_Fail[Primary Sidewall Fail];
        D2_Active[Secondary Sidewall Active];

        D1_Active -- Normal Operation --> D1_Fail;
        D1_Fail -- Switches to --> D2_Active;
    end

---

Derivatives of Independent Claim 8 (Method for Fabricating a Semiconductor Device)

Independent Claim 8: A method for fabricating a semiconductor device, comprising the steps of: a) forming a high dielectric constant gate insulating film on an active region of a substrate; b) forming a gate electrode on the high dielectric constant gate insulating film; c) etching, after the step b), part of the high dielectric constant gate insulating film located in an external side to the gate electrode to reduce a thickness of the part; and d) forming, after the step c), an insulating sidewall on a side surface of the gate electrode.

---

1. Material & Component Substitution

Derivative 8.1: Atomic Layer Deposition (ALD) for HDK Film and Selective Wet Etching

• Enabling Description:
  a) Forming the high dielectric constant gate insulating film: Employing Atomic Layer Deposition (ALD) to deposit a Hafnium Silicate (HfSiO) film with precise thickness control on the active region.
  b) Forming the gate electrode: Standard deposition and patterning of a polysilicon gate electrode.
  c) Etching the HDK film: Utilizing a highly selective aqueous hydrofluoric acid (HF) based wet etching solution at controlled temperature (e.g., 25°C) to preferentially remove a portion of the HfSiO film external to the gate electrode, reducing its thickness by 50%. The etchant is formulated to have a high etch rate selectivity between HfSiO and the gate electrode material.
  d) Forming the insulating sidewall: Deposition of tetraethyl orthosilicate (TEOS) SiO2 via Low-Pressure Chemical Vapor Deposition (LPCVD), followed by anisotropic dry etching to form the sidewalls.

graph TD
    A[Substrate + Active Region] --> B{ALD HfSiO Deposition};
    B --> C{Polysilicon Gate Formation};
    C --> D{Selective HF Wet Etch of HfSiO};
    D --> E{LPCVD TEOS SiO2 Deposition};
    E --> F{Anisotropic Dry Etch for Sidewall};
    F --> G[Fabricated Device];

Derivative 8.2: Plasma Enhanced Atomic Layer Deposition (PEALD) for HDK and Reactive Ion Etching (RIE)

• Enabling Description:
  a) Forming the high dielectric constant gate insulating film: Employing Plasma Enhanced Atomic Layer Deposition (PEALD) to deposit Zirconium Oxide (ZrO2) on the active region, leveraging plasma for lower temperature processing and enhanced film quality.
  b) Forming the gate electrode: Deposition and patterning of a Work Function Metal (e.g., TiN) gate electrode.
  c) Etching the HDK film: Utilizing a fluorine-based Reactive Ion Etching (RIE) process with precise control over plasma power and gas flow (e.g., CF4/O2 chemistry) to anisotropically etch the ZrO2 film external to the gate electrode, achieving a 60% thickness reduction.
  d) Forming the insulating sidewall: Deposition of Silicon Nitride (SiN) using Plasma Enhanced Chemical Vapor Deposition (PECVD), followed by an anisotropic RIE process for sidewall formation.

graph TD
    A[Substrate + Active Region] --> B{PEALD ZrO2 Deposition};
    B --> C{TiN Metal Gate Formation};
    C --> D{Fluorine-based RIE Etch of ZrO2};
    D --> E{PECVD SiN Deposition};
    E --> F{Anisotropic RIE for Sidewall};
    F --> G[Fabricated Device];

Derivative 8.3: Spin-on Dielectric (SOD) for HDK Film and Laser Ablation Etching

• Enabling Description:
  a) Forming the high dielectric constant gate insulating film: Applying a Spin-on Dielectric (SOD) solution containing high-k nanoparticles (e.g., titanium dioxide (TiO2) precursors) onto the active region, followed by curing to form the dielectric film.
  b) Forming the gate electrode: Standard deposition and patterning of a highly doped polysilicon gate.
  c) Etching the HDK film: Using a pulsed UV laser ablation system to selectively remove and reduce the thickness of the TiO2 SOD film external to the gate electrode. The laser parameters (wavelength, pulse energy, scan speed) are tuned to precisely control the removal depth.
  d) Forming the insulating sidewall: Standard silicon oxide (SiO2) deposition via PECVD and anisotropic dry etching.

graph TD
    A[Substrate + Active Region] --> B{Spin-on TiO2 Precursor + Cure};
    B --> C{Polysilicon Gate Formation};
    C --> D{Pulsed UV Laser Ablation of TiO2};
    D --> E{PECVD SiO2 Deposition};
    E --> F{Anisotropic Dry Etch for Sidewall};
    F --> G[Fabricated Device];

---

2. Operational Parameter Expansion

Derivative 8.4: Cryogenic Etching of HDK Film for Enhanced Selectivity

• Enabling Description:
  a) Forming the high dielectric constant gate insulating film: Standard HfSiON film deposition.
  b) Forming the gate electrode: Standard polysilicon gate electrode formation.
  c) Etching the HDK film: Performing the etching step at cryogenic temperatures (e.g., -100°C to -150°C) using an SF6/O2 plasma. This ultra-low temperature etching process significantly enhances the selectivity between the HfSiON and the underlying substrate, allowing for extremely precise and damage-free thickness reduction (e.g., 75% reduction) of the HDK film external to the gate electrode without affecting the substrate or gate material.
  d) Forming the insulating sidewall: Standard SiN sidewall formation.

graph TD
    A[Substrate + Active Region] --> B{HfSiON Deposition};
    B --> C{Polysilicon Gate Formation};
    C --> D{Cryogenic SF6/O2 Plasma Etch of HfSiON};
    D --> E{SiN Sidewall Formation};
    E --> F[Fabricated Device];

Derivative 8.5: High-Vacuum, Low-Ion-Energy Etching for Angstrom-Level Control

• Enabling Description:
  a) Forming the high dielectric constant gate insulating film: ALD HfO2 film deposited with an initial thickness of 5 nm.
  b) Forming the gate electrode: TiN metal gate formation.
  c) Etching the HDK film: Utilizing a high-vacuum (e.g., < 10^-5 Torr) etching process with ultra-low ion energy (e.g., < 20 eV), such as a neutral beam etching or thermal atomic layer etching. This process enables Ångström-level precision in reducing the thickness of the HfO2 film external to the gate electrode (e.g., from 5 nm to 1.5 nm), minimizing sub-surface damage and creating an atomically smooth etched surface.
  d) Forming the insulating sidewall: Highly conformal Al2O3 sidewalls formed by ALD.

graph TD
    A[Substrate + Active Region] --> B{ALD HfO2 Deposition (5nm)};
    B --> C{TiN Gate Formation};
    C --> D{High-Vacuum Low-Ion-Energy Etch of HfO2 (to 1.5nm)};
    D --> E{ALD Al2O3 Sidewall Formation};
    E --> F[Fabricated Device];

Derivative 8.6: High-Temperature Annealing Post-Etch for Dielectric Re-densification

• Enabling Description:
  a) Forming the high dielectric constant gate insulating film: PECVD SiON film.
  b) Forming the gate electrode: Polysilicon gate.
  c) Etching the HDK film: Standard dry etching to reduce thickness. Immediately following this etching, a rapid thermal anneal (RTA) at 800-1000°C in an inert atmosphere (e.g., N2) is performed. This high-temperature step serves to re-densify any etching-induced damage in the thinned HDK film, passivate interface traps, and improve the overall dielectric integrity and reliability before subsequent processing.
  d) Forming the insulating sidewall: Standard SiO2 sidewall.

graph TD
    A[Substrate + Active Region] --> B{PECVD SiON Deposition};
    B --> C{Polysilicon Gate Formation};
    C --> D{Dry Etch of SiON};
    D --> E{Rapid Thermal Anneal (RTA)};
    E --> F{SiO2 Sidewall Formation};
    F --> G[Fabricated Device];

---

3. Cross-Domain Application

Derivative 8.7: Fabricating Variable-Thickness Dielectric in MEMS Resonators

• Enabling Description:
  a) Forming a high dielectric constant film: ALD HfO2 film is deposited across a sacrificial layer for a MEMS resonator structure.
  b) Forming an electrode: A metal (e.g., Au) resonant electrode is patterned on the HfO2.
  c) Etching the HDK film: Anisotropic dry etching is performed to create variable stiffness zones in the HfO2 film. The HfO2 under the main body of the resonant electrode is left thicker (e.g., 20 nm), while regions extending outwards, which will form the flexible hinges of the resonator, have their HfO2 thickness reduced (e.g., to 5 nm). This precise control of dielectric thickness translates to tailored mechanical properties for frequency tuning.
  d) Forming insulating sidewalls: SiO2 sidewalls define the etched regions and provide structural support. This method is crucial for fabricating high-performance MEMS resonators with custom frequency response characteristics.

graph TD
    A[Substrate + Sacrificial Layer] --> B{ALD HfO2 Deposition};
    B --> C{Au Resonant Electrode Formation};
    C --> D{Anisotropic Dry Etch of HfO2 (Variable Stiffness Zones)};
    D --> E{SiO2 Sidewall Formation};
    E --> F[MEMS Resonator with Tailored Stiffness];

Derivative 8.8: Fabrication of Graded Refractive Index Optical Waveguides

• Enabling Description:
  a) Forming a high dielectric constant film: A thin film of titanium dioxide (TiO2), chosen for its high refractive index, is deposited via PECVD on a silicon substrate destined to be an optical waveguide.
  b) Forming a masking layer: A photoresist mask is patterned defining the desired waveguide core and cladding regions.
  c) Etching the HDK film: A multi-step dry etching process is used to selectively reduce the thickness of the TiO2 film. The region intended to be the waveguide core remains at its original thickness (e.g., 200 nm), while the regions flanking it, forming the waveguide cladding, are progressively etched to reduced thicknesses (e.g., 100 nm, 50 nm). This creates a graded refractive index profile in the lateral direction.
  d) Forming insulating sidewalls: A silicon oxide (SiO2) buffer layer is deposited to encapsulate the graded TiO2, providing further optical isolation. This method enables advanced optical components with improved light confinement and mode control.

graph TD
    A[Silicon Substrate] --> B{PECVD TiO2 Deposition};
    B --> C{Photoresist Mask Patterning};
    C --> D{Multi-step Dry Etch of TiO2 (Graded RI)};
    D --> E{SiO2 Buffer Layer Deposition};
    E --> F[Graded Refractive Index Optical Waveguide];

Derivative 8.9: Manufacturing of Patterned Dielectric Layers for Lab-on-a-Chip Microfluidics

• Enabling Description:
  a) Forming a high dielectric constant film: A silicon dioxide (SiO2) film is deposited via PECVD on a glass substrate, serving as the base dielectric for microfluidic channels.
  b) Forming a gate electrode equivalent: A patterned chromium (Cr) masking layer is formed on the SiO2, defining future channel structures.
  c) Etching the HDK film: A wet etching process (e.g., buffered HF) is used to selectively reduce the thickness of the SiO2 film in regions adjacent to the Cr mask. The SiO2 directly under the Cr remains at its original thickness (e.g., 500 nm), while the exposed SiO2 is etched to a reduced thickness (e.g., 200 nm) to create regions with different surface energy characteristics for manipulating fluid flow and droplet behavior within the microfluidic channels.
  d) Forming insulating sidewalls: Subsequent deposition of a parylene layer encapsulates the etched SiO2 structures, forming the walls of the microfluidic channels.

graph TD
    A[Glass Substrate] --> B{PECVD SiO2 Deposition};
    B --> C{Cr Masking Layer Formation};
    C --> D{Wet Etch of SiO2 (Patterned Surface Energy)};
    D --> E{Parylene Channel Wall Formation};
    E --> F[Lab-on-a-Chip Microfluidic Device];

---

4. Integration with Emerging Technologies

Derivative 8.10: AI-Driven Adaptive Etch Process for Heterogeneous Integration

• Enabling Description:
  a) Forming a high dielectric constant film: ALD HfSiON film on a heterogeneous substrate (e.g., Si-Ge).
  b) Forming a gate electrode: Metal gate (e.g., W).
  c) Etching the HDK film: An AI-driven adaptive RIE process is employed. Real-time optical emission spectroscopy (OES) and interferometry provide feedback to an AI model, which dynamically adjusts plasma power, gas flow, and etch time. This allows for precise, on-the-fly correction of etch rates across different material regions or wafer non-uniformities, ensuring a consistent and optimized thickness reduction (e.g., 65% reduction) of the HfSiON external to the gate electrode, critical for heterogeneous integration where material properties can vary.
  d) Forming insulating sidewall: Standard SiN sidewalls.

sequenceDiagram
    participant AI as AI Control System
    participant OES_Sensor as OES/Interferometry Sensor
    participant RIE_Tool as RIE Etching Tool
    participant Wafer as Wafer (HDK Film)

    loop Adaptive Etch Cycle
        RIE_Tool->Wafer: Initiate Etch Step
        Wafer->OES_Sensor: Emit Optical/Interference Data
        OES_Sensor->AI: Send Real-time Process Data
        AI->AI: Analyze, Predict Etch Deviation
        AI->RIE_Tool: Adjust Etch Parameters (Power, Gas, Time)
        RIE_Tool->Wafer: Apply Adjusted Etch
    end
    RIE_Tool->Wafer: Complete Etch

Derivative 8.11: IoT-Monitored Fabrication Line for Predictive Maintenance

• Enabling Description:
  a) Forming a high dielectric constant film: Automated ALD HfO2 deposition.
  b) Forming a gate electrode: Automated polysilicon gate patterning.
  c) Etching the HDK film: IoT sensors integrated into the dry etching chamber (e.g., pressure transducers, gas flow meters, temperature sensors) continuously stream environmental and process parameters to a central IoT platform. This data is analyzed for anomalies or drifts indicating potential equipment malfunction or process deviations that could impact the HDK film thickness reduction. The platform triggers predictive maintenance alerts before critical failures occur, ensuring consistent etching quality (e.g., 70% thickness reduction) and minimizing downtime.
  d) Forming insulating sidewall: Automated PECVD SiN sidewall formation.

graph TD
    subgraph IoT-Enabled Fabrication
        A[ALD HfO2] --> B(IoT Sensors);
        B --> C[IoT Platform];
        C --> D{Data Analysis (ML)};
        D --> E{Predictive Maintenance Alert};
        E --> F[RIE Etch of HDK];
        F --> G[PECVD SiN];
    end

    F -- Monitored by --> B;

Derivative 8.12: Blockchain for Secure Process Traceability and IP Protection

• Enabling Description:
  a) Forming a high dielectric constant film: Proprietary Hf-based high-k film is deposited. Upon completion, a hash of all equipment settings, material batch IDs, and operator IDs is committed to a permissioned blockchain.
  b) Forming a gate electrode: Metal gate formation. Hash of process parameters committed to blockchain.
  c) Etching the HDK film: The specific etch recipe, etch time, gas composition, and final measured thickness reduction (e.g., 60%) of the HDK film are digitally signed and hashed onto the blockchain. This provides an unalterable audit trail, critical for intellectual property protection and ensuring that only authorized and validated processes are used, preventing illicit modification or replication of the manufacturing method.
  d) Forming insulating sidewall: SiN sidewall. Hash of process parameters committed to blockchain.

sequenceDiagram
    participant FabricationStep as "Fab Step: HDK Deposition"
    participant Measurement as "Metrology: Thickness"
    participant Blockchain as "Blockchain Ledger"
    participant EtchStep as "Fab Step: HDK Etch"
    participant SidewallStep as "Fab Step: Sidewall Form"

    FabricationStep->Measurement: Complete
    Measurement->Blockchain: Commit (HDK_Dep_Hash)
    EtchStep->Measurement: Complete
    Measurement->Blockchain: Commit (HDK_Etch_Hash)
    SidewallStep->Measurement: Complete
    Measurement->Blockchain: Commit (Sidewall_Form_Hash)

---

5. The "Inverse" or Failure Mode

Derivative 8.13: Controlled Undermining Etch for Deliberate Device Disablement

• Enabling Description:
  a) Forming a high dielectric constant film: Standard HfSiON deposition.
  b) Forming a gate electrode: Standard polysilicon gate.
  c) Etching the HDK film: After initial thickness reduction, a secondary, isotropic wet etch step is introduced. This etch is designed to intentionally undermine the gate electrode by laterally etching the now-thinner HDK film from under the sidewall. This precisely controlled undermining, leading to a localized, deliberate thinning or removal of the HDK at the gate edge, results in a pre-programmed failure point that can be activated (e.g., via a fuse) to disable the device remotely or upon detection of tampering, ensuring secure operation or preventing unauthorized use.
  d) Forming insulating sidewall: Standard SiO2 sidewall.

graph TD
    A[HDK Film] --> B{Gate Electrode};
    B --> C{Initial Anisotropic Etch (Thins HDK)};
    C --> D{Secondary Isotropic Wet Etch (Undermine)};
    D --> E{Controlled HDK Removal at Gate Edge};
    E --> F[Deliberate Device Disablement];

Derivative 8.14: Low-Yield, High-Safety Fabrication for Critical Components

• Enabling Description:
  a) Forming a high dielectric constant film: A thicker-than-normal (e.g., 10 nm) HfO2 film is deposited, sacrificing nominal device performance for increased robustness.
  b) Forming a gate electrode: Standard TiN gate.
  c) Etching the HDK film: The etching process is deliberately slowed down and conducted with redundant in-situ monitoring (e.g., multiple endpoint detectors). The target thickness reduction is conservative (e.g., 20% reduction), leaving a still-robust 8 nm HDK film under the sidewall. This low-throughput, high-safety approach prioritizes maximizing the integrity and breakdown voltage of the dielectric, accepting a lower fabrication yield and potentially lower peak performance to ensure unparalleled reliability for applications like medical implants or automotive safety systems.
  d) Forming insulating sidewall: Extra-thick SiN sidewalls.

stateDiagram
    direction LR
    InitialHDKDep : HfO2 Deposition (10nm)
    GateFormation : TiN Gate
    SlowEtch : Slow, Monitored Etch (Target: 20% reduction)
    RobustHDK : Robust HDK (8nm) under Sidewall
    ThickSidewall : Extra-thick SiN Sidewalls
    HighSafety : Prioritize Safety over Yield
    AcceptLowPerformance : Accept Lower Performance

    InitialHDKDep --> GateFormation
    GateFormation --> SlowEtch
    SlowEtch --> RobustHDK
    RobustHDK --> ThickSidewall
    ThickSidewall --> HighSafety
    HighSafety --> AcceptLowPerformance

Derivative 8.15: Adaptive Etch for "Safe Mode" Functionality on Substrate Defects

• Enabling Description:
  a) Forming a high dielectric constant film: Standard HfSiON deposition.
  b) Forming a gate electrode: Standard polysilicon gate.
  c) Etching the HDK film: Prior to etching, in-line defect scanning identifies localized substrate imperfections (e.g., crystal defects). The etching process is then adaptively modified based on this defect map. In areas with identified defects, the thickness reduction of the HDK film external to the gate electrode is less aggressive (e.g., 30% reduction vs. 50% elsewhere), leaving a thicker, more robust dielectric layer (e.g., 3.5 nm vs. 2.5 nm). This intentionally compromises optimal performance in defect-prone areas but ensures that the device can still operate in a "safe mode" rather than failing entirely, improving overall product reliability even on imperfect substrates.
  d) Forming insulating sidewall: Standard SiO2 sidewall.

graph TD
    A[Substrate + Active Region] --> B{In-line Defect Scan};
    B -- Defect Map --> C{HDK Film Deposition};
    C --> D{Polysilicon Gate Formation};
    D --> E{Adaptive Etch of HDK Film (Defect-aware)};
    E -- If Defect Present --> F1{Less Aggressive Etch (Thicker HDK)};
    E -- If No Defect --> F2{Normal Etch (Thinner HDK)};
    F1 --> G[Safe Mode Functionality];
    F2 --> H[Optimized Performance];
    G --> I{SiO2 Sidewall Formation};
    H --> I;

---

Combination Prior Art Scenarios

1. US7923764 combined with Open-Source Flexible Electronics Manufacturing Standards (e.g., OE-A Roadmap for flexible substrates and processes):
   The semiconductor device structure of US7923764, particularly a MISFET with a high-k gate insulating film having a continuously varying thickness under the gate and sidewall, can be readily combined with existing open-source manufacturing standards for flexible electronics. Specifically, the principles of depositing the high-k gate dielectric (e.g., HfO2 or ZrO2) and forming the gate electrode (e.g., ITO or CNT) on flexible polymer substrates (e.g., PEN, PI) as outlined in the OE-A (Organic and Printed Electronics Association) Roadmap are well-established. The methods described in US7923764 for selectively etching the high-k film to achieve a thinner region under the sidewall can be adapted for roll-to-roll processing or large-area flexible circuits, to optimize charge transfer characteristics and reduce parasitic capacitance in mechanically flexible FETs. Such integration is a straightforward application of known high-k integration techniques onto flexible platforms.

2. US7923764 combined with Open-Source EDA Toolchains for 3D IC Design (e.g., OpenROAD Project):
   The fabrication method of US7923764, which involves precise control over high-k dielectric thickness under gate electrodes and sidewalls, can be directly applied and optimized using open-source Electronic Design Automation (EDA) toolchains for 3D Integrated Circuits (3D ICs), such as those developed by the OpenROAD Project. These toolchains often include modules for advanced lithography, etching simulation, and process variation awareness for vertical stacking and through-silicon vias (TSVs). Adapting the method claims of US7923764 to these tools would involve simulating the etching profiles of high-k dielectrics around stacked gates and TSVs. The ability to create variable-thickness high-k films would be beneficial for managing inter-layer capacitance and thermal dissipation in 3D stacked devices, an obvious extension to existing 3D IC manufacturing flows supported by open-source platforms.

3. US7923764 combined with Open-Source Neuromorphic Hardware Architectures (e.g., Loihi or similar open-source inspired designs):
   The semiconductor device structure, particularly the use of high dielectric constant gate insulating films with tailored thickness profiles, can be adapted for use in neuromorphic computing architectures that utilize open-source hardware designs (e.g., inspired by Intel's Loihi or other open-source research platforms for memristive devices). In neuromorphic circuits, the properties of the gate dielectric (e.g., charge trapping, defect engineering) can be exploited to mimic synaptic plasticity or memory effects. The concept of a high-k gate insulating film having a smaller thickness under the sidewall can be directly applied to optimize the electric field distribution for memristor devices or to create distinct 'learning' and 'read-out' regions within a single transistor structure, leveraging the differential dielectric properties. This combination is a natural progression of utilizing advanced transistor structures in emerging computing paradigms.