US 11386024

I'll search for authoritative information on US 11386024, including any 2026 litigation activity.

Let me verify the current legal status of this patent, which appears to have changed significantly.

US Patent 11,386,024 — Analyst Summary

Important caveat up front: the substantive content below is grounded in the authoritative full text of the patent you supplied. The legal-status information is from live search results. Note that this patent's status has changed materially since issuance — see §5.

1. Bibliographic data

Continuation chain (from the patent's own Cross-Reference section): this patent is a continuation of 15/857,553 (filed 2017-12-28), itself a continuation of 15/088,115 (2016-04-01, now US 9,858,218), a continuation of 13/942,721 (2013-07-16, now US 9,311,116), a continuation of 12/815,339 (2010-06-14, now US 8,489,837), which claims benefit of provisional 61/186,799 (2009-06-12). US 11,880,319 and application 18/413,017 claim benefit of this patent.

2. Abstract (as printed)

According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.

3. Plain-language overview of the independent claims

(a) Claim 1 — the memory module

The module has a PCB whose edge connections fit a host slot and are grouped into first edge connections (address/control), second edge connections (data), and a separate third error edge connection. A module controller on the PCB receives the address/control signals on the first edge connections; DRAM elements on the PCB exchange data over the second edge connections based on those signals. The recited novelty is in the module controller's transistor: its open drain is tied to the error edge connection, its source is tied to ground, and the module controller drives its gate. Driving the gate with a first signal reports a parity error during a normal read/write access; driving the gate with a second signal conveys information about training sequences, at a time when the DRAMs are not being accessed for any normal read/write operation. In substance: one JEDEC-style error/ERROUT pin, one open-drain transistor, two time-multiplexed signaling functions (error reporting vs. initialization/training handshake).

(b) Claim 10 — the method

A method of operation in a host system with a memory controller, performed at the memory module (same PCB / edge-connection / open-drain-transistor structure as claim 1): the module controller receives address/control signals for normal read/write operations on the first edge connections; the DRAM elements input/output the corresponding data over the second edge connections; a first gate signal is applied to indicate a parity error occurring during a normal read/write operation; and training operations are performed, with a second gate signal applied to the gate of the same transistor in connection with those training operations. (The claim text available to me is truncated mid-limitation [10.j]; the full closing limitation, including the "not accessed for any normal read or write operations" negative limitation, is not reproduced in the source text I have. See the uncertainty note in §6.)

(c) Claim 19 — the memory module

Another memory module claim with the same "operable with a memory controller of a host system" preamble and the same PCB/edge-connection/transistor architecture, but with additional limitations folded in (drawn from the dependent set): the first signal drives the gate high to create a low-impedance path between the error edge connection and ground; and the second signal drives the gate high to drive the error edge connection to a low-impedance state and drives the gate low to drive it to a high-impedance state. In plain terms, it hard-codes the specific open-drain drive behavior (assert-low / release-to-Hi-Z) rather than just the dual-function concept.

Dependent claims 2–9 / 11–18 / 20 add: state transitions between low logic level and high-impedance (2, 3, 11); gate-high = low logic level / gate-low = Hi-Z (4, 12); gate-high = low-impedance path to ground for the parity-error signal (5, 13); the transistor being part of an integrated circuit (6, 14); the negative limitations that training occurs while the DRAMs are not communicating normal read/write data and the second edge connections are inactive (7, 8, 16, 17); and a multiplexor/logic circuit at the gate that selects between the parity-error input and the training input (9, 18).

4. Disclosure context (specification)

The specification frames the problem as the absence of any handshaking between the MCH (memory controller hub) and a memory subsystem during initialization in LR-DIMM configurations where the MCH hands off training to the module's local controller. It critiques (i) fixed predetermined wait periods (blind execution) and (ii) SMBus register polling as inefficient, and advocates the notifying approach. It identifies the JEDEC-specified error-out pin as the ideal vehicle because its behavior is undefined during initialization and it can be asserted by the module independently of controller requests. FIG. 2 shows open-drain transistors (36, 38) on two modules wired to a shared bus 32 with the memory controller's internal pull-up 40, so the bus is released only when all modules finish. FIG. 3 shows a multiplexor 42 selecting between a task_in_progress signal 44 and an error signal 46 depending on initialization vs. operational mode.

5. Current legal status — materially changed since issuance

This is the most consequential finding from the docket search, and it is not evident from the patent document itself:

• All 20 claims have been statutorily disclaimed. Netlist, Inc. filed a disclaimer under 37 C.F.R. § 1.321(a) on 2025-08-06 (signed /Jamie J. Zheng/), disclaiming "the following complete claim(s) … 1‑20" — i.e., the entire claim set. The disclaimer is binding on the patentee and its successors/assigns.
• PTAB adverse judgment. In IPR2025‑00001, Samsung Electronics Co., Ltd. v. Netlist, Inc. (filed 2024‑10‑08; institution granted 2025‑05‑15; Director Review denied 2025‑07‑17), Netlist requested adverse judgment under 37 C.F.R. § 42.73(b) on 2025‑08‑07 based on that disclaimer. The Board granted the adverse judgment on 2025‑09‑08. Case status is "Terminated – Adverse Judgment." Netlist stated the disclaimer was filed "merely to avoid additional costs … and without any admission as to the propriety of any statement in the Petition."
• Grounds asserted in the IPR (for context): obviousness over (1) Hazelzet (US 2008/0098277) + JEDEC Proposal 142.35, (2) Hazelzet + Buchmann (US 8,139,430), (3) Hazelzet/Wang (US 8,386,722) variants, and (4)–(6) those combinations further in view of Kim (US 8,359,521). Samsung also argued collateral estoppel from prior final written decisions against Netlist's '623, '218 and '595 patents, whose claims were cancelled by IPR certificates.
• District court: Samsung Electronics Co., Ltd. v. Netlist, Inc., No. 1:23‑cv‑01122 (D. Del.), a declaratory-judgment action on the '024 patent filed 2023‑10‑09 (Netlist's Rule 12(b)(1)/(6) motion denied 2025‑03‑04); consolidated with No. 1:24‑cv‑00614. Netlist moved to stay on 2025‑06‑13; the stay was granted 2025‑08‑01. Per Netlist's Form 10‑Q (filed 2026‑03‑28), the consolidated action was closed on 2026‑06‑17 after the parties dismissed all pending claims and counterclaims.
• CAFC 2026: I found no Federal Circuit appeal specific to US 11,386,024 in the 2026 docket. The September 2, 2026 Netlist Federal Circuit decisions (24‑1707 Netlist v. Micron, precedential; 24‑1859/24‑1863 Netlist v. Samsung, nonprecedential) concern US 10,949,339, 11,016,918, 11,232,054, 13,060 and 13,160 — not the '024 patent. Any suggestion that '024 was addressed in those 2026 opinions would be incorrect.
• Google Patents' legal-status field still reads "Active," and the IPR banner listed on that page shows "PTAB case IPR2025‑00001 filed (Adverse Judgment)." The "Active" label reflects fee/maintenance status and does not reflect the disclaimers; for practical purposes no enforceable claims of the '024 patent remain.

6. Uncertainty notes

• Claim 10's full text: the claim listing in the source I have is truncated mid-limitation ("performing training operat…"). I therefore cannot quote its closing limitation verbatim. Claims 1, 10 and 19 are the independent claims (consistent with Samsung's complaint, which identifies ¶105 independent claims 1, 10 and 19, and with the IPR petition's negative-limitation grouping of "claims 1, 10, 19"). I have described claim 10's substance only to the point the text supports.
• Priority date discrepancy: the patent itself and Google Patents state 2009‑06‑12; the Unified Patents portal lists 2009‑06‑11, and its application/grant dates (2019‑11‑10, 2022‑07‑11) are one day earlier than the patent's official dates (2019‑11‑11, 2022‑07‑12). I treat the one-day differences as time-zone/Tool-record artifacts and use the patent's own dates, but flag them since I was instructed to interpret identifiers literally.
• Claim 19's structure: my reading that claim 19 is claim 1 plus the claim 4/5 limitations is inferred from the IPR petition exhibit mapping elements [19.f] and [19.g] to claims 5 and 4 respectively; I did not see the verbatim issued text of claim 19.
• Alternative prior-art reading: one third-party summary (ai-lab.exparte.com) labels the '024 patent's title as "Memory Module with Handshake Mechanism" and describes the JEDEC reference as a "December 2009 LRDIMM Memory Initialization Proposal," which appears to conflict with the 2009‑06‑12 priority date and with the patent's own title. I have used the patent's title and treated that third-party title as an error by that source.

I'll research litigation involving US patent 11386024. Let me search multiple sources.

Excellent findings. Let me dig deeper into specific cases.

Let me verify the IPR outcome and check for any additional cases.

Litigation Involving U.S. Patent No. 11,386,024 ("the '024 patent")

Patent: U.S. 11,386,024 B2 — "Memory Module Having an Open-Drain Output for Parity Error and for Training Sequences"
Assignee/Owner: Netlist, Inc. (Irvine, CA)
Inventors: Hyun Lee · App. No. 16/680,060 · Filed: Nov. 11, 2019 · Granted: July 12, 2022
Priority: June 12, 2009 (per Google Patents; Unified Patents lists 2009-06-11) — continuation of U.S. 15/857,553 → 15/088,115 (US 9,858,218) → 13/942,721 (US 9,311,116) → 12/815,339 (US 8,489,837) → provisional 61/186,799.
Note: The '024 patent is a continuation of the '218 and '595 patents (U.S. 9,858,218 and 10,474,595), which Netlist has asserted against Samsung in Samsung Elecs. Co., Ltd. v. Netlist, Inc., No. 21-1453-JLH (D. Del.).

Below are the proceedings I could verify that specifically identify the '024 patent. I did not locate any case in which Netlist asserted the '024 patent as the primary patent-in-suit in a district-court infringement complaint; its appearances are in a Samsung declaratory-judgment action and a Samsung-filed IPR.

1. Samsung Electronics Co., Ltd., Samsung Semiconductor, Inc. & Samsung Electronics America, Inc. v. Netlist, Inc.

Declaratory Judgment of Non-Infringement + Breach of Contract (RAND)

Sources: D. Del. Memorandum Order, Samsung v. Netlist, C.A. No. 23-1122-JLH (https://www.ded.uscourts.gov/sites/ded/files/opinions/23-1122.pdf); Netlist SEC Form 10-K dated Dec. 27, 2025 (https://www.sec.gov/Archives/edgar/data/[1282631](/patent/1282631)/000110465926032152/nlst-20251227x10k.htm) and Form 10-Q dated Mar. 28, 2026 (https://www.sec.gov/Archives/edgar/data/1282631/000110465926059350/nlst-20260328x10q.htm).

Related:

• Consolidated case 1:24-cv-00614 (D. Del.) — another Samsung declaratory-judgment action, consolidated with 1:23-cv-01122 on July 8, 2025. (I could not fully confirm which patent(s) are at issue in 1:24-cv-00614, but the SEC disclosure ties the '319 patent to a companion stay motion and IPR2025-00002.)
• In its counterclaims in the Delaware litigation, Netlist reportedly counterclaimed for infringement on the '523, '218, '595, '024, and '319 patents (per Samsung's later complaint, Samsung Elecs. Co. et al. v. Netlist, Inc., filed Apr. 9, 2026, ¶ 133).

2. Samsung Electronics Co., Ltd. v. Netlist, Inc. — IPR2025-00001 (PTAB)

Inter Partes Review of the '024 patent

Sources: PTAB petition documents (https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556759](/patent/1556759)/download-documents); IPVerse case page (https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2025-00001); Docket Alarm PTAB docket (https://www.docketalarm.com/search/PTAB/dockets/...); Google Patents (https://patents.google.com/patent/[US11386024](/patent/US11386024)/en).

The petition's prior-art citations confirm the '024 patent was challenged by Samsung as part of the same Samsung–Netlist memory-patent campaign, and the pre-existing invalidation/estoppel record the petition discusses (e.g., the '218 and '595 patents) provides broader context.

Cases You May See Cited but That Do NOT Involve the '024 Patent

To avoid conflating similar numbers, note that the following frequently-cited Netlist cases do not list the '024 patent as an asserted patent:

• Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:22-cv-00293-JRG (E.D. Tex.) — the $118M Nov. 2024 willfulness verdict. Asserted patents were U.S. 7,619,912; 11,093,417; and 10,268,608 (the '215 patent was dropped). Not the '024 patent.
• Netlist, Inc. v. Samsung Elecs. Co., Ltd. et al., No. 2:21-cv-00463-JRG (E.D. Tex.) — the $303M Apr. 2023 verdict; also not the '024 patent.
• Samsung Elecs. Co., Ltd. v. Netlist, Inc., No. 21-cv-1453-JLH (D. Del.) — asserts the '218 and '595 patents (the '024's parents); the '024 itself is only the subject of Samsung's DJ case above.
• ITC Inv. Nos. 337-TA-1523 / the Sept. 2026 Netlist ITC complaint — asserts '731, '523, '366, and '407 patents (DRAM/DDR5 DIMMs); the '024 patent is not included in that ITC action.

Summary

There appear to be two proceedings specifically involving U.S. 11,386,024:

1. Samsung v. Netlist, D. Del. No. 1:23-cv-01122 (-JLH) — Samsung DJ of non-infringement + breach of contract, filed Oct. 9, 2023, consolidated with 1:24-cv-00614 and stayed on Aug. 1, 2025 pending IPR; trial currently set Aug. 2, 2027. Netlist counterclaimed for infringement of the '024 patent in the Delaware litigation.
2. Samsung v. Netlist, PTAB IPR2025-00001 — filed Oct. 8, 2024, challenging all claims 1–20 of the '024 patent; reported by aggregators as ending in adverse judgment, with a statutory disclaimer (37 CFR 1.321(a)) on the '024 patent appearing in the record.

Caveats: I did not find (a) any case where the '024 patent is the primary asserted patent in a Netlist-filed infringement complaint; (b) any CAFC appeal docketed specifically on the '024 patent; or (c) any PACER-level confirmation of the exact IPR2025-00001 final outcome. The "adverse judgment" label is from Google Patents' family-litigation data and should be verified against the PTAB Final Written Decision / adverse-judgment paper and the 37 CFR 1.321(a) disclaimer record. The Darts-IP family litigation entry for this family is: https://patents.darts-ip.com/?family=48749188 (linked from Google Patents).

I'll verify the PTAB record for US 11,386,024 with targeted searches before writing anything up.

Key finding: a statutory disclaimer of all claims. Let me dig into the proceeding details and outcomes.

Let me pin down the IPR2025-00001 institution date, termination, and the disclaimer's effect.

PTAB / AIA Trial Proceedings — US 11,386,024 ("Memory module having an open-drain output for parity error and for training sequences", Netlist, Inc.)

Data-integrity flag up front: the structured "PTAB proceedings on file" block states the USPTO ODP API returns no AIA trial proceedings for this patent. That is stale/incorrect. There is at least one AIA trial on the '024 — IPR2025-00001 (Samsung v. Netlist) — which the Board instituted, which Netlist asked the Director to review, and which terminated by adverse judgment on 2025-09-08 after Netlist statutorily disclaimed all 20 claims. The Google Patents page for this patent itself carries the "PTAB case IPR2025-00001 filed (Adverse Judgment)" litigation tag. Do not rely on the ODP-absence signal for this patent.

Proceedings overview

There is 1 AIA trial proceeding on US 11,386,024 (IPR2025-00001), plus 1 coordinated companion IPR on the sibling continuation US 11,880,319 (IPR2025-00002) resolved identically on the same day; status breakdown: active 0 · claims invalidated by the Board 0 · claims sustained 0 · settled 0 · institution denied 0 · instituted-then-terminated by adverse judgment 1 (all 20 claims canceled by the patentee's own statutory disclaimer). Bottom-line defensive posture: the patent is not merely narrowed, it is gone — Netlist statutorily disclaimed claims 1–20 of the '024 on 2025-08-06, and the Board entered adverse judgment on 2025-09-08. Any demand letter, complaint, or ITC assertion premised on the '024 is now baseless. The one caveat a defendant must not miss: because no Final Written Decision ever issued, there is no Board adjudication of unpatentability and no § 315(e)(2) statutory estoppel — the kill was the patentee's own act, not a merits win.

IPR2025-00001 — Samsung Electronics Co., Ltd. v. Netlist, Inc.

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2024-10-08 (Petition for IPR of US 11,386,024; PTAB docket and IP Verse both show 2024-10-08, matching Ex. 1001 captioning. Note: a Netlist SEC Form 10-Q describes the '024 petition as filed 2024-10-18 — a one-line inconsistency in the patent owner's own disclosure; the docket date controls.)
• Status: Terminated – Adverse Judgment (verbatim from PTAB docket). Plain English: Netlist disclaimed every claim, mooted the trial, and the Board entered judgment against it under 37 C.F.R. § 42.73(b). The case never reached a Final Written Decision.
• Judge panel: Norman H. Beamer, Sheila F. McShane, Kara L. Szpondowski (Administrative Patent Judges). The same panel sat on IPR2025-00002.
• Petition grounds: Challenged claims 1–20 (all claims). Six grounds, all § 103 obviousness, built on four primary references and one additive reference:
  • Grounds 1–3 — Hazelzet (US 2008/0098277 A1, open-drain "UE" error pin on an RDIMM) in view of, alternatively, JEDEC (JEDEC Proposal 142.35, the December 2009 LRDIMM memory-initialization proposal — Ex. 1015), Buchmann (US 8,139,430, SBC-mode training with a "TS_done" notification), or Wang (application 12/144,396; US 8,386,722).
  • Grounds 4–6 — the Grounds 1–3 combinations further in view of Kim (US 8,359,521, OR-gating multiple status signals onto a shared ERROR# open-drain pin) — aimed squarely at the multiplexor/logic-circuit limitations of claim 9.
  • § 112 as a predicate, not a ground: the petition led with written-description defects ("unsupported negative limitation" for claims 1, 10, 19; 7 and 16; 8 and 17) to argue the effective filing date is no earlier than 2010-06-14, so the December 2009 JEDEC proposal qualifies as prior art notwithstanding the '024's 2009-06-12 provisional priority claim.
• Institution decision: Instituted 2025-05-15 (Paper 17), on all six grounds. Reasoning, in substance: (i) the Board credited Petitioner's framing that the December 2009 JEDEC proposal is a printed publication / admitted prior art, and directed the parties to the narrow accessibility issues (e.g., who could join JEDEC); (ii) the Board gave weight to the fact that Netlist had filed a terminal disclaimer for the '024 over the '595 and '218 patents, calling it "a strong clue that a patent examiner, and, by concession, the applicant, thought the claims in the continuation lacked a patentable distinction over the parent" (IPR2025-00001, Paper 17 at 19, 22), and concluding that "the differences between the claims in the '024 patent and the '623, '218, and '525 patents do not appear to materially alter the question of invalidity" (Paper 17 at 22). Roughly put: the '024 was, on the Board's preliminary view, a repackaging of claims already canceled in earlier Netlist IPRs. Samsung's later litigation pleadings characterize the institution decision as also resting on collateral estoppel; treat that as party characterization of the '024 ruling — the explicit collateral-estoppel finding of record ("collaterally estopped as to the challenges involved in the Petition, i.e., obviousness of claims 1-20") is in the '319 institution decision (IPR2025-00002, Paper 17 at 23).
• Final Written Decision: None. Never issued. This is the single most important fact about this proceeding. No claim of the '024 was held unpatentable by the Board, and no claim was held patentable by the Board. The claims were canceled by the patentee's statutory disclaimer, not by adjudication.
• Settlement / termination: Not a settlement. On 2025-08-06 Netlist filed a statutory disclaimer under 37 C.F.R. § 1.321(a) disclaiming "the following complete claim(s) in the above-identified patent: 1-20" of US 11,386,024 (signed by Netlist's attorney /Jamie J. Zheng/, 2025-08-06; patent owner 100%). On 2025-08-07 Netlist filed a Patent Owner's Request for Adverse Judgment under 37 C.F.R. § 42.73(b), arguing that because it "has no remaining claims in this inter partes review," adverse judgment should be entered — while expressly stating the disclaimer was filed "merely to avoid additional costs associated with continuing trial in this inter partes review proceeding and without any admission as to the propriety of any statement in the Petition, Institution Decision, or any other pleading." The Board entered adverse judgment on 2025-09-08. The terms of the underlying commercial dispute are not public and the disclaimer carries no admission; nothing here was "confidential settlement" in the ordinary sense — the operative act is on the public record.
• Director Review: Netlist requested Director Review of the institution decisions on 2025-05-29; the requests in both IPR2025-00001 and IPR2025-00002 were considered together and denied — Netlist's SEC filings date the denial to 2025-07-17 ("Having reviewed the requests and responses, it is: ORDERED that the requests for Director Review are denied."). Netlist's arguments (waste of Board resources, voluminous record, JEDEC accessibility) were rejected; the denial order was accompanied by an authorized Petitioner response arguing the JEDEC accessibility question is a simple, non-technical legal issue and that efficiencies exist in deciding the parallel IPRs together.
• Appeal: None identified. With no FWD, there was no Board decision for Netlist to appeal to the Federal Circuit; the adverse judgment rests on the patentee's disclaimer. (Contrast: Netlist's docket shows it does appeal adverse decisions elsewhere, e.g., the appeal of IPR2023-00847 on the '608 patent, Fed. Cir. No. 25-1378.) I found no CAFC docket for the '024.
• Defensive value: Claim 1 — and every other claim of the '024 — was canceled by Netlist's own statutory disclaimer, treated as though it never existed. Any infringement theory built on the '024 is dead on arrival; a defendant's motion to dismiss or for summary judgment writes itself, and continued assertion of the '024 after 2025-08-06 is sanction-bait. The offsetting caveat: because no FWD issued, there is no § 315(e)(2) estoppel and no precedential invalidity ruling to borrow. You do not get the benefit of a merits win — you get something better (no claims) with less procedural baggage.

Related coordinated proceeding (NOT on the '024 — flagged for context)

IPR2025-00002 — Samsung Electronics Co., Ltd. v. Netlist, Inc. (US 11,880,319)

• Type: Inter Partes Review — on the sibling continuation US 11,880,319 ("Memory subsystem with an open drain output for communicating during an initialization operation"), which claims priority through the same family (2009-06-12 provisional 61/186,799). Included because it was instituted, Director-Review-denied, and disclaimed in lockstep with the '024 IPR, and the two share a panel and a record.
• Filed: 2024-10-24.
• Status: Terminated – Adverse Judgment (PTAB docket; "Outcome: Unpatentable" in third-party databases is a database gloss, not an FWD — no FWD exists).
• Judge panel: Norman H. Beamer (joined by Sheila F. McShane and Kara L. Szpondowski) — same panel as the '024 proceeding.
• Petition grounds: Claims 1–20, § 103 — Hazelzet + JEDEC / Buchmann / Wang, plus Kim; substantively the same art and substantially the same expert declaration as the '024 petition.
• Institution decision: Instituted 2025-05-15 (Paper 17). The Board found Patent Owner collaterally estopped, holding that "prior IPRs had already litigated and decided the same art combinations," that the issue was "identical, necessarily adjudicated, and fully contested," and therefore "Netlist [is] estopped from relitigating the obviousness of claims 1-20 of the '319 patent." The Board also found "the differences between the claims in the '319 patent and the '623, '218, and '525 patents do not appear to materially alter the question of invalidity" (Paper 17 at 23).
• Final Written Decision: None. Never issued.
• Termination: Netlist statutorily disclaimed claims 1–20 of the '319 on 2025-08-06 (same day as the '024 disclaimer), requested adverse judgment on 2025-08-07, and the Board entered adverse judgment on 2025-09-08.
• Appeal: None identified.
• Defensive value: Reinforces that Netlist's exit strategy for this patent family was disclaimer, not defense. If a defendant sees the '024 in a chart, expect the same-family '319 and check for a disclaimed-status confirmation before responding.

Strategic summary

Claim status — CANCELED vs. SUSTAINED vs. UNTESTED. There is no "sustained" and no "untested" bucket for the '024: all 20 claims (1–20) were statutorily disclaimed by Netlist on 2025-08-06 and are treated as if they never existed. Claims 1–20 are also the entire claim set (the patent issued with 20 claims). The precise legal posture matters: the claims were not held unpatentable by the Board — there was no FWD in IPR2025-00001 — so a defendant should plead "all claims canceled/ disclaimed; no claim remains to be asserted" (35 U.S.C. § 253; 37 C.F.R. § 1.321), not "claims held invalid." Pleading "the PTAB invalidated the claims" would be inaccurate and easily shown inaccurate.

Estoppel landscape — and the trap. Because IPR2025-00001 terminated by adverse judgment before any Final Written Decision, § 315(e)(2) IPR estoppel does not attach to Samsung (the statute keys estoppel to "the final written decision"). So Samsung, and any privies, are not statutorily barred from raising Hazelzet/JEDEC/Buchmann/Wang/Kim in the district court or the ITC — but that is academic, since there are no claims left to invalidate. The meaningful asymmetry runs the other way: 37 C.F.R. § 42.73(d)(3)(i) precludes the patent owner from "taking action inconsistent with the adverse judgment, including obtaining in any patent … a claim that is not patentably distinct from a finally refused or canceled claim." For a defendant, that is an affirmative weapon against any new continuation claims Netlist might try to prosecute off this specification: the prosecution history now contains (a) an examiner-driven terminal disclaimer over the '595/'218 patents, and (b) an adverse judgment canceling claims 1–20 — together a strong obviousness-type double-patenting and § 42.73(d)(3) record. Press that in any new-family prosecution or DJ.

Pattern signals. This is a repeat-player campaign, not a one-off. Samsung filed the two IPRs as a coordinated pair (IPR2025-00001 on the '024; IPR2025-00002 on the '319); the same panel sat on both; Director Review of both was denied in a single order. The Board's own institution reasoning tied the '024 to prior Final Written Decisions in the '623, '218, and '525 patents and to an earlier terminal disclaimer over the '595 and '218 patents — i.e., the Board viewed the '024 as a continuation-patent re-run of claims already canceled. Earlier Netlist memory-module patents in this chain saw FWDs in proceedings including IPR2017-00548 ('837, SK hynix), IPR2018-00303 ('623), and IPR2022-00064 / related filings ('218, '595). No defensive aggregator is the petitioner here — the petitioner is Samsung (Litigation tag: Delaware DJ action 1:23-cv-01122, filed 2023-10-09, seeking a declaration of non-infringement of the '024). The parallel litigation was stayed on 2025-08-01 pending the two IPRs' FWDs and then, per Netlist's 10-Q, the consolidated Delaware action was closed on 2026-06-17 after the parties dismissed all pending claims and counterclaims — consistent with a disclaimed patent having nothing left to litigate.

Recommended next steps

1. If you are a defendant and a demand letter or complaint cites the '024, the answer is one paragraph: no claims exist. Link and quote the operative documents: (a) Netlist's Statutory Disclaimer under 37 C.F.R. § 1.321(a), executed 2025-08-06, disclaiming "the following complete claim(s) in the above-identified patent: 1-20" — filed in IPR2025-00001 and available via PTAB E2E / PTACTS (https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556759](/patent/1556759)/download-documents?artifactId=Cbtw6axCCuTyKVy0E0Z-GXd1zBTiDqATeLdekU_duMs4O8WdHevWzHg); (b) Patent Owner's Request for Adverse Judgment Under 37 C.F.R. § 42.73(b), dated 2025-08-07 (https://ptacts.uspto.gov/ptacts/public-informations/petitions/1556759/download-documents?artifactId=6IEQE8MoNXNgh3Gx6kAdhw8Rtdu7f6awr8V8LjWrt1uzcXdbLQusjY0); and (c) the Board's adverse judgment entered 2025-09-08, docketed as "Terminated – Adverse Judgment" (case page: https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2025-00001). Note that Netlist expressly disclaimed "without any admission" — do not over-argue the file history as an admission of invalidity.
2. No active proceeding, so no trial milestones to track. The statutory 1-year FWD clock from institution (2025-05-15) would have run to ~2026-05-15, but the case terminated 2025-09-08. Verify current status directly on PTAB E2E before any filing; the ODP-derived list supplied in this task is stale and should not be cited.
3. Sweep the family and any live continuations. The '024's parent chain ('837 → '116 → '218 → '024) has already seen cancellations and disclaimers, and the Google Patents family record shows a further continuation track (US 2024/0232105 A1, priority to US 18/413,017). Before conceding that the family is harmless, confirm the disclaimed status of US 11,880,319 and check whether any newly issued continuation claim is patentably distinct from the canceled '024/'319 claims — if not, invoke 37 C.F.R. § 42.73(d)(3)(i) and obviousness-type double patenting, and link the '024 and '319 adverse judgments.
4. Correct the record internally. Whoever is relying on the "no PTAB activity" signal should be told: for this patent the absence is a data artifact, and the true signal is stronger — a patent owner that disclaimed every claim of the '024 and the '319 on the same day is not a patent owner with a case under this family.

Sourcing note / confidence: the petition, grounds, exhibit lists, Panel composition, institution date (2025-05-15), Director Review denial, the 2025-08-06 disclaimer, the 2025-08-07 adverse-judgment request, and the 2025-09-08 adverse judgment are corroborated across PTAB docket data (IP Verse, DockteAlarm/GAE Flex docket), the filed PTAB papers themselves, Banner Witcoff's PTAB Highlights (IPR2025-00002, Paper 17, 2025-05-15), and Netlist's SEC Form 10-Q (filed 2026-03-28). The one item I could not verify from a primary source is the exact date of the Director Review denial order (2025-07-17 per Netlist's 10-Q; the order text itself is undated in the copy retrieved) — treat that date as reported-by-patent-owner rather than docket-confirmed.

I'll research this patent's ownership chain using available sources.

Assignment & Ownership Analysis — US 11,386,024 B2

Patent: US 11,386,024 B2 — "Memory module having an open-drain output for parity error and for training sequences"
App. No. 16/680,060 · filed 2019-11-11 · issued 2022-07-12 · priority 2009-06-12 (Prov. 61/186,799)
Source of record: https://patents.google.com/patent/US11386024/en · Assignment Center: https://assignmentcenter.uspto.gov/

Sourcing caveat (read first): I do not have a live session against assignmentcenter.uspto.gov, so I could not pull the Assignment Abstract of Title for 16/680,060 directly. The entries below are reconstructed from USPTO PTAB exhibits and court filings that reproduce the Assignment Center abstracts, plus SEC filings. Where a primary document quoted a reel/frame I give it; where I could not verify one, I say so rather than inventing it.

Inventors

Unusual patterns flagged:

• Sole-inventor family / inventorship dispute. The entire "Notification-Signal" family (US 8,489,837 → 9,311,116 → 9,858,218 → 11,386,024) names Hyun Lee alone. Samsung's declaratory-judgment complaint (Samsung v. Netlist, filed 2026, D.D.C. 1:26-mc-00032) alleges that Lee attended a JEDEC meeting in Montreal on 2009-06-04 at which Inphi presented "MB Initialization Sequence Item 142.35" and IDT/TI/Montage/Inphi presented on MEMBIST initialization signaling, and that Netlist filed the '799 provisional eight days later (2009-06-12) and "fraudulently portrayed Mr. Lee as the sole inventor." These are allegations, not adjudicated findings — but the 8-day gap between the JEDEC presentation and the provisional is a documented, checkable fact and is the kind of provenance pattern that matters to validity, not ownership.
• No inventor-departure pattern. Unlike a classic pre-fire-sale tell, Lee did not leave. He remains a named inventor on Netlist patents issuing as late as US 12,308,087 (issued 2025-05-20) — evidence of continuity, not abandonment.

Original assignee

Netlist, Inc. — a Delaware corporation, HQ at 51 Discovery, Suite 150, Irvine, CA 92618 (later 3 Goddard, Irvine, CA 92618). Named as assignee on the face of the '024 patent.

• Line of business: design and sale of memory subsystems — historically HyperCloud DDR3 modules, NVvault NVDIMMs, Vault/EXPRESSO storage, and currently NVMe SSDs and memory products, largely to hyperscale/enterprise customers. Publicly traded US company (ticker NLST).
• Products embodying the claims: not established. The '024 claims an LRDIMM-class feature (open-drain error pin repurposed as a training/notification handshake driven by a module controller). Netlist asserts the accused implementations are Samsung's, Micron's, Google's and SK hynix's products — not its own. I found no record evidence of a Netlist commercial product practicing claim 1.
• Current status: operating, not in bankruptcy. Recurring going-concern disclosures and a history of secured financings (Silicon Valley Bank; the 2015 SVIC facility; a 2017 TR Global Funding facility). It is simultaneously one of the most active patent plaintiffs in the US — E.D. Tex. verdicts of $303.15M and $118M against Samsung (2023–2024), ongoing Micron and Google actions, and a September 2025 ITC complaint against Samsung and its customers.

Assignment timeline

No assignment of title out of Netlist appears in any record I could retrieve. The recorded items against this portfolio are two security-interest pledge/release pairs (securitization), not conveyances. The inventor→Netlist assignment that put title in the company was executed as part of the original 2010 parent filing (12/815,339); I could not verify the specific reel/frame that covers application 16/680,060.

• 2015-11-18 (executed) / recorded 2015-11-20 — Reel 037150/0897

  • Conveyance: Security Agreement — Intellectual Property Security Agreement ("Netlist – Project Neptune")
  • Assignor/Grantor: Netlist, Inc. (Delaware corporation)
  • Assignee/Secured Party: SVIC No. 28 New Technology Business Investment L.L.P. (Korean limited liability partnership; Samsung Venture Investment affiliate)
  • Correspondent: DLA Piper LLP (US), 4365 Executive Drive, Suite 1100, San Diego, CA 92121 — submitter Troy Zander, contact susan.reynholds@dlapiper.com, attorney docket 350916-9. This is lender's counsel on a single security filing — one appearance, no recurrence across the chain, so it is not a "repeat correspondent" finding.
  • Context: securitization — portfolio-wide pledge expressly covering "improvements, divisions, continuations, renewals, reissues, extensions and continuations-in-part," i.e. after-acquired continuations of the family (which is how a 2019-filed application like 16/680,060 would be captured), executed alongside the 2015 Samsung joint development/license arrangement and Samsung's 3.25% equity stake in Netlist.

• 2017 (executed) — recording and reel/frame NOT VERIFIED

  • Conveyance: Patent Security Agreement (pledge)
  • Assignor/Grantor: Netlist, Inc. Assignee/Grantee: TR Global Funding V, LLC (managed by TR Global Associates V, LLC; TRGP Capital Partners, L.P. as permitted assignee)
  • Correspondent: not determined
  • Context: securitization — a second financing facility. The version reproduced in Netlist's 10-Q is an unfilled form ("as of [●], 2017"), so no firm execution date and no confirmed USPTO recording. Listed for completeness, flagged as unverified.

• 2023-10-27 (recorded) — Reel 065629/[frame NOT VERIFIED]

  • Conveyance: Release of security interest ("Release of Assignment")
  • Assignor: SVIC No. 28 New Technology Business Investment L.L.P. (Samsung-affiliated secured party)
  • Assignee: Netlist, Inc.
  • Correspondent: not determined
  • Context: lien release — clears the 2015 pledge. Netlist's own PTAB briefing states Samsung "did not record its release of the security interest to Netlist's patent assets until October 27, 2023," i.e. after the parties had become fully adverse and after Netlist terminated Samsung's license for breach in 2020.

Failure to record — note: the inventor-to-Netlist records I could verify belong to sibling Netlist filings, not provably to 16/680,060 — e.g. Reel 044194/0965 (recorded 2017-11-21, cited in a 37 CFR 3.73(c) statement) and plainsite-indexed Assignment 64686/603 (Lee, Hyun + Bhakta, Jayesh R. → Netlist, Inc., 3 Goddard, Irvine CA 92618; executed 2010-08-30, recorded 2023-08-23, covering US 10,949,339). Do not treat either as the '024's chain-of-title record without confirming the abstract at Assignment Center.

Timeline diagram

timeline
    title Ownership and liens US 11386024
    2009 : Provisional filed by Netlist
    2010 : Parent application filed
    2013 : First continuation filed
    2015 : Portfolio pledged to SVIC Samsung affiliate
    2017 : TR Global patent security agreement
    2019 : Application for this patent filed
    2022 : Patent issued to Netlist Inc
    2023 : Samsung records release of security interest
         : Netlist sues Samsung in Delaware
    2024 : Samsung files IPR2025-00001
    2025 : Netlist files statutory disclaimer

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No title ever moved to an LLC. The only USPTO recordings against the chain are a pledge (Reel 037150/0897, 2015-11-20) and its release (Reel 065629, 2023-10-27). Assignee of record has been Netlist, Inc. throughout.

2. Known asserter in the chain — NOT PRESENT. Netlist, Inc. does not appear on the RPX / Unified Patents high-frequency NPE directories; it is an operating memory company suing actual competitors (Samsung, Micron, Google, SK hynix). Caveat worth recording: Netlist is an extraordinarily frequent plaintiff whose revenue is increasingly litigation-dependent, which is why defendants describe it in NPE-like terms — but that is advocacy, not an NPE listing.

3. Repeat correspondent across the chain — NOT PRESENT / UNCLEAR. The only recorded-filing correspondent I could identify is DLA Piper LLP (US), San Diego (Troy Zander / Susan Reynholds, docket 350916-9) on Reel 037150/0897 — lender's counsel on a collateral filing. A single appearance is not the signal; no recurrence established. (Separately, the 2025 statutory disclaimer in the '024 file was filed by a "Jamie Zheng", docket NL066-13US01 — a prosecution/PTAB filer, not an assignment correspondent.)

4. Cascading transfers — NOT PRESENT. Zero consecutive LLC-to-LLC assignments. There is no chain to cascade.

5. Pre-litigation transfer — NOT PRESENT. The '024 issued to Netlist on 2022-07-12 and was still Netlist's when asserted in D. Del. 1:23-cv-01122 (2023) and attacked in IPR2025-00001 (filed 2024-10-08). No assignment within six months of any suit.

6. Bankruptcy fire-sale — NOT PRESENT. Netlist has never filed Chapter 7/11 to my knowledge. The 2015 pledge to a Samsung-affiliated fund and its late 2023 release are the residue of genuine distressed financing (after the Fortress payoff in Nov 2015), but no bankruptcy sale of this patent occurred.

7. Privateering — NOT PRESENT (and arguably inverted). The interesting inversion here is that a Samsung-affiliated fund (SVIC No. 28) held a security interest in the Netlist portfolio (Reel 037150/0897) while Samsung held a license (2015 JDLA). Netlist terminated that license for breach in 2020 and is now adverse to Samsung — the opposite of an operating company funding an NPE proxy.

8. Defensive aggregator — NOT PRESENT. The chain terminates at Netlist, an asserting operating company. No RPX/AST/LOT/OIN involvement. However: Google Patents records an adverse judgment in IPR2025-00001, and a statutory disclaimer under 37 CFR 1.321(a) naming patent 11,386,024 and Netlist, Inc. was filed (PTAB docket NL066-13US01). If claims were disclaimed/cancelled, the asset was neutralized by Netlist itself, not by a defensive aggregator — and that materially affects the patent's assertion value going forward. I could not verify which claims were disclaimed; treat the scope as unconfirmed.

Verdict

Operating-company assertion.

Title to US 11,386,024 never left Netlist, Inc.: the only USPTO recordings touching this portfolio are the 2015-11-18/2015-11-20 pledge to SVIC No. 28 New Technology Business Investment L.L.P. at Reel 037150/0897 and its release at Reel 065629 recorded 2023-10-27 — security interests, not conveyances — and the patent was asserted while Netlist still owned it (D. Del. 1:23-cv-01122; IPR2025-00001 filed 2024-10-08). With six of the eight NPE signals affirmatively absent, this is an operating memory company asserting against real competitors, notwithstanding that Netlist is a very high-volume plaintiff.

Two qualifications the record compels: (a) I could not verify a reel/frame for the underlying inventor→Netlist assignment for 16/680,060, so the chain-of-title granularity is incomplete; and (b) the recorded adverse judgment / 37 CFR 1.321(a) statutory disclaimer in the '024 file means the remaining enforceable scope may be materially narrower than the issued claims suggest.

Verify at: https://assignmentcenter.uspto.gov/ (search "11386024" or "16/680,060") · https://patents.google.com/patent/US11386024/en

I'll research US patent 11386024 and its cited prior art references.

Let me search for the specific prior art references cited against this patent and their details.

Prior-Art Analysis — U.S. Patent No. 11,386,024

⚠️ Important threshold caveats (read first)

1. Patent identity (literal reading). I analyzed US 11,386,024 B2, titled "Memory module having an open-drain output for parity error and for training sequences," Application No. US 16/680,060, filed 2019‑11‑11, granted 2022‑07‑12, assignee Netlist, Inc., inventor Hyun Lee, priority date 2009‑06‑12 (provisional 61/186,799). Source: https://patents.google.com/patent/US11386024/en

2. § 102 vs. § 103 — critical honesty note. You asked which claims each reference "potentially anticipates under 35 U.S.C. § 102." On the record I was able to retrieve, essentially no reference was asserted to anticipate the challenged claims standing alone. The '024 patent has been challenged (and its family siblings invalidated) through obviousness combinations under § 103 (Hazelzet + JEDEC, Hazelzet + Buchmann, + Kim). I therefore map each reference to the claims it is relevant to, and flag explicitly where § 102 anticipation is arguably available (Hazelzet alone) versus where only § 103 applies. I will not overstate anticipation.

3. Source of the "citations." I could retrieve the citation list for the family member US 10,474,595 (same specification, same family), which is the closest verified "References Cited" list. I could not independently verify the exact face-of-patent citation list printed on US 11,386,024 itself. I label Part B accordingly rather than present it as certain.

4. I prioritized live search results over training data where they conflicted, per your instruction.

Context: how the '024 patent is being litigated (procedural posture)

• IPR2025‑00001 — Samsung Electronics Co., Ltd. v. Netlist, Inc., Patent 11,386,024, challenged claims 1–20 (filed Oct. 8, 2024 per the PTAB docket capture).
  • Ground 1: Obviousness over Hazelzet + JEDEC — claims 1–20.
  • Ground 2: Obviousness over Hazelzet + Buchmann — claims 1–20.
  • Ground 3: Obviousness over Grounds 1–2 in further view of Kim — claims 1–20.
  • Source: https://ai-lab.exparte.com/case/ptab/IPR2025-00001/doc/1001
• Google Patents records, for this family, a Delaware District Court case (1:23‑cv‑01122) and PTAB activity. Source: https://patents.google.com/patent/US11386024/en
• Related family challenges: IPR2018‑00303 ('623), IPR2020‑01042 ('595), IPR2020‑01044 ('218), IPR2017‑00548 ('837) — all Netlist patents sharing this specification.

Part A — The most relevant prior art (references actually applied against the '024 family)

1. Hazelzet — primary reference (the "base" memory module)

Brief description. Hazelzet discloses a high-density RDIMM with an ECC/Parity register/buffer ("module controller") coupled to DRAMs and to a host memory controller. The module operates in either an ECC mode or a parity mode. In parity mode, a parity-generator/checker produces a parity error signal (PERR) that drives the module's open‑drain uncorrectable-error output (/Error (UE)) low. Hazelzet expressly states: "Two open‑drain outputs are available to permit multiple modules to share a common signal line for reporting an error… The outputs are driven low for two clocks to allow the memory controller time to sense the error." It also discloses driving the error line low, then disabling the driver to return the output to a high-impedance state so the line can be shared. Source (full text): https://uspto.report/patent/app/20080098277 ; corroboration in petitioner briefing: https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556759](/patent/1556759)/download-documents

Relevance / § 102–§ 103 mapping:

• Discloses (relevant to claim 1 / claim 10): a memory module with a module controller, DRAMs communicating data via edge connections, a transistor having an open drain coupled to an error edge connection, source to ground, and a gate, and a first signal that drives the gate to indicate a parity error during a normal read/write operation (claims 1, 2, 4, 5, 10).
• Does not disclose driving that same output with a second signal related to training sequences while DRAMs are not accessed for any normal read/write operation — the core of claims 1 and 10.
• § 102 verdict: Hazelzet alone cannot anticipate claims 1–3 or 10 (they require the training-sequence signaling). Hazelzet could arguably anticipate a dependent claim drawn solely to the parity-error reporting/open-drain structure (e.g., the subject matter of claim 5, "the first signal drives the gate of the transistor high to provide a low impedance path between the error edge connection and ground") if such a claim existed in isolation — but in the '024 patent that limitation is a dependent claim (5) that inherits all of claim 1's training-sequence elements, so no claim is anticipated by Hazelzet alone. Its real role is as the primary reference in § 103 combinations.

2. JEDEC LRDIMM DDR3 Material — primary reference for the training aspect

Brief description. The JEDEC LRDIMM work describes a Memory Buffer (MB / module controller) on a DDR3 LRDIMM with an initialization mode containing training sequences (e.g., "MB‑DRAM interface training"), during which no normal DRAM commands can be issued ("No DRAM commands… over the Command/Address and Control buses… can be issued to the MB until… training is complete"). Critically, it discloses an open‑drain ERROUT# pin used to signal training completion and also to report a parity error. Sources: https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556760](/patent/1556760)/ ; https://storage.courtlistener.com/recap/gov.uscourts.cand.[222877](/patent/222877)/gov.uscourts.cand.222877.301.4.pdf

Relevance mapping: supplies the "second signal related to training sequences while DRAMs are not accessed for normal read/write" element (claim 1) and the dual-use of the single error pin (claims 1–5, 7–10).

§ 102 verdict: JEDEC material is highly material and, combined with Hazelzet, formed the § 103 ground (Ground 1). Standing alone, JEDEC's ERROUT#/parity usage is close to the claim, and one could argue § 102 anticipation of some dependent claims — but the family record shows it was applied in § 103 combinations, not as a standalone anticipating reference.

3. Buchmann — training-sequence reference

Brief description. Buchmann discloses a cascade‑interconnect memory buffer operable in a static‑bit‑communication (SBC) mode and a high‑speed mode. It executes a power‑on/initialization training sequence (states TS0…TS7, including TS0 clock test/repair and TS3 upstream lane training/repair) initiated by the memory controller, performs handshaking in SBC mode, and generates status/notification signals (e.g., TS_done, TS3_ack) when a training step completes. Sources: https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1537243](/patent/1537243)/ ; https://bannerwitcoff.com/wp-content/uploads/2025/05/IPR2025-00002.pdf

Relevance mapping: supplies training performed outside normal memory operation plus status notification on completion — the "second signal related to training sequences" element (claim 1; claims 2–5, 7–10). PTAB previously found all claims of sibling patent '623 unpatentable over Hazelzet + Buchmann (IPR2018‑00303, FWD).

§ 102 verdict: Not a standalone anticipating reference for the '024 claims; applied under § 103 (Ground 2).

4. Kim — secondary reference (open-drain / shared error pin detail)

Brief description. Kim discloses a memory device/module with a single shared ERROR# feedback pin dotted via open drain across multiple memory devices, using an OR‑gate logic element to select between parity error and CRC error signals to drive the gate of the open‑drain pull‑down transistor (drain → output pin, source → ground, gate → logic). Source: https://patents.google.com/patent/[US8359521](/patent/US8359521)/en ; analysis: https://www.courtlistener.com/docket/64861664/478/3/netlist-inc-v-samsung-electronics-co-ltd/

Relevance mapping: supplies the explicit transistor (gate/source/open drain) structure and the multiplexor/logic circuit selecting between two signals — relevant to claims 4, 6, 9 (and, in the family, claims drawn to "a transistor having an open drain coupled to the error edge connection, a source coupled to ground, and a gate"). Applied in Ground 3 of IPR2025‑00001.

§ 102 verdict: Not an anticipating reference; § 103 secondary reference.

5. Wang — noted but not fully identified

Samung's IPR2025‑00001 lists Wang among the references combined for the training/interface-training element. I was unable to verify Wang's full citation (number, dates, title) in the searches performed, so I will not fabricate it. Treat "Wang" as identified but unconfirmed and requiring direct verification from the IPR2025‑00001 exhibit list.

Part B — Patent citations on the face of the family specification (References Cited)

The following U.S. patent documents appear in the "References Cited" list of family member US 10,474,595 (same specification/priority as the '024 patent), per https://patents.justia.com/patent/[10474595](/patent/10474595). Treat this as the family citation list, not a verified face-of-'024 list.

Also referenced in the specification as incorporated by reference: U.S. 2006/0062047 A1 and U.S. 2006/0262586 A1 (both listed above).

For each of these, the same caveat applies: none appears to anticipate the challenged claims standing alone; the material references (Hazelzet, Talbot, Amidi, Buchmann, Kim) were used in § 103 combinations across the family's IPRs.

Part C — Bottom line: claim-by-claim relevance of the strongest art

Limitations of this analysis

• I could not retrieve the verified face-of-patent "References Cited" list for US 11,386,024 itself; Part B reflects the family member US 10,474,595 and is flagged as such.
• The IPR2025‑00001 outcome/grounds were captured from third-party PTAB-data aggregators (exparte.ai, Darts‑IP/Unified Patents); I did not pull the official PTAB Final Written Decision for '024.
• "Wang" could not be fully identified (number/date/title unverified) — flagged rather than fabricated.
• No reference in the retrieved record was held to anticipate the '024 claims under § 102; all challenges were § 103 obviousness grounds. Any § 102 characterization here is a relevance assessment, not a holding.

Primary sources cited: https://patents.google.com/patent/US11386024/en · https://ai-lab.exparte.com/case/ptab/IPR2025-00001/doc/1001 · https://ptacts.uspto.gov/ptacts/public-informations/petitions/1556759/ · https://ptacts.uspto.gov/ptacts/public-informations/petitions/1556760/ · https://uspto.report/patent/app/20080098277 · https://patents.google.com/patent/US8359521/en · https://patents.justia.com/patent/10474595 · https://bannerwitcoff.com/wp-content/uploads/2025/05/IPR2025-00002.pdf

I'll gather the prior-art references associated with this patent before building the obviousness analysis.

Let me pull additional detail on the key references and the litigation/PTAB record.

Obviousness Analysis — U.S. Patent No. 11,386,024 B2

Patent: US 11,386,024 B2 ("the '024 patent"), Memory module having an open-drain output for parity error and for training sequences
Assignee: Netlist Inc. | Inventor: Hyun Lee
App. No.: 16/680,060, filed 2019-11-11 | Granted: 2022-07-12
Earliest priority (as listed): 2009-06-12 (Prov. 61/186,799)
Continuation chain: 12/815,339 (now 8,489,837) → 13/942,721 (now 9,311,116) → 15/088,115 (now 9,858,218) → 15/857,553 (now 10,474,595) → 16/680,060
Source of record for this analysis: https://patents.google.com/patent/US11386024/en

1. Claimed subject matter (what must be rendered obvious)

Claim 1 is the anchor. It requires, in combination:

Note a labeling point I will flag but not "correct": in granted claim 1 the first edge connections carry address/control and the second edge connections carry data. Elsewhere in the same document (Summary; the FIG. 1–3 description and the earlier family members) the module controller is described as receiving address/control "via the second edge connections." The claim and the specification therefore appear to use the first/second designations inconsistently. I flag this as an observation only; claim language controls.

Claims 2–9 add: state-to-state driving between low logic level and high impedance (2–4); gate-high → low-impedance path to ground for the parity signal (5); the transistor inside an integrated circuit (6); data edge connections inactive during training (7, 8); and a multiplexor or logic circuit at the gate selecting between the first and second signals by mode (9). Claim 10 is a method counterpart; claims 11–20 depend from it.

2. The prior art (identifiers stated literally as they appear in the record)

Sources: PTAB petition and declaration excerpts — https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556759](/patent/1556759)/download-documents?artifactId=UFCNZwtZiN4iX2qQnQvWSd6SxwLrJBrd7ecyW3J0mwsVBxSozNZFtIU ; https://ptacts.uspto.gov/ptacts/public-informations/petitions/1556759/download-documents?artifactId=FjXMi8a50C1-6kjSOW6BHPA-nOFV2fTOW5LOuFbw_6LFJ2Z4i5Y0yUg ; JEDEC register spec text — https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/JESD82_2D00_29A.01.pdf ; '595/'218 IPR record — https://www.docketalarm.com/cases/PTAB/IPR2020-01042/Inter_Partes_Review_of_U.S._Pat._10474595/docs/06-09-2020-Petitioner/Exhibit-1035-35-SK_hynix_Inc_et_al_v_Netlist,_Inc,_IPR2017_00548,_Paper_No_25_PTAB_May_3,_2018_837_Patent_Final_Written_Decision.pdf

3. Ground 1 (primary): Hazelzet in view of JEDEC — claims 1–20

Limitations (a)–(c): Hazelzet's DIMM 20 is a printed circuit board with edge contacts that plug into a host slot; it carries SDRAMs 22 and an ECC/Parity buffer/register 21 interposed between the DRAMs and the memory interface chip/controller, receiving address-and-command signals and conveying data over the module data lines. That is a module controller receiving address/control and DRAMs communicating data over separate edge connections — (a)–(c). JEDEC supplies the LRDIMM variant in which the module buffer (MB) is the "module controller" and normal DRAM commands are blocked until training completes.

Limitation (d): Hazelzet's "/Error (CE)" and "/Error (UE)" are open-drain outputs, which to a POSITA necessarily means the output node is the drain of a field-effect transistor whose source is tied to ground and whose gate is driven by logic (the drain connects to the module's error edge contact; a pull-up on the planar provides the high side). Hazelzet's own text confirms the driver is enabled/disabled and the output returns to "an un-driven state (high impedance)." The transistor terminal identity is inherent in "open drain" and is further illustrated by Kim's and Dill's teachings.

Limitation (e): In Hazelzet's parity mode, the parity generator/checker produces PERR, and the error logic drives the UE line low — the reporting is qualified by a valid command (/CS low), i.e., "when the memory module is being accessed for a normal memory read or write operation." The same open drain / parity error behavior is independently stated in JESD82-29: the register "accepts a parity bit … compares it with the data received … and indicates on its open-drain ERROUT# pin (active LOW) whether a parity error has occurred."

Limitation (f): This is the heart of the case, and JEDEC discloses it directly:

• JEDEC's initialization chapter provides that after reset the MB takes autonomous control of the command/address, control and data/strobe signals to the DRAMs "without any further assistance from the host" to run Write Leveling, Read Enable Training and Read/Write DQ/DQS training.
• JEDEC states that no DRAM commands or control-word writes can be issued to the MB until MB-DRAM interface training is complete — i.e., the DRAM elements are not accessed for any normal read or write during training (also satisfying claims 7 and 8).
• JEDEC states the host "can wait for the per-physical-rank timeout … or wait for ERROUT#," i.e., training completion is signaled on the same open-drain ERROUT# pin that reports parity errors.

So the second signal "related to one or more training sequences" is applied to the gate of the very transistor whose drain is the error edge connection — exactly limitation (f).

Motivation to combine (KSR rationales):

1. Known problem / known solution. Hazelzet's stated object is a high-density, high-reliability module ("improved overall system reliability … high memory density"); JEDEC's LRDIMM buffering + training is a known technique for reducing bus loading and enabling higher capacity/speed. A POSITA seeking Hazelzet's own stated goals would have looked to LRDIMM buffering and its associated training.
2. Avoiding polling. The '024 patent itself characterizes polling as inefficient and notification/interrupt as the advantageous handshake. Open-drain signaling was a standard, standardized interrupt-style alternative to SMBus register polling — JEDEC expressly offers ERROUT# as the "wait for" alternative to polling the buffer's CSRs.
3. Pin economy. The '024 patent's own stated advantage is reusing an existing JEDEC-specified pin rather than adding pin-outs. Re-using Hazelzet's already-present open-drain UE output for training status is the same design choice, and JEDEC confirms it on the ERROUT# pin.
4. Wired-OR benefit. An open-drain line shared across modules lets any module still training hold the line low, so the controller learns that all modules have finished — a result Hazelzet itself notes ("allowing this line to be shared by multiple modules") and which suits Hazelzet's multi-module server.
5. Predictable result. Both are memory-module architectures in the same field, addressing the same problem; driving an existing open-drain gate with a training-status signal is a simple logic change with no change to module hardware.

Expectation of success: High — data buffering, training, and open-drain error signaling were each well-known; JEDEC demonstrates the exact result (training completion signaled on ERROUT#) in an LRDIMM.

4. Ground 2: Hazelzet in view of Buchmann — claims 1–20

Buchmann supplies the training/notification half without resort to the JEDEC ballot, which matters if the JEDEC material's public-availability date is contested.

• Buchmann's module has an MB with an SBC mode used at power-on for initialization and training (TS0, TS3), and a high-speed functional mode thereafter. Training occurs before normal operation and produces a TS_done notification.
• Hazelzet supplies the module with DRAMs, a module controller, and the open-drain UE/CE output driven to ground on an error during a valid command.
• Motivation: Hazelzet expressly seeks "improved overall system reliability"; Buchmann's training exists precisely to establish reliable communication before high-speed operation; a POSITA would apply Buchmann's proven training to Hazelzet and use Hazelzet's existing open-drain output to convey TS_done, because (i) the UE pin is idle during training (no valid commands are being processed, hence no parity errors to report), and (ii) reusing it avoids adding pins.
• This is not merely my analysis: the Board has already found substantially the same claims of the related family members obvious over Hazelzet + Buchmann ('623 and '218 Final Written Decisions; see the '837 FWD and the '218/'595 record at the docketalarm URL above), and the '218/'595/'024 claims are admitted or found to be patentably indistinct in material respects (Netlist filed terminal disclaimers tying the '024 family members together).

5. Ground 3: Grounds 1 or 2 further in view of Kim — claims 4, 5, 9 (and 6)

Kim supplies the explicit circuit for the "multiplexor or logic circuit" of claim 9 and reinforces claims 4–6.

• Kim's FIG. 5 shows an OR gate receiving parity error and CRC error inputs and driving an open-drain output, so that a single shared error pin reflects either condition. Kim also shows the open drain as a three-terminal transistor output (FIG. 4).
• Motivation: to place a training-status signal and a parity-error signal on one open-drain pin, one needs to combine the two sources; OR-gating is the classic, minimal way to do it, and Kim demonstrates exactly that. (Equivalently, the multiplexor of the '024 patent's FIG. 3 — driving the transistor with task_in_progress or error — is the same selection function.) Kim also teaches the mode-based selection concept and that the shared function may be "merged with an existing error pin available on many industry standard modules."
• Claim 5's "gate driven high to provide a low-impedance path between the error edge connection and ground" is inherent in open-drain operation (Kim FIGS. 4–5; Dill for FET structure), and claim 6's "integrated circuit that includes the transistor" is met by Hazelzet's teaching that the module support devices "may be combined onto a single package or even integrated onto a single device."

6. Ground 4: Hazelzet in view of Wang — claims 1–20

Wang is a substitute for JEDEC/Buchmann on the training half: Wang's interface circuits buffer data between DRAMs and the memory controller and are trained/calibrated in response to a calibrate command, with training being distinct from normal read/write operation. Motivation: Wang expressly seeks to overcome command-scheduling constraints and to eliminate idle bus cycles while remaining usable with existing memory controllers, which dovetails with Hazelzet's stated goal of industry compatibility at higher density; and the same open-drain reuse rationale applies.

Amidi and Talbot are secondary supports: Amidi for tying multiple status sources to one error-out terminal through a logic-OR/wired-OR/open-collector device, and Talbot for the normal-mode vs. configuration-and-training-mode duality in which the error path is repurposed when the error function is idle.

7. Dependent claims 2–9

Claims 2–9 add only conventional electrical details of open-drain signaling and a routine mode-selection logic function; they carry no separate inventive weight.

8. Method claims 10–20

Claim 10 recites the same structure and steps in method form: receiving address/control over the first edge connections; outputting/receiving data over the second edge connections; applying a first signal to the gate to indicate a parity error during a normal read/write; and performing training operations with the corresponding second-signal application. Because apparatus and method claims rise and fall together where the method is the intended use of the disclosed structure, the same combinations (Hazelzet + JEDEC, +Buchmann, +Wang, +Kim) render claims 10–20 obvious for the reasons in §§3–6. The method steps are performed by the conventional operation of the very circuitry relied upon for claim 1 — no additional reference is required.

9. Where a patent owner could push back, and limits on confidence

• Priority. If the '024 claims are not entitled to 2009-06-12 (the Delaware/related litigation record includes allegations to that effect), the December 2009 JEDEC ballot and JESD82-29 (dated December 2009) become squarely available even under §102(a)/(b). If, conversely, the claims do get the 2009-06-12 date, the JEDEC material that predates it is the June 4, 2009 draft. I cannot, from the sources reviewed, confirm which date the claims ultimately receive — treat this as the pivotal unresolved fact.
• "Open drain = FET with source to ground." A patent owner could argue the prior art does not expressly recite gate/source/drain. The answer is that "open drain" has a definite meaning to a POSITA and Dill/Kim supply the structure; this is at most an inherency-obviousness dispute, and the Board has resolved it against the patent owner in the related proceedings.
• Teaching away / separate purposes. A patent owner may argue Hazelzet's error outputs are for error reporting, not status handshaking. JEDEC defeats this by expressly using ERROUT# for training completion, and Hazelzet itself contemplates the error pin conveying module status to the system controller. The "training status ≠ error" gap is bridged by the express JEDEC disclosure, not by inference.
• One inconsistency I will not silently fix: the claim/specification mismatch between "first" and "second" edge connections noted in §1. If construed strictly against the specification, this could complicate mapping; I am flagging it rather than assuming an intended reading.

10. Litigation / PTAB posture (as reported)

• Google Patents lists this family as having litigation and links Delaware District Court case 1:23-cv-01122 (https://portal.unifiedpatents.com/litigation/Delaware%20District%20Court/case/1%3A23-cv-01122).
• Google Patents lists PTAB case IPR2025-00001 filed (Adverse Judgment) (https://portal.unifiedpatents.com/ptab/case/IPR2025-00001); the petitioner field is blank on the page as fetched. Separate ex parte material identifies IPR2025-00001 as [Samsung Electronics Co Ltd](/litigations/by-plaintiff/Samsung%20Electronics%20Co%20Ltd) v. Netlist Inc against the '024 patent, challenging claims 1–20 on grounds of (1) Hazelzet + JEDEC, (2) Hazelzet + Buchmann, and (3) those grounds further in view of Kim (https://ai-lab.exparte.com/case/ptab/IPR2025-00001/doc/1001). I report the "Adverse Judgment" label exactly as the Google Patents page states it and do not extrapolate its basis.
• Substantially identical claims in the family were held unpatentable as obvious over Hazelzet + Buchmann (and over Hazelzet + JEDEC), e.g. the '837 and '218 Final Written Decisions (https://www.docketalarm.com/cases/PTAB/IPR2020-01042/Inter_Partes_Review_of_U.S._Pat._10474595/docs/06-09-2020-Petitioner/Exhibit-1035-35-SK_hynix_Inc_et_al_v_Netlist,_Inc,_IPR2017_00548,_Paper_No_25_PTAB_May_3,_2018_837_Patent_Final_Written_Decision.pdf).

Bottom line

Claims 1–20 of US 11,386,024 are, on this record, obvious under 35 U.S.C. § 103(a) (pre-AIA, given the 2009 priority):

• Primary: Hazelzet (module with DRAMs, module controller, and an open-drain error output driven low on a parity error during a valid command) in view of JEDEC's LRDIMM initialization proposal/JESD82-29 (MB training sequences, no DRAM access during training, and use of the same open-drain ERROUT# pin to signal training completion/parity error).
• Equivalent alternatives: Hazelzet + Buchmann (TS0/TS3 training with TS_done notification), and Hazelzet + Wang (buffered interface with calibration training) supply the same missing teaching.
• Secondary: Kim (OR-gate aggregation of parity and CRC onto a shared open-drain error pin) supplies the claim 9 logic/multiplexor element and reinforces claims 4–6; Amidi and Talbot provide corroborating OR-gate and training-mode teachings.

The motivation is supplied by the references themselves and by the patent's own stated rationale: improve density/performance and reliability, avoid inefficient polling with an interrupt-style notification, and reuse an existing JEDEC-defined open-drain error pin rather than adding pins — with a reasonable expectation of success because each element (buffering, training, open-drain error signaling, logic aggregation) was individually known and combined for its known purpose.