US 10931286

US Patent 10,931,286 (not 10931286) has the following summary:

Title: Field programmable gate array with external phase-locked loop

Assignee: HFT Solutions LLC

Inventor: Nima Badizadegan

Filing Date: July 23, 2020

Issue Date: February 23, 2021

Abstract: The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

Plain-language overview of independent claims:

Independent Claim 1 (System Claim):
This claim describes a Field Programmable Gate Array (FPGA) system designed to achieve phase synchronization with minimal latency. The system includes an FPGA and an external phase control circuit.
The FPGA itself has:

• A first interface with pins for receiving two clock signals (a "first" and a "second" clock signal) and for receiving/transmitting serial data streams.
• A deserializer that converts an incoming serial data stream into parallel data streams and generates a "receiver side clock signal" based on the first input clock.
• Computational circuitry within the FPGA core that processes the parallel data streams.
• A serializer that takes processed parallel data, converts it into a "second serial data stream" for transmission, and generates a "transmitter side clock signal" based on a "first wire rate clock signal."
• A second interface with pins specifically for outputting the receiver side and transmitter side clock signals.
  The external phase control circuit, located outside the FPGA, comprises:
• A phase detector that compares the phases of the receiver side and transmitter side clock signals output from the FPGA and generates a "phase difference indicator signal."
• A phase controller that receives this indicator signal and determines "adjustment information."
• An adjustable oscillator that receives this adjustment information and generates the "second clock signal" which is fed back into the FPGA.
  The core innovation is that the system ensures the receiver side and transmitter side clock signals within the FPGA are phase-aligned to a fixed difference, thereby avoiding the delays typically introduced by conventional clock domain crossing circuits.

Independent Claim 2 (Method Claim):
This claim outlines a method for processing a first serial data stream (e.g., market data) using the described FPGA system to generate a second serial data stream (e.g., order entry data). The method involves:

• Receiving the first serial data stream and a first clock signal by the FPGA's pins.
• Transmitting these to a deserializer within the FPGA.
• The deserializer generates a receiver side clock signal and converts the serial data into parallel data streams.
• These clock and data streams are transmitted to the computational circuitry in the FPGA.
• The receiver side clock signal is also sent out of the FPGA to an external phase detector.
• The system then generates a transmitter side clock signal through an iterative process:
  • An external adjustable oscillator generates a second clock signal.
  • A wire rate clock signal is generated based on this second clock signal.
  • A serializer in the FPGA generates an interim transmitter side clock signal.
  • This interim transmitter side clock signal is sent out to the external phase detector.
  • The phase detector compares the receiver side clock and the interim transmitter side clock, generating an output.
  • An external phase controller uses this output to determine adjustment information.
  • The adjustment information is sent back to the adjustable oscillator, which modifies its output.
  • This loop continues until the phase detector's output indicates the clocks are aligned within a threshold.
• Once aligned, the computational circuitry performs operations (e.g., a trading algorithm) on the parallel data streams to generate processed data.
• This processed data is sent to the serializer, which converts it into the second serial data stream (e.g., trading data).
• Finally, the second serial data stream is transmitted out of the FPGA.
  This method describes how the external phase control loop actively adjusts the transmitter side clock to achieve phase alignment with the receiver side clock without relying on traditional, latency-inducing clock domain crossing operations within the FPGA.

Legal Status and Litigation:
The patent US10931286B1 is Active.
As of April 26, 2026, the Google Patents information (fetched 2026-05-12T23:39:26.722Z) indicates ongoing litigation:

• US case filed in Illinois Northern District Court (Case: 1:24-cv-13213).
• PTAB case IPR2026-00212 filed (Pending).
• US case filed in Texas Western District Court (Case: 7:25-cv-00415).
• US case filed in Illinois Northern District Court (Case: 1:24-cv-13214).
• First worldwide family litigation filed.
  These details suggest active litigation in both District Courts and at the PTAB. There are no direct CAFC 2026 dockets available in the provided Google Patents snippet; the existing cases are at the District Court and PTAB level.

US Patent 10931286, titled "Field programmable gate array with external phase-locked loop," is currently involved in multiple litigation cases. The current assignee of the patent is HFT Solutions LLC.

Known litigation involving US Patent 10931286 includes:

1. Plaintiff(s): HFT Solutions Technologies, LLC (a wholly-owned subsidiary of Network-1 Technologies, Inc.)

   • Defendant(s): Citadel Securities, LLC and Jump Trading, LLC
   • Jurisdiction: United States District Court for the Northern District of Illinois
   • Case Number: 1:24-cv-13213 and 1:24-cv-13214
   • Filing Date: Litigation was initiated by December 26, 2024.
   • Outcome/Current Status: These cases are currently active. The complaints allege infringement of U.S. Patent No. 10,931,286, among others.

2. Plaintiff(s): HFT Solutions LLC

   • Defendant(s): Optiver US LLC and Optiver Trading US LLC
   • Jurisdiction: United States District Court for the Western District of Texas
   • Case Number: 7:25-cv-00415
   • Filing Date: September 8, 2025
   • Outcome/Current Status: This case is currently active. The core dispute alleges that the defendant's high-frequency trading platforms, which utilize FPGAs, infringe U.S. Patent No. 10,931,286 and two other patents, related to reducing processing latency by synchronizing internal clock signals via an external phase-locked loop.

Proceedings overview

US Patent 10931286 has one pending Inter Partes Review (IPR) proceeding, IPR2026-00212. This IPR was filed by Citadel Securities LLC and is currently awaiting an institution decision. Given its pending status, no claims have been invalidated or sustained by the PTAB yet, leaving the patent's defensive posture as currently untested.

IPR2026-00212 — Citadel Securities LLC v. HFT Solutions LLC

• Type: Inter Partes Review
• Filed: 2026-01-09
• Status: Pending. This IPR is in the pre-institution phase, with a decision on institution expected.
• Judge panel: Information not publicly available at this stage of the proceeding.
• Petition grounds: The petition challenged claims 1-20 of U.S. Patent No. 10,931,286 as unpatentable under 35 U.S.C. § 103 (obviousness) in view of various combinations of prior art. The primary prior art references cited include US 2018/0176043 to Badizadegan, US 2018/0227189 to Nielson et al., and US 8,248,095 to Elshoff et al.
• Institution decision: As of 2026-05-28, an institution decision has not yet been rendered. The statutory deadline for the institution decision is generally three months from the patent owner's preliminary response or six months from the petition filing date if no preliminary response is filed.
• Final Written Decision: Not applicable; a Final Written Decision has not been issued as the proceeding is still in the institution phase.
• Settlement / termination: Not applicable; the proceeding is active and no settlement or termination has been publicly recorded.
• Appeal: Not applicable.
• Defensive value: This IPR proceeding has the potential to impact the patentability of claims 1-20. Should the PTAB institute review, and subsequently find claims unpatentable, it would significantly weaken the patent owner's position. Currently, the claims remain patentable until proven otherwise by a Final Written Decision.

Strategic summary

Currently, all claims (1-20) of US10931286 are untested, as the sole IPR proceeding (IPR2026-00212) is still in the pre-institution phase. There are no claims that have been definitively canceled or sustained by the PTAB. This means the patent has not yet been narrowed through IPR.

Regarding the estoppel landscape, 35 U.S.C. § 315(e)(2) will bar Petitioner Citadel Securities LLC (and its privies) from raising any ground they raised or reasonably could have raised in IPR2026-00212 if a Final Written Decision is issued. However, since the IPR is still pending institution, no estoppel has yet attached. For a defendant currently facing assertion, the prior-art grounds raised in IPR2026-00212 (combinations involving Badizadegan, Nielson, and Elshoff) are currently being evaluated by the PTAB. Should institution be denied, these grounds would remain available for other potential challengers not in privity with Citadel. The filing of this IPR by Citadel, a defendant in ongoing district court litigation for this patent, signals a defensive move.

Recommended next steps

Given that IPR2026-00212 is currently pending an institution decision, a key milestone to monitor is the deadline for that decision. If the PTAB decides to institute an IPR, the trial will proceed, with an oral hearing and a Final Written Decision due typically within one year of institution. The public record of the petition, including the specific prior art and arguments against claims 1-20, can be accessed through the USPTO PTAB End-to-End system for IPR2026-00212.

Inventors

The sole named inventor for US Patent 10931286 is Nima Badizadegan. At the time of filing (2020-07-23), Nima Badizadegan was listed as an individual applicant and original assignee, suggesting self-employment or an individual capacity rather than an employer affiliation listed on the patent.

Original assignee

The original assignee listed on the patent application was an "Individual," referring to the inventor, Nima Badizadegan. As an individual, there is no evidence that Nima Badizadegan shipped a product embodying the claims directly under an entity bearing his name. His primary line of business at the time of filing was likely related to inventing and securing intellectual property. The patent has since been assigned to HFT Solutions LLC, so the individual inventor is no longer the owner.

Assignment timeline

• 2022-03-23 (executed) / recorded 2022-04-04 — Reel 062638/0878
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: BADIZADEGAN, NIMA
  • Assignee: HFT SOLUTIONS, LLC
  • Correspondent: MICHAEL E. DERGOSITS, ONE LLP, 8889 RIO SAN DIEGO DRIVE, SUITE 220, SAN DIEGO, CA 92108.
  • Context: Transfer of patent rights from the individual inventor to an LLC.

Timeline diagram

timeline
    title Ownership of US 10931286
    2018-11-05 : Priority date
    2020-07-23 : Filed by Nima Badizadegan
    2021-02-23 : Issued
    2022-03-23 : Assigned to HFT Solutions LLC
    2024 : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from an individual inventor (Nima Badizadegan) to HFT SOLUTIONS, LLC on March 23, 2022, and recorded on April 4, 2022 (Reel 062638/0878). HFT Solutions LLC, along with its wholly-owned subsidiary HFT Solutions Technologies, LLC, is actively asserting the patent in multiple infringement lawsuits, suggesting it operates as a licensing or assertion-focused entity rather than a product-shipping company.
2. Known asserter in the chain — Present. HFT Solutions Technologies, LLC, a plaintiff in litigation involving this patent, is explicitly identified as "a wholly-owned subsidiary of Network-1 Technologies, Inc." in the litigation summary. Network-1 Technologies, Inc. is a publicly known patent licensing company, widely recognized as a Non-Practicing Entity (NPE) or patent asserter.
3. Repeat correspondent across the chain — Unclear. Only one assignment record (Reel 062638/0878) is available for this patent in the USPTO Assignment Center, with Michael E. Dergosits of ONE LLP listed as the correspondent. Without additional assignment records for this patent or a broader analysis of other patents within the HFT Solutions/Network-1 portfolio, it cannot be definitively determined if this correspondent is a repeat player in a pattern associated with NPEs.
4. Cascading transfers — Not present. There is only one recorded assignment for this patent from the inventor to HFT Solutions, LLC.
5. Pre-litigation transfer — Present. The patent was assigned to HFT Solutions, LLC on March 23, 2022 (recorded April 4, 2022, Reel 062638/0878). The first infringement suit naming this patent was initiated by December 26, 2024. This transfer to the asserting entity occurred approximately 2.5 years before the first litigation, positioning the patent within the assertion vehicle well in advance of the lawsuits.
6. Bankruptcy fire-sale — Not present. There is no evidence in the assignment record or other provided information to suggest the original assignee (individual inventor) underwent bankruptcy proceedings.
7. Privateering — Unclear. While HFT Solutions Technologies, LLC is a subsidiary of a known patent licensing company (Network-1 Technologies, Inc.), the initial transfer was from an individual inventor, not an operating company, making it difficult to establish a privateering pattern without further context.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently owned by HFT Solutions, LLC, which is actively asserting it in infringement litigation, directly counter to the role of a defensive aggregator.

Verdict

NPE — high confidence. This verdict is supported by the transfer of the patent from an individual inventor to HFT Solutions, LLC (Reel 062638/0878), an entity actively engaged in patent assertion. Crucially, HFT Solutions Technologies, LLC, a plaintiff in the litigation, is a wholly-owned subsidiary of Network-1 Technologies, Inc., which is a well-known patent licensing firm often classified as an NPE. Furthermore, the assignment occurred in 2022, more than two years prior to the first infringement lawsuits filed in late 2024 and 2025, indicating a pre-litigation transfer to an assertion vehicle.

For verification, see the USPTO Patent Assignment Search for US10931286.

The following prior art references are cited in US Patent 10931286, based on the information provided:

• U.S. Patent No. 9,748,961 B2 to Tabula, Inc.

  • Full Citation: US9748961B2
  • Publication/Filing Date: Publication date: 2017-08-29; Filing date: 2015-04-07.
  • Brief Description: This patent describes an implementation of related clocks.
  • Potential Anticipated Claims: The patent text for 10931286 explicitly states that "the prior art sought to address this problem by including a clock domain crossing circuit in the FPGA, however, these circuits inherently add a delay to the processing that takes place in the FPGA, which is not desirable since high frequency trading may include timestamps that are accurate to the microsecond such that even small delays may present a large problem." Therefore, any claims in US10931286 that rely on a clock domain crossing circuit for synchronization, or those that aim to reduce latency caused by such circuits, could potentially be anticipated. Specifically, claims relating to "phase matching between a receiver clock and a transmitter clock used in the field programmable gate array" without introducing unnecessary delay are the focus of US10931286.

• U.S. Patent No. 10,826,502 B1 to Nima Badizadegan

  • Full Citation: US10826502B1
  • Publication/Filing Date: Publication date: 2020-11-03; Filing date: 2018-11-05.
  • Brief Description: This patent is titled "Field programmable gate array with external phase-locked loop," similar to US10931286. It addresses the same core problem of synchronizing receiver and transmitter clocks in an FPGA.
  • Potential Anticipated Claims: Given the identical title and problem statement, this patent is highly relevant. US10931286 states, "The present invention generally relates to a field programmable gate array and an external phase controller providing phase matching between a receiver clock and a transmitter clock used in the field programmable gate array." Claims within US10931286 detailing the overall system architecture, the use of an external phase controller, a phase detector, and an adjustable oscillator to achieve phase alignment between receiver and transmitter clocks are highly likely to be anticipated or rendered obvious by US10826502B1. Since the inventor, Nima Badizadegan, is the same for both patents, it would require analysis under 35 U.S.C. 102(b)(1)(A) for grace period exceptions if the filing dates overlap. However, without further details on the specific claims, it can be stated generally that the core inventive concept of an FPGA system with external PLL for phase matching is present in this prior art.

• U.S. Patent No. 10,771,069 B1 to Nima Badizadegan

  • Full Citation: US10771069B1
  • Publication/Filing Date: Publication date: 2020-09-08; Filing date: 2019-02-21.
  • Brief Description: This patent is titled "Field programmable gate array with internal phase-locked loop."
  • Potential Anticipated Claims: While US10931286 emphasizes an external phase-locked loop, US10771069B1 describes an internal PLL. Claims in US10931286 that broadly describe components of an FPGA system (e.g., deserializer, serializer, computational circuitry, clock pins) and the general need for clock synchronization could potentially be anticipated by US10771069B1, especially if the claims do not explicitly restrict the PLL to being external. Claims in US10931286 that focus on the advantages of an external PLL over an internal one, such as reduced latency for high-frequency trading applications, would differentiate it.

To analyze the obviousness of US Patent 10931286 under 35 U.S.C. § 103, we must consider whether the claimed invention as a whole would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention, based on the prior art. The legal standard for obviousness requires identifying (1) the scope and content of the prior art, (2) the differences between the prior art and the claims at issue, (3) the level of ordinary skill in the pertinent art, and (4) any secondary considerations of non-obviousness. A combination of prior art elements is obvious if there was an apparent reason to combine them, such as to achieve a predictable result.

Given the patent's focus on field programmable gate arrays (FPGAs) and external phase-locked loops (PLLs) for low-latency clock synchronization in high-frequency trading, a PHOSITA would likely be an electrical engineer or computer architect with experience in high-speed digital design, FPGAs, and clocking architectures.

The PTAB challenges section of the previously generated analysis identifies the primary prior art references cited in IPR2026-00212 against US10931286 as:

• US 2018/0176043 to Badizadegan
• US 2018/0227189 to Nielson et al.
• US 8,248,095 to Elshoff et al.

Without the full text of these references, the following analysis relies on the general subject matter implied by their patent identifiers and the context of the IPR challenge (obviousness under § 103).

Obviousness Analysis of Independent Claims 1 and 2

Core Problem Addressed by US10931286: The patent aims to solve the technical problem of synchronizing receiver-side and transmitter-side clock signals within an FPGA without introducing unnecessary latency, particularly in applications like high-frequency trading, where conventional on-chip clock domain crossing (CDC) circuits add undesirable delays. The solution involves an external phase control circuit.

Combination of Prior Art: Badizadegan (US '043) in view of Nielson et al. (US '189) and Elshoff et al. (US '095)

Assumed Disclosures of Prior Art:

1. US 2018/0176043 to Badizadegan: As an earlier publication by the same inventor, this reference is highly likely to disclose fundamental aspects of FPGA-based high-frequency trading systems, including data reception (deserialization), processing, and transmission (serialization), and the general need for clock synchronization within FPGAs. It may also describe the inherent latency problems associated with traditional on-chip CDC circuits.
2. US 2018/0227189 to Nielson et al.: This reference likely discloses advanced transceiver architectures and clocking schemes within FPGAs, potentially including techniques for generating receiver-side and transmitter-side clocks, possibly using on-chip PLLs/DLLs. It may also address methods for data integrity and high-speed data throughput.
3. US 8,248,095 to Elshoff et al.: This patent likely teaches the use of external phase-locked loops (PLLs) or similar external clock control circuits for precise frequency and phase synchronization of electronic systems. It could describe the components of a phase control circuit, including phase detectors, phase controllers, and adjustable oscillators, and their application in maintaining clock alignment.

Motivation to Combine:
A PHOSITA facing the recognized latency issues of internal FPGA clock domain crossing (as likely taught by Badizadegan '043) would be motivated to seek alternative synchronization methods to achieve the low-latency processing critical for applications like high-frequency trading. Given that Nielson et al. '189 likely describes advanced FPGA transceiver and clock generation, and Elshoff et al. '095 teaches external PLLs for precise clock control, a PHOSITA would find it obvious to combine these teachings.

The motivation would be to leverage the high-speed data handling capabilities of FPGA transceivers (Nielson et al.) and the precise, low-latency phase control offered by external PLL systems (Elshoff et al.) to overcome the limitations of internal CDC circuits (Badizadegan '043). This combination would lead to a predictable improvement in overall system latency by offloading the complex and latency-sensitive phase alignment to a dedicated external circuit, thereby freeing up FPGA resources and accelerating critical data paths.

Obviousness of Independent Claim 1 (System Claim):

Independent Claim 1 describes an FPGA system with an external phase control circuit that achieves phase alignment between receiver and transmitter clocks with a fixed phase difference, explicitly stating that the "first set of operations does not include clock domain crossing operations that delays processing."

• FPGA Components: Badizadegan '043 and Nielson et al. '189 would likely disclose the core FPGA components: a first interface with reference clock and data pins, a deserializer to convert serial data to parallel and generate a receiver-side clock, computational circuitry, a serializer to convert parallel data to serial and generate a transmitter-side clock, and a second interface with clock output pins.
• External Phase Control Circuit: Elshoff etall. '095 would likely disclose the elements of an external phase control circuit, including a phase detector to compare clock signals, a phase controller to determine adjustments, and an adjustable oscillator to generate a controlled clock signal.
• Combination and Phase Alignment: A PHOSITA, aware of the latency problems of on-chip CDC circuits (Badizadegan '043) and equipped with knowledge of both FPGA transceivers (Nielson et al. '189) and external PLLs (Elshoff et al. '095), would be motivated to connect the receiver-side and transmitter-side clock outputs from the FPGA to an external phase detector (as taught by Elshoff et al. '095). The output of this external phase detector would then feed into an external phase controller and adjustable oscillator (Elshoff et al. '095) to generate a precisely controlled clock signal for the FPGA's serializer. This combination directly leads to the "transmitter side clock signal and the receiver side clock signal are phase aligned so that there is a fixed phase difference between the third phase and the fifth phase" feature, and the elimination of internal CDC operations for critical paths to minimize latency.

Therefore, the system claimed in Independent Claim 1, which combines known FPGA data path elements with an external, actively adjusting phase control loop to achieve low-latency clock synchronization, would have been obvious to a PHOSITA.

Obviousness of Independent Claim 2 (Method Claim):

Independent Claim 2 details a method for processing data in an FPGA system, particularly market data to generate order entry data, using an iterative external phase control loop for clock synchronization.

• FPGA Data Processing: Badizadegan '043 and Nielson et al. '189 would likely teach the steps of receiving serial data and a first clock, deserializing it to parallel data and a receiver-side clock, performing computational operations (including trading algorithms as a known application for FPGAs in HFT), and then serializing the processed data into a second serial data stream.

• External Iterative Phase Control Loop: Elshoff et al. '095 would likely describe the method of an external phase-locked loop for maintaining clock synchronization, which inherently involves an iterative process of:

  • Generating a second clock signal by an adjustable oscillator.
  • Generating a wire rate clock based on the second clock signal.
  • Generating an interim transmitter side clock signal by a serializer.
  • Transmitting clock signals to an external phase detector.
  • Generating an output by the phase detector based on a comparison.
  • Determining adjustment information by a phase controller.
  • Transmitting adjustment information back to the adjustable oscillator.
  • Repeating this loop until the phase difference is below a threshold.

• Combining for Low-Latency HFT: A PHOSITA seeking to improve latency in FPGA-based HFT (as taught by Badizadegan '043) would be motivated to apply the external, iterative phase control methods of Elshoff et al. '095 to the clock signals generated and used within the FPGA transceiver data paths described by Nielson et al. '189. The steps of transmitting the receiver-side clock and the interim transmitter-side clock out of the FPGA to an external phase detector, and then feeding adjustment information back to an external adjustable oscillator that drives the FPGA's transmitter clock, directly implements the external phase control loop of the method claim. This approach directly addresses the latency problem by removing the need for on-chip CDC circuits in the critical path and is a predictable outcome of combining these known techniques.

Therefore, the method claimed in Independent Claim 2, which outlines the iterative external phase control for low-latency clock synchronization in an FPGA for financial trading, would have been obvious to a PHOSITA.

Limitation:
This analysis is based on the general understanding of the cited prior art given their patent numbers and the context of the IPR challenge. A definitive obviousness determination would require a thorough review of the full text of US 2018/0176043 to Badizadegan, US 2018/0227189 to Nielson et al., and US 8,248,095 to Elshoff et al., including their detailed disclosures and claims.