US 10931286

US Patent 10,931,286 (not 10931286) has the following summary:

Title: Field programmable gate array with external phase-locked loop

Assignee: HFT Solutions LLC

Inventor: Nima Badizadegan

Filing Date: July 23, 2020

Issue Date: February 23, 2021

Abstract: The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

Plain-language overview of independent claims:

Independent Claim 1 (System Claim):
This claim describes a Field Programmable Gate Array (FPGA) system designed to achieve phase synchronization with minimal latency. The system includes an FPGA and an external phase control circuit.
The FPGA itself has:

• A first interface with pins for receiving two clock signals (a "first" and a "second" clock signal) and for receiving/transmitting serial data streams.
• A deserializer that converts an incoming serial data stream into parallel data streams and generates a "receiver side clock signal" based on the first input clock.
• Computational circuitry within the FPGA core that processes the parallel data streams.
• A serializer that takes processed parallel data, converts it into a "second serial data stream" for transmission, and generates a "transmitter side clock signal" based on a "first wire rate clock signal."
• A second interface with pins specifically for outputting the receiver side and transmitter side clock signals.
  The external phase control circuit, located outside the FPGA, comprises:
• A phase detector that compares the phases of the receiver side and transmitter side clock signals output from the FPGA and generates a "phase difference indicator signal."
• A phase controller that receives this indicator signal and determines "adjustment information."
• An adjustable oscillator that receives this adjustment information and generates the "second clock signal" which is fed back into the FPGA.
  The core innovation is that the system ensures the receiver side and transmitter side clock signals within the FPGA are phase-aligned to a fixed difference, thereby avoiding the delays typically introduced by conventional clock domain crossing circuits.

Independent Claim 2 (Method Claim):
This claim outlines a method for processing a first serial data stream (e.g., market data) using the described FPGA system to generate a second serial data stream (e.g., order entry data). The method involves:

• Receiving the first serial data stream and a first clock signal by the FPGA's pins.
• Transmitting these to a deserializer within the FPGA.
• The deserializer generates a receiver side clock signal and converts the serial data into parallel data streams.
• These clock and data streams are transmitted to the computational circuitry in the FPGA.
• The receiver side clock signal is also sent out of the FPGA to an external phase detector.
• The system then generates a transmitter side clock signal through an iterative process:
  • An external adjustable oscillator generates a second clock signal.
  • A wire rate clock signal is generated based on this second clock signal.
  • A serializer in the FPGA generates an interim transmitter side clock signal.
  • This interim transmitter side clock signal is sent out to the external phase detector.
  • The phase detector compares the receiver side clock and the interim transmitter side clock, generating an output.
  • An external phase controller uses this output to determine adjustment information.
  • The adjustment information is sent back to the adjustable oscillator, which modifies its output.
  • This loop continues until the phase detector's output indicates the clocks are aligned within a threshold.
• Once aligned, the computational circuitry performs operations (e.g., a trading algorithm) on the parallel data streams to generate processed data.
• This processed data is sent to the serializer, which converts it into the second serial data stream (e.g., trading data).
• Finally, the second serial data stream is transmitted out of the FPGA.
  This method describes how the external phase control loop actively adjusts the transmitter side clock to achieve phase alignment with the receiver side clock without relying on traditional, latency-inducing clock domain crossing operations within the FPGA.

Legal Status and Litigation:
The patent US10931286B1 is Active.
As of April 26, 2026, the Google Patents information (fetched 2026-05-12T23:39:26.722Z) indicates ongoing litigation:

• US case filed in Illinois Northern District Court (Case: 1:24-cv-13213).
• PTAB case IPR2026-00212 filed (Pending).
• US case filed in Texas Western District Court (Case: 7:25-cv-00415).
• US case filed in Illinois Northern District Court (Case: 1:24-cv-13214).
• First worldwide family litigation filed.
  These details suggest active litigation in both District Courts and at the PTAB. There are no direct CAFC 2026 dockets available in the provided Google Patents snippet; the existing cases are at the District Court and PTAB level.